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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc
    from Rev 152 to Rev 153
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Rev 152 → Rev 153

/trunk/VHDL/Open8.vhd
74,9 → 74,6
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/19/06 Design Start
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
-- Seth Henry 06/14/11 Fixed STO instruction to avoid register corruption
-- Fixed interrupt logic to avoid address corruption
-- when interrupt coincides with branch instruction
 
library ieee;
use ieee.std_logic_1164.all;
584,7 → 581,6
signal Pending_D : INTERRUPT_BUNDLE := (others => '0');
signal Pending : INTERRUPT_BUNDLE := (others => '0');
signal Wait_for_FSM : std_logic := '0';
signal Mask : std_logic_vector(6 downto 0) := (others => '0');
signal ISR_D, ISR_Q : ADDRESS_TYPE := (others => '0');
 
type INT_HIST is array (0 to 8) of integer range 0 to 7;
594,13 → 590,13
signal Hist_Ptr : integer range 0 to 8 := 0;
 
begin
Int_Mask <= Mask & '1';
 
ISR <= ISR_Q;
 
Int_Mask_proc: process( Mask, Interrupts, INT_Ctrl )
Int_Mask_proc: process( Int_Mask, Interrupts, INT_Ctrl )
variable S_Mask : std_logic_vector(7 downto 0);
begin
S_Mask := Mask & '1';
S_Mask := Int_Mask;
for i in 0 to 7 loop
i_Ints(i) <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i))
and S_Mask(i);
679,7 → 675,7
Int_Req <= '0';
Pending <= x"00";
Wait_for_FSM <= '0';
Mask <= Default_Interrupt_Mask(7 downto 1);
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
ISR_Q <= INT_VECTOR_0;
for i in 0 to 8 loop
History(i) <= 0;
696,16 → 692,16
elsif( Int_Trig = '1' )then
Wait_for_FSM <= '1';
end if;
if( INT_Ctrl.Mask_Set = '1' )then
Mask <= INT_Ctrl.Mask_Data(7 downto 1);
end if;
ISR_Q <= ISR_D;
if( Int_Trig = '1' )then
History(Hist_Ptr+1) <= Hist_Level;
Hist_Ptr <= Hist_Ptr + 1;
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then
Hist_Ptr <= Hist_Ptr - 1;
end if;
if( INT_Ctrl.Mask_Set = '1' )then
Int_Mask <= INT_Ctrl.Mask_Data(7 downto 1) & '1';
end if;
ISR_Q <= ISR_D;
if( Int_Trig = '1' )then
History(Hist_Ptr+1) <= Hist_Level;
Hist_Ptr <= Hist_Ptr + 1;
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then
Hist_Ptr <= Hist_Ptr - 1;
end if;
end if;
end if;
end process;
1334,10 → 1330,16
-- states to avoid corruption due to incomplete instruction execution
if( Int_Req = '1' )then
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
CPU_Next_State <= ISR_C1;
-- Reset all of the sub-block controls to IDLE, to avoid unintended
-- operation due to the current instruction
ALU_Ctrl.Oper <= ALU_IDLE;
Cache_Ctrl <= CACHE_IDLE;
SP_Ctrl.Oper <= SP_IDLE;
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Oper <= PC_INCR;
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Offset <= x"FF";
CPU_Next_State <= ISR_C1;
 
end if;
end if;
 
/trunk/VHDL/Open8_pkg.vhd
39,7 → 39,7
subtype DATA_TYPE is std_logic_vector(7 downto 0);
-- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
subtype INTERRUPT_BUNDLE is DATA_TYPE;
 
constant DATA_WIDTH : integer := 8;
-- Component declaration
component Open8_CPU is
generic(

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