URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc
- from Rev 161 to Rev 162
- ↔ Reverse comparison
Rev 161 → Rev 162
/trunk/VHDL/Open8.vhd
76,10 → 76,13
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8 |
-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data |
-- corruption issues. |
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data path |
-- sections. |
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data |
-- path sections. |
-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into |
-- single entity. |
-- Seth Henry 09/20/11 Added BRK_Implements_WAI option, allowing the |
-- processor to wait for an interrupt instead of the |
-- normal BRK behavior. |
|
library ieee; |
use ieee.std_logic_1164.all; |
93,6 → 96,7
generic( |
Stack_Start_Addr : ADDRESS_TYPE := x"007F"; -- Top of Stack |
Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP |
BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int |
ISR_Start_Addr : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's |
Program_Start_Addr : ADDRESS_TYPE := x"0090"; -- Initial PC location |
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints |
432,8 → 436,15
SP_Ctrl.Oper <= SP_POP; |
|
when SOP_BRK => |
CPU_Next_State <= BRK_C1; |
PC_Ctrl.Oper <= PC_REV2; |
CPU_Next_State <= BRK_C1; |
PC_Ctrl.Oper <= PC_REV2; |
-- If Break implements Wait for Interrupt |
-- Replace normal flow with a modified |
-- version of INT instruction |
if( BRK_Implements_WAI )then |
CPU_Next_State <= WAIT_FOR_INT; |
PC_Ctrl.Oper <= PC_INCR; |
end if; |
|
when SOP_JMP => |
CPU_Next_State <= JMP_C1; |