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Rev 167 → Rev 166

/trunk/VHDL/o8_alu16.vhd File deleted
/trunk/VHDL/o8_rtc.vhd File deleted
/trunk/VHDL/o8_gpin.vhd File deleted
/trunk/VHDL/o8_gpio.vhd File deleted
/trunk/VHDL/o8_gpout.vhd File deleted
/trunk/VHDL/o8_pit.vhd File deleted
/trunk/VHDL/o8_vdsm8.vhd File deleted
/trunk/VHDL/Open8.vhd
1,4 → 1,4
-- Copyright (c)2006,2013 Jeremy Seth Henry
-- Copyright (c)2006, Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
20,20 → 20,10
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
 
-- VHDL Units : Open8_CPU
-- Description: VHDL model of a RISC 8-bit processor core loosely based on the
-- : V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
-- :
-- Description: VHDL model of the V8 uRISC 8-bit processor core
-- Notes : Generic definitions
-- :
-- : Program_Start_Addr - Determines the initial value of the
-- : program counter.
-- :
-- : ISR_Start_Addr - determines the location of the interrupt
-- : service vector table. There are 8 service vectors, or 16
-- : bytes, which must be allocated to either ROM or RAM.
-- :
-- : Stack_Start_Address - determines the initial (reset) value of
-- : the stack pointer. Also used for the RSP instruction if
-- : Allow_Stack_Address_Move is 0.
42,94 → 32,68
-- : programmed via thet RSP instruction. If enabled, the contents
-- : of R1:R0 are used to initialize the stack pointer.
-- :
-- : The Enable_Auto_Increment generic can be used to modify the
-- : indexed instructions such that specifying an odd register
-- : will use the next lower register pair, post-incrementing the
-- : value in that pair. IOW, specifying STX R1 will instead
-- : result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
-- : ISR_Start_Addr - determines the location of the interrupt
-- : service vector table. There are 8 service vectors, or 16
-- : bytes, which must be allocated to either ROM or RAM.
-- :
-- : BRK_Implements_WAI modifies the BRK instruction such that it
-- : triggers the wait for interrupt state, but without triggering
-- : a soft interrupt in lieu of its normal behavior, which is to
-- : insert several dead clock cycles - essentially a long NOP
-- : Program_Start_Addr - Determines the initial value of the
-- : program counter.
-- :
-- : Enable_NMI overrides the mask bit for interrupt 0, creating a
-- : non-maskable interrupt at the highest priority.
-- :
-- : Default_Interrupt_Mask - Determines the intial value of the
-- : interrupt mask. To remain true to the original core, which
-- : had no interrupt mask, this should be set to x"FF". Otherwise
-- : it can be initialized to any value. Enable_NMI will logically
-- : force the LSB high.
-- :
-- : Reset_Level - Determines whether the processor registers reset
-- : on a high or low level from higher logic.
-- : it can be initialized to any value.
-- :
-- : Architecture notes
-- : This model deviates from the original ISA in a few important
-- : ways.
-- : Enable_CPU_Halt - determines whether the CPU_Halt pin is
-- : connected or not. This signal is typically used to halt the
-- : processor for a few cycles when accessing slower peripherals,
-- : but may also be used to single step the processor. If this
-- : feature isn't used, it can be disabled to increase Fmax.
-- :
-- : First, there is only one set of registers. Interrupt service
-- : routines must explicitely preserve context since the the
-- : hardware doesn't. This was done to decrease size and code
-- : complexity. Older code that assumes this behavior will not
-- : execute correctly on this processor model.
-- : The CPU_Halt signal can be used to access slower peripherals
-- : by allowing the device to "pause" the CPU. This can be used,
-- : for example, to write to a standard LCD panel, which requires
-- : a 4MHz interface, by halting on writes. Alternately, devices
-- : such as SDRAM controllers, can pause the processor until the
-- : data is ready to be presented.
-- :
-- : Second, this model adds an additional pipeline stage between
-- : the instruction decoder and the ALU. Unfortunately, this
-- : means that the instruction stream has to be restarted after
-- : any math instruction is executed, implying that any ALU
-- : instruction now has a latency of 2 instead of 0. The
-- : advantage is that the maximum frequency has gone up
-- : significantly, as the ALU code is vastly more efficient.
-- : As an aside, this now means that all math instructions,
-- : including MUL (see below) and UPP have the same instruction
-- : latency.
-- : The Enable_Auto_Increment generic can be used to modify the
-- : indexed instructions such that specifying an odd register
-- : will use the next lower register pair, post-incrementing the
-- : value in that pair. IOW, specifying STX R1 will instead
-- : result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
-- :
-- : Third, the original ISA, also a soft core, had two reserved
-- : instructions, USR and USR2. These have been implemented as
-- : DBNZ, and MUL respectively.
-- : Instructions USR and USR2 have been replaced with DBNZ, and MUL
-- : respectively. DBNZ decrements the specified register, and will
-- : branch if the result is non-zero (Zero flag is not set). MUL
-- : places the result of R0 * Rn into R1:R0, and executes in two
-- : cycles. (R1:R0 = R0 * Rn)
-- :
-- : DBNZ decrements the specified register and branches if the
-- : result is non-zero. The instruction effectively executes a
-- : DEC Rn instruction prior to branching, so the same flags will
-- : be set.
-- :
-- : MUL places the result of R0 * Rn into R1:R0. Instruction
-- : latency is identical to other ALU instructions. Only the Z
-- : flag is set, since there is no defined overflow or "negative
-- : 16-bit values"
-- :
-- : Fourth, indexed load/store instructions now have an (optional)
-- : ability to post-increment their index registers. If enabled,
-- : using an odd operand for LDO,LDX, STO, STX will cause the
-- : register pair to be incremented after the storage access.
-- :
-- : Fifth, the RSP instruction has been (optionally) altered to
-- : allow the stack pointer to be sourced from R1:R0.
-- :
-- : Sixth, the BRK instruction can optionally implement a WAI,
-- : which is the same as the INT instruction without the soft
-- : interrupt, as a way to put the processor to "sleep" until the
-- : next interrupt.
-- :
-- : Seventh, the original CPU model had 8 non-maskable interrupts
-- : with priority. This model has the same 8 interrupts, but
-- : allows software to mask them (with an additional option to
-- : override the highest priority interrupt, making it the NMI.)
-- : The interrupt code will retain memory of lower priority
-- : interrupts, and execute them as it can.
-- :
-- : Lastly, previous unmapped instructions in the OP_STK opcode
-- : were repurposed to support a new interrupt mask.
-- : SMSK and GMSK transfer the contents of R0 (accumulator)
-- : to/from the interrupt mask register. SMSK is immediate, while
-- : GMSK has the same overhead as a math instruction.
-- : BRK_Implements_WAI modifies the BRK instruction such that it
-- : triggers the wait for interrupt state, but without triggering
-- : a soft interrupt in lieu of its normal behavior, which is to
-- : insert several dead clock cycles - essentially a long NOP
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/19/06 Design Start
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data
-- corruption issues.
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data
-- path sections.
-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into
-- single entity.
-- Seth Henry 09/20/11 Added BRK_Implements_WAI option, allowing the
-- processor to wait for an interrupt instead of the
-- normal BRK behavior.
-- Seth Henry 12/20/11 Modified core to allow WAIT_FOR_INT state to idle
-- the bus entirely (Rd_Enable is low)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
 
library work;
use work.Open8_pkg.all;
136,18 → 100,19
 
entity Open8_CPU is
generic(
Program_Start_Addr : ADDRESS_TYPE := x"0090"; -- Initial PC location
ISR_Start_Addr : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
Stack_Start_Addr : ADDRESS_TYPE := x"007F"; -- Top of Stack
Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
Enable_Auto_Increment : boolean := false; -- Modify indexed instr
BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
Enable_NMI : boolean := true; -- force mask for int 0
ISR_Start_Addr : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
Program_Start_Addr : ADDRESS_TYPE := x"0090"; -- Initial PC location
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
Enable_CPU_Halt : boolean := false; -- Disable HALT pin
Enable_Auto_Increment : boolean := false; -- Modify indexed instr
Reset_Level : std_logic := '0' ); -- Active reset level
port(
Clock : in std_logic;
Reset : in std_logic;
CPU_Halt : in std_logic := '0';
Interrupts : in INTERRUPT_BUNDLE;
--
Address : out ADDRESS_TYPE;
162,8 → 127,7
subtype OPCODE_TYPE is std_logic_vector(4 downto 0);
subtype SUBOP_TYPE is std_logic_vector(2 downto 0);
 
-- All opcodes should be identical to the opcode used by the assembler
-- In this case, they match the original V8/ARC uRISC ISA
-- These are all the primary instructions/op-codes (upper 5-bits)
constant OP_INC : OPCODE_TYPE := "00000";
constant OP_ADC : OPCODE_TYPE := "00001";
constant OP_TX0 : OPCODE_TYPE := "00010";
184,9 → 148,9
constant OP_POP : OPCODE_TYPE := "10001";
constant OP_BR0 : OPCODE_TYPE := "10010";
constant OP_BR1 : OPCODE_TYPE := "10011";
constant OP_DBNZ : OPCODE_TYPE := "10100";
constant OP_DBNZ : OPCODE_TYPE := "10100"; -- USR
constant OP_INT : OPCODE_TYPE := "10101";
constant OP_MUL : OPCODE_TYPE := "10110";
constant OP_MUL : OPCODE_TYPE := "10110"; -- USR2
constant OP_STK : OPCODE_TYPE := "10111";
constant OP_UPP : OPCODE_TYPE := "11000";
constant OP_STA : OPCODE_TYPE := "11001";
197,9 → 161,7
constant OP_LDX : OPCODE_TYPE := "11110";
constant OP_LDO : OPCODE_TYPE := "11111";
 
-- OP_STK uses the lower 3 bits to further refine the instruction by
-- repurposing the source register field. These "sub opcodes" are
-- take the place of the register select for the OP_STK opcode
-- These are all specific sub-opcodes for OP_STK / 0xB8 (lower 3-bits)
constant SOP_RSP : SUBOP_TYPE := "000";
constant SOP_RTS : SUBOP_TYPE := "001";
constant SOP_RTI : SUBOP_TYPE := "010";
209,18 → 171,18
constant SOP_GMSK : SUBOP_TYPE := "110";
constant SOP_JSR : SUBOP_TYPE := "111";
 
-- Preinitialization is for simulation only - check actual reset conditions
type CPU_STATES is (
-- Instruction fetch & Decode
PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
-- Branching
BRN_C1, DBNZ_C1, DBNZ_C2, JMP_C1, JMP_C2,
BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
-- Loads
LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1, LDO_C1, LDX_C1, LDX_C2, LDX_C3,
-- Stores
STA_C1, STA_C2, STO_C1, STO_C2, STX_C1, STX_C2,
-- math
MATH_C1, GMSK_C1, MUL_C1, UPP_C1,
STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
-- 2-cycle math
MUL_C1, UPP_C1,
-- Stack
PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
-- Subroutines & Interrupts
229,11 → 191,53
-- Debugging
BRK_C1 );
 
-- To simplify the logic, the first 16 of these should exactly match their
-- corresponding Opcodes. This allows the state logic to simply pass the
-- opcode field to the ALU for most math operations.
type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
CACHE_PREFETCH );
 
type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD );
 
type PC_CTRL_TYPE is record
Oper : PC_MODES;
Offset : DATA_TYPE;
Addr : ADDRESS_TYPE;
end record;
 
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
 
type SP_CTRL_TYPE is record
Oper : SP_MODES;
Addr : ADDRESS_TYPE;
end record;
 
type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
 
type DATA_CTRL_TYPE is record
Src : DP_MODES;
Reg : SUBOP_TYPE;
end record;
 
-- Preinitialization is for simulation only - check actual reset conditions
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
 
type INT_CTRL_TYPE is record
Mask_Set : std_logic;
Soft_Ints : INTERRUPT_BUNDLE;
Incr_ISR : std_logic;
end record;
 
type INT_HIST is array (0 to 8) of integer range 0 to 7;
 
-- Most of the ALU instructions are the same as their Opcode equivalents with
-- three exceptions (for IDLE, UPP2, and MUL2)
constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00"
constant ALU_UPP1 : OPCODE_TYPE := "00000"; -- Alias of ALU_INC
constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01"
constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02"
constant ALU_OR : OPCODE_TYPE := "00011"; -- x"03"
249,12 → 253,16
constant ALU_CLP : OPCODE_TYPE := "01101"; -- x"0D"
constant ALU_T0X : OPCODE_TYPE := "01110"; -- x"0E"
constant ALU_CMP : OPCODE_TYPE := "01111"; -- x"0F"
constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"11"
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"12"
constant ALU_POP : OPCODE_TYPE := "10001"; -- x"11"
constant ALU_MUL : OPCODE_TYPE := "10110"; -- x"16"
constant ALU_UPP : OPCODE_TYPE := "11000"; -- x"18"
constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C"
constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E"
 
constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"12"
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"13"
 
constant FL_ZERO : integer := 0;
constant FL_CARRY : integer := 1;
constant FL_NEG : integer := 2;
264,1033 → 272,1082
constant FL_GP3 : integer := 6;
constant FL_GP4 : integer := 7;
 
type ALU_CTRL_TYPE is record
Oper : OPCODE_TYPE;
Reg : SUBOP_TYPE;
Data : DATA_TYPE;
end record;
 
constant ACCUM : SUBOP_TYPE := "000";
constant INT_FLAG : SUBOP_TYPE := "011";
 
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
 
subtype FLAG_TYPE is DATA_TYPE;
 
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr + 0;
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr + 2;
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr + 4;
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr + 6;
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr + 8;
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr + 10;
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr + 12;
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr + 14;
signal Halt : std_logic;
 
type CPU_CTRL_TYPE is record
State : CPU_STATES;
LS_Address : ADDRESS_TYPE;
Program_Ctr : ADDRESS_TYPE;
Stack_Ptr : ADDRESS_TYPE;
Opcode : OPCODE_TYPE;
SubOp_p0 : SUBOP_TYPE;
SubOp_p1 : SUBOP_TYPE;
Cache_Valid : std_logic;
Prefetch : DATA_TYPE;
Operand1 : DATA_TYPE;
Operand2 : DATA_TYPE;
AutoIncr : std_logic;
A_Oper : OPCODE_TYPE;
A_Reg : SUBOP_TYPE;
A_Data : DATA_TYPE;
A_NoFlags : std_logic;
M_Reg : SUBOP_TYPE;
M_Prod : ADDRESS_TYPE;
Regfile : REGFILE_TYPE;
Flags : FLAG_TYPE;
Int_Mask : DATA_TYPE;
Int_Addr : ADDRESS_TYPE;
Int_Pending : DATA_TYPE;
Int_Level : integer range 0 to 7;
Wait_for_FSM : std_logic;
end record;
signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
signal CPU_State : CPU_STATES := PIPE_FILL_0;
 
signal CPU : CPU_CTRL_TYPE;
signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
 
alias Accumulator is CPU.Regfile(0);
alias Flags is CPU.Flags;
signal Opcode : OPCODE_TYPE := (others => '0');
signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0');
 
signal Ack_Q, Ack_Q1 : std_logic;
signal Int_Req, Int_Ack : std_logic;
signal Prefetch : DATA_TYPE := x"00";
signal Operand1, Operand2 : DATA_TYPE := x"00";
 
type IC_MODES is ( CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
CACHE_PREFETCH, CACHE_PFFLUSH, CACHE_INVALIDATE );
signal Instr_Prefetch : std_logic := '0';
 
type PC_MODES is ( PC_INCR, PC_IDLE, PC_REV1, PC_REV2, PC_REV3,
PC_BRANCH, PC_LOAD );
signal PC_Ctrl : PC_CTRL_TYPE;
signal Program_Ctr : ADDRESS_TYPE := x"0000";
 
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
signal SP_Ctrl : SP_CTRL_TYPE;
signal Stack_Ptr : ADDRESS_TYPE := x"0000";
 
type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
signal DP_Ctrl : DATA_CTRL_TYPE;
 
type DP_CTRL_TYPE is record
Src : DP_MODES;
Reg : SUBOP_TYPE;
end record;
signal INT_Ctrl : INT_CTRL_TYPE;
signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
signal Int_RTI_D, Int_RTI : std_logic := '0';
signal Int_Req, Int_Ack : std_logic := '0';
signal Int_Mask : DATA_TYPE := x"00";
signal ISR_Addr : ADDRESS_TYPE := x"0000";
signal i_Ints : INTERRUPT_BUNDLE := x"00";
signal Pending : INTERRUPT_BUNDLE := x"00";
signal Wait_for_FSM : std_logic := '0';
signal History : INT_HIST := (others => 0);
signal Hst_Ptr : integer range 0 to 8 := 0;
 
type INT_CTRL_TYPE is record
Mask_Set : std_logic;
Soft_Ints : INTERRUPT_BUNDLE;
Incr_ISR : std_logic;
end record;
signal ALU_Ctrl : ALU_CTRL_TYPE;
signal Regfile : REGFILE_TYPE;
signal Flags : FLAG_TYPE;
signal Mult : ADDRESS_TYPE := x"0000";
 
begin
 
Address_Sel: process( CPU )
variable Offset_SX : ADDRESS_TYPE;
begin
Offset_SX(15 downto 8) := (others => CPU.Operand1(7));
Offset_SX(7 downto 0) := CPU.Operand1;
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate
Halt <= '0';
end generate;
 
case( CPU.State )is
when LDO_C1 | LDX_C1 | STO_C1 | STX_C1 =>
Address <= CPU.LS_Address + Offset_SX;
when LDA_C2 | STA_C2 =>
Address <= (CPU.Operand2 & CPU.Operand1);
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 |
RTS_C1 | RTS_C2 | RTS_C3 =>
Address <= CPU.Stack_Ptr;
when ISR_C1 | ISR_C2 =>
Address <= CPU.Int_Addr;
when others =>
Address <= CPU.Program_Ctr;
end case;
end process;
Halt_Enabled_fn: if( Enable_CPU_Halt )generate
Halt <= CPU_Halt;
end generate;
 
CPU_Proc: process( Clock, Reset )
variable IC : IC_MODES;
variable PC : PC_MODES;
variable SP : SP_MODES;
variable DP : DP_CTRL_TYPE;
variable INT : INT_CTRL_TYPE;
variable RegSel : integer range 0 to 7;
variable Reg_l, Reg_u : integer range 0 to 7;
variable Ack_D : std_logic;
-------------------------------------------------------------------------------
-- State Logic / Instruction Decoding & Execution
-- Combinatorial portion of CPU finite state machine
-------------------------------------------------------------------------------
 
State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode,
SubOp , SubOp_p1, Operand1, Operand2, Int_Req,
Program_Ctr, Stack_Ptr, ISR_Addr )
variable Reg, Reg_1 : integer range 0 to 7 := 0;
variable Offset_SX : ADDRESS_TYPE;
variable Index : integer range 0 to 7;
variable Temp : std_logic_vector(8 downto 0);
begin
if( Reset = Reset_Level )then
CPU.State <= PIPE_FILL_0;
CPU.LS_Address <= (others => '0');
CPU.Program_Ctr <= Program_Start_Addr;
CPU.Stack_Ptr <= Stack_Start_Addr;
CPU.Opcode <= (others => '0');
CPU.SubOp_p0 <= (others => '0');
CPU.SubOp_p1 <= (others => '0');
CPU.Prefetch <= (others => '0');
CPU.Operand1 <= (others => '0');
CPU.Operand2 <= (others => '0');
CPU.AutoIncr <= '0';
CPU.Cache_Valid <= '0';
CPU.A_Oper <= ALU_IDLE;
CPU.A_Reg <= ACCUM;
CPU.A_Data <= x"00";
CPU.A_NoFlags <= '0';
CPU.M_Reg <= (others => '0');
for i in 0 to 7 loop
CPU.Regfile(i) <= x"00";
end loop;
CPU.Flags <= (others => '0');
if( Enable_NMI )then
CPU.Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
else
CPU.Int_Mask <= Default_Interrupt_Mask;
end if;
CPU.Int_Addr <= (others => '0');
CPU.Int_Pending <= (others => '0');
CPU.Int_Level <= 7;
CPU.Wait_for_FSM <= '0';
CPU_Next_State <= CPU_State;
Cache_Ctrl <= CACHE_IDLE;
--
ALU_Ctrl.Oper <= ALU_IDLE;
ALU_Ctrl.Reg <= ACCUM;
ALU_Ctrl.Data <= x"00";
--
PC_Ctrl.Oper <= PC_IDLE;
PC_Ctrl.Offset <= x"03";
PC_Ctrl.Addr <= x"0000";
--
SP_Ctrl.Oper <= SP_IDLE;
--
Address <= Program_Ctr;
--
DP_Ctrl.Src <= DATA_RD_MEM;
DP_Ctrl.Reg <= ACCUM;
--
INT_Ctrl.Mask_Set <= '0';
INT_Ctrl.Soft_Ints <= x"00";
INT_Ctrl.Incr_ISR <= '0';
Ack_D <= '0';
Int_RTI_D <= '0';
 
Ack_Q <= '0';
Ack_Q1 <= '0';
Int_Ack <= '0';
Int_Req <= '0';
-- Assign the most common value of Reg and Reg1 outside the case structure
-- to simplify things.
Reg := conv_integer(SubOp);
Reg_1 := conv_integer(SubOp_p1);
Offset_SX(15 downto 0) := (others => Operand1(7));
Offset_SX(7 downto 0) := Operand1;
 
Wr_Data <= x"00";
Wr_Enable <= '0';
Rd_Enable <= '1';
elsif( rising_edge(Clock) )then
case CPU_State is
-------------------------------------------------------------------------------
-- Initial Instruction fetch & decode
-------------------------------------------------------------------------------
when PIPE_FILL_0 =>
CPU_Next_State <= PIPE_FILL_1;
PC_Ctrl.Oper <= PC_INCR;
 
IC := CACHE_IDLE;
SP := SP_IDLE;
DP.Src := DATA_RD_MEM;
DP.Reg := ACCUM;
Ack_D := '0';
INT.Mask_Set := '0';
INT.Soft_Ints := x"00";
INT.Incr_ISR := '0';
RegSel := conv_integer(CPU.SubOp_p0);
when PIPE_FILL_1 =>
CPU_Next_State <= PIPE_FILL_2;
PC_Ctrl.Oper <= PC_INCR;
 
if( Enable_Auto_Increment )then
Reg_l := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
Reg_u := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
else
Reg_l := conv_integer(CPU.SubOp_p0);
Reg_u := conv_integer(CPU.SubOp_p1);
end if;
when PIPE_FILL_2 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
 
CPU.LS_Address <= CPU.Regfile(Reg_u) & CPU.Regfile(Reg_l);
when INSTR_DECODE =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
 
CPU.AutoIncr <= '0';
if( Enable_Auto_Increment )then
CPU.AutoIncr <= CPU.SubOp_p0(0);
end if;
case Opcode is
when OP_PSH =>
CPU_Next_State <= PSH_C1;
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_REV1;
DP_Ctrl.Src <= DATA_WR_REG;
DP_Ctrl.Reg <= SubOp;
 
CPU.A_Oper <= ALU_IDLE;
CPU.A_Reg <= ACCUM;
CPU.A_Data <= x"00";
CPU.A_NoFlags <= '0';
when OP_POP =>
CPU_Next_State <= POP_C1;
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_REV2;
SP_Ctrl.Oper <= SP_POP;
 
case( CPU.State )is
when PIPE_FILL_0 =>
PC := PC_INCR;
CPU.State <= PIPE_FILL_1;
when OP_BR0 | OP_BR1 =>
CPU_Next_State <= BRN_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_INCR;
 
when PIPE_FILL_1 =>
PC := PC_INCR;
CPU.State <= PIPE_FILL_2;
when OP_DBNZ =>
CPU_Next_State <= DBNZ_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_DEC;
ALU_Ctrl.Reg <= SubOp;
 
when PIPE_FILL_2 =>
IC := CACHE_INSTR;
PC := PC_INCR;
CPU.State <= INSTR_DECODE;
when OP_INT =>
PC_Ctrl.Oper <= PC_INCR;
-- Make sure the requested interrupt is actually enabled first
if( Int_Mask(Reg) = '1' )then
CPU_Next_State <= WAIT_FOR_INT;
INT_Ctrl.Soft_Ints(Reg) <= '1';
end if;
 
-------------------------------------------------------------------------------
-- Instruction Decode and dispatch
-------------------------------------------------------------------------------
when OP_STK =>
case SubOp is
when SOP_RSP =>
PC_Ctrl.Oper <= PC_INCR;
SP_Ctrl.Oper <= SP_RSET;
 
when INSTR_DECODE =>
IC := CACHE_INSTR;
PC := PC_INCR;
case CPU.Opcode is
when OP_PSH =>
IC := CACHE_PREFETCH;
PC := PC_IDLE;
DP.Src := DATA_WR_REG;
DP.Reg := CPU.SubOp_p0;
CPU.State <= PSH_C1;
when SOP_RTS | SOP_RTI =>
CPU_Next_State <= RTS_C1;
Cache_Ctrl <= CACHE_IDLE;
SP_Ctrl.Oper <= SP_POP;
 
when OP_POP =>
IC := CACHE_PREFETCH;
PC := PC_REV2;
SP := SP_POP;
CPU.State <= POP_C1;
when SOP_BRK =>
CPU_Next_State <= BRK_C1;
PC_Ctrl.Oper <= PC_REV2;
-- If Break implements Wait for Interrupt
-- Replace normal flow with a modified
-- version of INT instruction
if( BRK_Implements_WAI )then
CPU_Next_State <= WAIT_FOR_INT;
PC_Ctrl.Oper <= PC_INCR;
end if;
 
when OP_BR0 | OP_BR1 =>
IC := CACHE_OPER1;
CPU.State <= BRN_C1;
when SOP_JMP =>
CPU_Next_State <= JMP_C1;
Cache_Ctrl <= CACHE_OPER1;
 
when OP_DBNZ =>
IC := CACHE_OPER1;
CPU.A_Oper <= ALU_DEC;
CPU.A_Reg <= CPU.SubOp_p0;
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= DBNZ_C1;
when SOP_SMSK =>
PC_Ctrl.Oper <= PC_INCR;
INT_Ctrl.Mask_Set <= '1';
 
when OP_INT =>
if( CPU.Int_Mask(RegSel) = '1' )then
CPU.State <= WAIT_FOR_INT;
INT.Soft_Ints(RegSel) := '1';
end if;
when SOP_GMSK =>
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper<= ALU_LDI;
ALU_Ctrl.Reg <= ACCUM;
ALU_Ctrl.Data<= Int_Mask;
 
when OP_STK =>
case CPU.SubOp_p0 is
when SOP_RSP =>
SP := SP_RSET;
when SOP_JSR =>
CPU_Next_State <= JSR_C1;
Cache_Ctrl <= CACHE_OPER1;
DP_Ctrl.Src <= DATA_WR_PC;
DP_Ctrl.Reg <= ACCUM+1;
 
when SOP_RTS | SOP_RTI =>
IC := CACHE_IDLE;
PC := PC_IDLE;
SP := SP_POP;
CPU.State <= RTS_C1;
when others => null;
end case;
 
when SOP_BRK =>
if( BRK_Implements_WAI )then
CPU.State<= WAIT_FOR_INT;
else
PC := PC_REV2;
CPU.State<= BRK_C1;
end if;
when OP_MUL =>
CPU_Next_State <= MUL_C1;
Cache_Ctrl <= CACHE_PREFETCH;
 
when SOP_JMP =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= JMP_C1;
-- We need to back the PC up by 1, and allow it to refill. An
-- unfortunate consequence of the pipelining. We can get away with
-- only 1 extra clock by pre-fetching the next instruction, though
PC_Ctrl.Oper <= PC_REV1;
-- Multiplication is automatic, but requires a single clock cycle.
-- We need to specify the register for Rn (R1:R0 = R0 * Rn) now,
-- but will issue the multiply command on the next clock to copy
-- the results to the specified register.
ALU_Ctrl.Oper <= ALU_IDLE;
ALU_Ctrl.Reg <= SubOp; -- Rn
 
when SOP_SMSK =>
INT.Mask_Set := '1';
when OP_UPP =>
CPU_Next_State <= UPP_C1;
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_REV1;
ALU_Ctrl.Oper <= Opcode;
ALU_Ctrl.Reg <= SubOp;
 
when SOP_GMSK =>
IC := CACHE_PREFETCH;
PC := PC_REV1;
CPU.State <= GMSK_C1;
when OP_LDA =>
CPU_Next_State <= LDA_C1;
Cache_Ctrl <= CACHE_OPER1;
 
when SOP_JSR =>
IC := CACHE_OPER1;
PC := PC_IDLE;
DP.Src := DATA_WR_PC;
DP.Reg := ACCUM+1;
CPU.State <= JSR_C1;
when OP_LDI =>
CPU_Next_State <= LDI_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_INCR;
 
when others => null;
end case;
when OP_LDO =>
CPU_Next_State <= LDO_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_REV2;
 
when OP_MUL =>
IC := CACHE_PREFETCH;
PC := PC_REV1;
CPU.M_Reg <= CPU.SubOp_p0;
CPU.State <= MUL_C1;
when OP_LDX =>
CPU_Next_State <= LDX_C1;
PC_Ctrl.Oper <= PC_REV2;
-- If auto-increment is disabled, use the specified register pair,
-- otherwise, for an odd:even pair, and issue the first half of
-- a UPP instruction to the ALU
if( not Enable_Auto_Increment )then
Address <= Regfile(Reg_1) & Regfile(Reg);
else
Reg := conv_integer(SubOp(2 downto 1) & '0');
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
Address <= Regfile(Reg_1) & Regfile(Reg);
if( SubOp(0) = '1' )then
ALU_Ctrl.Oper<= ALU_UPP;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
end if;
end if;
 
when OP_UPP =>
IC := CACHE_PREFETCH;
PC := PC_REV1;
CPU.A_Oper <= ALU_UPP1;
CPU.A_NoFlags <= '1';
CPU.A_Reg <= CPU.SubOp_p0;
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= UPP_C1;
when OP_STA =>
CPU_Next_State <= STA_C1;
Cache_Ctrl <= CACHE_OPER1;
 
when OP_LDA =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= LDA_C1;
when OP_STO =>
CPU_Next_State <= STO_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_REV2;
DP_Ctrl.Src <= DATA_WR_REG;
DP_Ctrl.Reg <= ACCUM;
 
when OP_LDI =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= LDI_C1;
when OP_STX =>
CPU_Next_State <= STX_C1;
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_REV2;
DP_Ctrl.Src <= DATA_WR_REG;
DP_Ctrl.Reg <= ACCUM;
 
when OP_LDO =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= LDO_C1;
when others =>
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= Opcode;
ALU_Ctrl.Reg <= SubOp;
 
when OP_LDX =>
IC := CACHE_PFFLUSH;
PC := PC_REV1;
CPU.State <= LDX_C1;
end case;
 
when OP_STA =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= STA_C1;
 
when OP_STO =>
IC := CACHE_OPER1;
PC := PC_REV2;
DP.Src := DATA_WR_REG;
DP.Reg := ACCUM;
CPU.State <= STO_C1;
 
when OP_STX =>
IC := CACHE_PFFLUSH;
PC := PC_REV2;
DP.Src := DATA_WR_REG;
DP.Reg := ACCUM;
CPU.State <= STX_C1;
 
when others =>
IC := CACHE_PREFETCH;
PC := PC_REV1;
CPU.State <= MATH_C1;
 
end case;
 
-------------------------------------------------------------------------------
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
-------------------------------------------------------------------------------
 
when BRN_C1 =>
if( Flags(RegSel) = CPU.Opcode(0) )then
IC := CACHE_IDLE;
PC := PC_BRANCH;
CPU.State <= PIPE_FILL_0;
else
IC := CACHE_INSTR;
CPU.State <= INSTR_DECODE;
end if;
when BRN_C1 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
if( Flags(Reg) = Opcode(0) )then
CPU_Next_State <= PIPE_FILL_0;
Cache_Ctrl <= CACHE_IDLE;
PC_Ctrl.Offset <= Operand1;
end if;
 
when DBNZ_C1 =>
IC := CACHE_PREFETCH;
PC := PC_IDLE;
CPU.State <= DBNZ_C2;
when DBNZ_C1 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
if( Flags(FL_ZERO) = '0' )then
CPU_Next_State <= PIPE_FILL_0;
Cache_Ctrl <= CACHE_IDLE;
PC_Ctrl.Offset <= Operand1;
end if;
 
when DBNZ_C2 =>
if( Flags(FL_ZERO) = '0' )then
IC := CACHE_INVALIDATE;
PC := PC_BRANCH;
CPU.State <= PIPE_FILL_0;
else
PC := PC_REV1;
CPU.State <= PIPE_FILL_1;
end if;
when JMP_C1 =>
CPU_Next_State <= JMP_C2;
Cache_Ctrl <= CACHE_OPER2;
 
when JMP_C1 =>
IC := CACHE_OPER2;
PC := PC_IDLE;
CPU.State <= JMP_C2;
when JMP_C2 =>
CPU_Next_State <= PIPE_FILL_0;
PC_Ctrl.Oper <= PC_LOAD;
PC_Ctrl.Addr <= Operand2 & Operand1;
 
when JMP_C2 =>
PC := PC_LOAD;
CPU.State <= PIPE_FILL_0;
 
-------------------------------------------------------------------------------
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
-------------------------------------------------------------------------------
 
when LDA_C1 =>
IC := CACHE_OPER2;
PC := PC_IDLE;
CPU.State <= LDA_C2;
when LDA_C1 =>
CPU_Next_State <= LDA_C2;
Cache_Ctrl <= CACHE_OPER2;
 
when LDA_C2 =>
PC := PC_IDLE;
CPU.State <= LDA_C3;
when LDA_C2 =>
CPU_Next_State <= LDA_C3;
Address <= Operand2 & Operand1;
 
when LDA_C3 =>
PC := PC_IDLE;
CPU.State <= LDA_C4;
when LDA_C3 =>
CPU_Next_State <= LDA_C4;
PC_Ctrl.Oper <= PC_INCR;
 
when LDA_C4 =>
IC := CACHE_OPER1;
PC := PC_INCR;
CPU.State <= LDI_C1;
when LDA_C4 =>
CPU_Next_State <= LDI_C1;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_INCR;
 
when LDI_C1 =>
IC := CACHE_PREFETCH;
PC := PC_INCR;
CPU.A_Oper <= ALU_LDI;
CPU.A_Reg <= CPU.SubOp_p0;
CPU.A_Data <= CPU.Operand1;
CPU.State <= PIPE_FILL_2;
when LDI_C1 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_LDI;
ALU_Ctrl.Reg <= SubOp;
ALU_Ctrl.Data <= Operand1;
 
when LDO_C1 =>
IC := CACHE_PREFETCH;
PC := PC_REV2;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
CPU.A_Oper <= ALU_UPP1;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
CPU.A_NoFlags <= '1';
CPU.A_Data <= CPU.RegFile(RegSel);
when LDO_C1 =>
CPU_Next_State <= LDX_C1;
PC_Ctrl.Oper <= PC_INCR;
if( Enable_Auto_Increment )then
Reg := conv_integer(SubOp(2 downto 1) & '0');
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
if( SubOp(0) = '1' )then
ALU_Ctrl.Oper<= ALU_UPP;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
end if;
CPU.State <= LDX_C2;
else
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
end if;
 
when LDX_C1 =>
PC := PC_REV2;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
CPU.A_Oper <= ALU_UPP1;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
CPU.A_NoFlags <= '1';
CPU.A_Data <= CPU.Regfile(RegSel);
end if;
CPU.State <= LDX_C2;
when LDX_C1 =>
CPU_Next_State <= LDX_C2;
PC_Ctrl.Oper <= PC_INCR;
 
when LDX_C2 =>
PC := PC_INCR;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
CPU.A_Oper <= ALU_UPP2;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
CPU.A_Data <= CPU.Regfile(RegSel);
end if;
CPU.State <= LDX_C3;
when LDX_C2 =>
CPU_Next_State <= LDX_C3;
PC_Ctrl.Oper <= PC_INCR;
Cache_Ctrl <= CACHE_OPER1;
 
when LDX_C3 =>
IC := CACHE_OPER1;
PC := PC_INCR;
CPU.State <= LDX_C4;
when LDX_C3 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_LDX;
ALU_Ctrl.Reg <= ACCUM;
ALU_Ctrl.Data <= Operand1;
 
when LDX_C4 =>
PC := PC_INCR;
CPU.A_Oper <= ALU_LDI;
CPU.A_Reg <= ACCUM;
CPU.A_Data <= CPU.Operand1;
CPU.State <= PIPE_FILL_2;
 
-------------------------------------------------------------------------------
-- Data Storage - Store to memory (STA, STO, STX)
-------------------------------------------------------------------------------
when STA_C1 =>
IC := CACHE_OPER2;
PC := PC_IDLE;
DP.Src := DATA_WR_REG;
DP.Reg := CPU.SubOp_p0;
CPU.State <= STA_C2;
when STA_C1 =>
CPU_Next_State <= STA_C2;
Cache_Ctrl <= CACHE_OPER2;
DP_Ctrl.Src <= DATA_WR_REG;
DP_Ctrl.Reg <= SubOp;
 
when STA_C2 =>
IC := CACHE_PREFETCH;
PC := PC_INCR;
CPU.State <= PIPE_FILL_1;
when STA_C2 =>
CPU_Next_State <= STA_C3;
Address <= Operand2 & Operand1;
PC_Ctrl.Oper <= PC_INCR;
 
when STO_C1 =>
IC := CACHE_PREFETCH;
PC := PC_INCR;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
if( not Enable_Auto_Increment )then
CPU.State <= PIPE_FILL_1;
else
CPU.State <= PIPE_FILL_0;
if( CPU.AutoIncr = '1' )then
CPU.A_Oper <= ALU_UPP1;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
CPU.A_NoFlags <= '1';
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= STO_C2;
end if;
when STA_C3 =>
CPU_Next_State <= PIPE_FILL_2;
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_INCR;
 
when STO_C1 =>
Cache_Ctrl <= CACHE_PREFETCH;
PC_Ctrl.Oper <= PC_INCR;
-- If auto-increment is disabled, just load the registers normally
if( not Enable_Auto_Increment )then
CPU_Next_State <= PIPE_FILL_1;
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
-- Otherwise, enforce the even register rule, and check the LSB to see
-- if we should perform the auto-increment on the register pair
else
CPU_Next_State <= PIPE_FILL_0;
Reg := conv_integer(SubOp(2 downto 1) & '0');
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
if( SubOp(0) = '1' )then
CPU_Next_State <= STO_C2;
ALU_Ctrl.Oper <= ALU_UPP;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
end if;
end if;
 
when STO_C2 =>
PC := PC_INCR;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
CPU.A_Oper <= ALU_UPP2;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= PIPE_FILL_1;
when STO_C2 =>
CPU_Next_State <= PIPE_FILL_1;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_UPP2;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
 
when STX_C1 =>
PC := PC_INCR;
if( not Enable_Auto_Increment )then
CPU.State <= PIPE_FILL_1;
else
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
CPU.State <= PIPE_FILL_1;
if( CPU.AutoIncr = '1' )then
CPU.A_Oper <= ALU_UPP1;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
CPU.A_NoFlags <= '1';
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= STX_C2;
end if;
when STX_C1 =>
PC_Ctrl.Oper <= PC_INCR;
-- If auto-increment is disabled, just load the registers normally
if( not Enable_Auto_Increment )then
CPU_Next_State <= PIPE_FILL_1;
Address <= (Regfile(Reg_1) & Regfile(Reg));
-- Otherwise, enforce the even register rule, and check the LSB to see
-- if we should perform the auto-increment on the register pair
else
CPU_Next_State <= PIPE_FILL_1;
Reg := conv_integer(SubOp(2 downto 1) & '0');
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
Address <= (Regfile(Reg_1) & Regfile(Reg));
if( SubOp(0) = '1' )then
CPU_Next_State <= STX_C2;
ALU_Ctrl.Oper <= ALU_UPP;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
end if;
end if;
 
when STX_C2 =>
PC := PC_INCR;
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
CPU.A_Oper <= ALU_UPP2;
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= PIPE_FILL_2;
when STX_C2 =>
CPU_Next_State <= PIPE_FILL_2;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_UPP2;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
 
-------------------------------------------------------------------------------
-- Multi-Cycle Math Operations
-- Multi-Cycle Math Operations (UPP, MUL)
-------------------------------------------------------------------------------
-- Because we have to backup the pipeline by 1 to refetch the 2nd
-- instruction/first operand, we have to return through PF2
 
when MATH_C1 =>
PC := PC_INCR;
CPU.A_Oper <= CPU.Opcode;
CPU.A_Reg <= CPU.SubOp_p0;
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= PIPE_FILL_2;
when MUL_C1 =>
CPU_Next_State <= PIPE_FILL_2;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_MUL;
 
when GMSK_C1 =>
PC := PC_INCR;
CPU.A_Oper <= ALU_LDI;
CPU.A_Data <= CPU.Int_Mask;
CPU.State <= PIPE_FILL_2;
when UPP_C1 =>
CPU_Next_State <= PIPE_FILL_2;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_UPP2;
ALU_Ctrl.Reg <= SubOp_p1;
 
when MUL_C1 =>
PC := PC_INCR;
CPU.A_Oper <= ALU_MUL;
CPU.State <= PIPE_FILL_2;
 
when UPP_C1 =>
PC := PC_INCR;
RegSel := conv_integer(CPU.SubOp_p1);
CPU.A_Oper <= ALU_UPP2;
CPU.A_Reg <= CPU.SubOp_p1;
CPU.A_Data <= CPU.Regfile(RegSel);
CPU.State <= PIPE_FILL_2;
 
-------------------------------------------------------------------------------
-- Basic Stack Manipulation (PSH, POP, RSP)
-------------------------------------------------------------------------------
when PSH_C1 =>
PC := PC_REV1;
SP := SP_PUSH;
CPU.State <= PIPE_FILL_1;
when PSH_C1 =>
CPU_Next_State <= PIPE_FILL_1;
Address <= Stack_Ptr;
SP_Ctrl.Oper <= SP_PUSH;
 
when POP_C1 =>
PC := PC_IDLE;
CPU.State <= POP_C2;
when POP_C1 =>
CPU_Next_State <= POP_C2;
Address <= Stack_Ptr;
 
when POP_C2 =>
PC := PC_IDLE;
CPU.State <= POP_C3;
when POP_C2 =>
CPU_Next_State <= POP_C3;
PC_Ctrl.Oper <= PC_INCR;
 
when POP_C3 =>
IC := CACHE_OPER1;
PC := PC_INCR;
CPU.State <= POP_C4;
when POP_C3 =>
CPU_Next_State <= POP_C4;
Cache_Ctrl <= CACHE_OPER1;
PC_Ctrl.Oper <= PC_INCR;
 
when POP_C4 =>
PC := PC_INCR;
CPU.A_Oper <= ALU_LDI;
CPU.A_Reg <= CPU.SubOp_p0;
CPU.A_NoFlags <= '1';
CPU.A_Data <= CPU.Operand1;
CPU.State <= PIPE_FILL_2;
 
when POP_C4 =>
CPU_Next_State <= INSTR_DECODE;
Cache_Ctrl <= CACHE_INSTR;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_POP;
ALU_Ctrl.Reg <= SubOp;
ALU_Ctrl.Data <= Operand1;
-------------------------------------------------------------------------------
-- Subroutines & Interrupts (RTS, JSR)
-------------------------------------------------------------------------------
when WAIT_FOR_INT =>
PC := PC_IDLE;
DP.Src := DATA_BUS_IDLE;
CPU.State <= WAIT_FOR_INT;
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
DP_Ctrl.Src <= DATA_BUS_IDLE;
CPU_Next_State <= WAIT_FOR_INT;
 
when ISR_C1 =>
PC := PC_IDLE;
INT.Incr_ISR := '1';
CPU.State <= ISR_C2;
when ISR_C1 =>
CPU_Next_State <= ISR_C2;
Address <= ISR_Addr;
INT_Ctrl.Incr_ISR <= '1';
 
when ISR_C2 =>
PC := PC_IDLE;
DP.Src := DATA_WR_FLAG;
CPU.State <= ISR_C3;
when ISR_C2 =>
CPU_Next_State <= ISR_C3;
Address <= ISR_Addr;
DP_Ctrl.Src <= DATA_WR_FLAG;
 
when ISR_C3 =>
IC := CACHE_OPER1;
PC := PC_IDLE;
SP := SP_PUSH;
DP.Src := DATA_WR_PC;
DP.Reg := ACCUM+1;
Ack_D := '1';
CPU.A_Oper <= ALU_STP;
CPU.A_Reg <= INT_FLAG;
CPU.State <= JSR_C1;
when ISR_C3 =>
CPU_Next_State <= JSR_C1;
Cache_Ctrl <= CACHE_OPER1;
Address <= Stack_Ptr;
SP_Ctrl.Oper <= SP_PUSH;
DP_Ctrl.Src <= DATA_WR_PC;
DP_Ctrl.Reg <= ACCUM+1;
ALU_Ctrl.Oper <= ALU_STP;
ALU_Ctrl.Reg <= INT_FLAG;
Ack_D <= '1';
 
when JSR_C1 =>
IC := CACHE_OPER2;
PC := PC_IDLE;
SP := SP_PUSH;
DP.Src := DATA_WR_PC;
DP.Reg := ACCUM;
CPU.State <= JSR_C2;
when JSR_C1 =>
CPU_Next_State <= JSR_C2;
Cache_Ctrl <= CACHE_OPER2;
Address <= Stack_Ptr;
SP_Ctrl.Oper <= SP_PUSH;
DP_Ctrl.Src <= DATA_WR_PC;
DP_Ctrl.Reg <= ACCUM;
 
when JSR_C2 =>
SP := SP_PUSH;
PC := PC_LOAD;
CPU.State <= PIPE_FILL_0;
when JSR_C2 =>
CPU_Next_State <= PIPE_FILL_0;
Address <= Stack_Ptr;
SP_Ctrl.Oper <= SP_PUSH;
PC_Ctrl.Oper <= PC_LOAD;
PC_Ctrl.Addr <= Operand2 & Operand1;
 
when RTS_C1 =>
PC := PC_IDLE;
SP := SP_POP;
CPU.State <= RTS_C2;
when RTS_C1 =>
CPU_Next_State <= RTS_C2;
Address <= Stack_Ptr;
SP_Ctrl.Oper <= SP_POP;
 
when RTS_C2 =>
PC := PC_IDLE;
if( CPU.SubOp_p0 = SOP_RTI )then
SP := SP_POP;
end if;
CPU.State <= RTS_C3;
when RTS_C2 =>
CPU_Next_State <= RTS_C3;
Address <= Stack_Ptr;
-- if this is an RTI, then we need to POP the flags
if( SubOp = SOP_RTI )then
SP_Ctrl.Oper <= SP_POP;
end if;
 
when RTS_C3 =>
IC := CACHE_OPER1;
PC := PC_IDLE;
CPU.State <= RTS_C4;
when RTS_C3 =>
CPU_Next_State <= RTS_C4;
Cache_Ctrl <= CACHE_OPER1;
-- It doesn't really matter what is on the address bus for RTS, while
-- it does for RTI, so we make this the default
Address <= Stack_Ptr;
 
when RTS_C4 =>
IC := CACHE_OPER2;
PC := PC_IDLE;
CPU.State <= RTS_C5;
when RTS_C4 =>
CPU_Next_State <= RTS_C5;
Cache_Ctrl <= CACHE_OPER2;
 
when RTS_C5 =>
PC := PC_LOAD;
CPU.State <= PIPE_FILL_0;
if( CPU.SubOp_p0 = SOP_RTI )then
IC := CACHE_OPER1;
CPU.State <= RTI_C6;
end if;
when RTS_C5 =>
CPU_Next_State <= PIPE_FILL_0;
PC_Ctrl.Oper <= PC_LOAD;
PC_Ctrl.Addr <= Operand2 & Operand1;
if( SubOp = SOP_RTI )then
CPU_Next_State <= RTI_C6;
Cache_Ctrl <= CACHE_OPER1;
end if;
 
when RTI_C6 =>
PC := PC_INCR;
CPU.Int_Level <= 7;
CPU.A_Oper <= ALU_RFLG;
CPU.A_Data <= CPU.Operand1;
CPU.State <= PIPE_FILL_1;
when RTI_C6 =>
CPU_Next_State <= PIPE_FILL_1;
PC_Ctrl.Oper <= PC_INCR;
ALU_Ctrl.Oper <= ALU_RFLG;
ALU_Ctrl.Data <= Operand1;
Int_RTI_D <= '1';
 
-------------------------------------------------------------------------------
-- Debugging (BRK) Performs a 5-clock NOP
-------------------------------------------------------------------------------
when BRK_C1 =>
CPU_Next_State <= PIPE_FILL_0;
 
when BRK_C1 =>
PC := PC_IDLE;
CPU.State <= PIPE_FILL_0;
when others =>
null;
end case;
 
when others =>
null;
 
end case;
 
-------------------------------------------------------------------------------
-- Interrupt Override Logic
-------------------------------------------------------------------------------
 
-- Interrupt service routines can only begin during the decode and wait
-- states to avoid corruption due to incomplete instruction execution
if( Int_Req = '1' )then
if( CPU.State = INSTR_DECODE or CPU.State = WAIT_FOR_INT )then
IC := CACHE_IDLE;
PC := PC_REV3;
SP := SP_IDLE;
DP.Src := DATA_RD_MEM;
INT.Soft_Ints := (others => '0');
CPU.A_Oper <= ALU_IDLE;
CPU.State <= ISR_C1;
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
-- Reset all of the sub-block controls to IDLE, to avoid unintended
-- operation due to the current instruction
ALU_Ctrl.Oper <= ALU_IDLE;
Cache_Ctrl <= CACHE_IDLE;
SP_Ctrl.Oper <= SP_IDLE;
DP_Ctrl.Src <= DATA_RD_MEM; -- JSH 7/20
INT_Ctrl.Soft_Ints <= (others => '0'); -- JSH 7/22
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Oper <= PC_INCR;
PC_Ctrl.Offset <= x"FF";
CPU_Next_State <= ISR_C1;
 
end if;
end if;
 
end process;
 
-- We need to infer a hardware multipler, so we create a special clocked
-- process with no reset or clock enable
Multiplier_proc: process( Clock )
begin
if( rising_edge(Clock) )then
Mult <= Regfile(0) *
Regfile(conv_integer(ALU_Ctrl.Reg));
end if;
end process;
 
-------------------------------------------------------------------------------
-- Vectored Interrupt Controller
-- Registered portion of CPU finite state machine
-------------------------------------------------------------------------------
CPU_Regs: process( Reset, Clock )
variable Offset_SX : ADDRESS_TYPE;
variable i_Ints : INTERRUPT_BUNDLE := (others => '0');
variable Sum : std_logic_vector(8 downto 0) := "000000000";
variable Index : integer range 0 to 7 := 0;
variable Temp : std_logic_vector(8 downto 0);
begin
if( Reset = Reset_Level )then
CPU_State <= PIPE_FILL_0;
Opcode <= OP_INC;
SubOp <= ACCUM;
SubOp_p1 <= ACCUM;
Operand1 <= x"00";
Operand2 <= x"00";
Instr_Prefetch <= '0';
Prefetch <= x"00";
 
CPU.Int_Pending <= ((Interrupts or INT.Soft_Ints) and
CPU.Int_Mask) or CPU.Int_Pending;
Wr_Data <= (others => '0');
Wr_Enable <= '0';
Rd_Enable <= '1';
 
if( CPU.Wait_for_FSM = '0' )then
if( CPU.Int_Pending(0) = '1' )then
CPU.Int_Addr <= INT_VECTOR_0;
CPU.Int_Level <= 0;
CPU.Int_Pending(0) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(1) = '1' and CPU.Int_Level > 0 )then
CPU.Int_Addr <= INT_VECTOR_1;
CPU.Int_Level <= 1;
CPU.Int_Pending(1) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(2) = '1' and CPU.Int_Level > 1 )then
CPU.Int_Addr <= INT_VECTOR_2;
CPU.Int_Level <= 2;
CPU.Int_Pending(2) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(3) = '1' and CPU.Int_Level > 2 )then
CPU.Int_Addr <= INT_VECTOR_3;
CPU.Int_Level <= 3;
CPU.Int_Pending(3) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(4) = '1' and CPU.Int_Level > 3 )then
CPU.Int_Addr <= INT_VECTOR_4;
CPU.Int_Level <= 4;
CPU.Int_Pending(4) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(5) = '1' and CPU.Int_Level > 4 )then
CPU.Int_Addr <= INT_VECTOR_5;
CPU.Int_Level <= 5;
CPU.Int_Pending(5) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(6) = '1' and CPU.Int_Level > 6 )then
CPU.Int_Addr <= INT_VECTOR_6;
CPU.Int_Level <= 6;
CPU.Int_Pending(6) <= '0';
CPU.Wait_for_FSM <= '1';
elsif( CPU.Int_Pending(7) = '1' )then
CPU.Int_Addr <= INT_VECTOR_7;
CPU.Int_Level <= 7;
CPU.Int_Pending(7) <= '0';
CPU.Wait_for_FSM <= '1';
end if;
end if;
Program_Ctr <= Program_Start_Addr;
Stack_Ptr <= Stack_Start_Addr;
 
Ack_Q <= Ack_D;
Ack_Q1 <= Ack_Q;
Int_Ack <= Ack_Q1;
if( Int_Ack = '1' )then
CPU.Wait_for_FSM <= '0';
end if;
Ack_Q <= '0';
Ack_Q1 <= '0';
Int_Ack <= '0';
Int_RTI <= '0';
 
Int_Req <= CPU.Wait_for_FSM and (not Int_Ack);
Int_Req <= '0';
Pending <= x"00";
Wait_for_FSM <= '0';
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
ISR_Addr <= INT_VECTOR_0;
for i in 0 to 8 loop
History(i) <= 0;
end loop;
Hst_Ptr <= 0;
 
if( INT.Mask_Set = '1' )then
if( Enable_NMI )then
CPU.Int_Mask <= Accumulator(7 downto 1) & '1';
else -- Disable NMI override
CPU.Int_Mask <= Accumulator;
end if;
end if;
for i in 0 to 7 loop
Regfile(i) <= (others => '0');
end loop;
Flags <= x"00";
 
if( INT.Incr_ISR = '1' )then
CPU.Int_Addr <= CPU.Int_Addr + 1;
end if;
elsif( rising_edge(Clock) )then
Wr_Enable <= '0';
Wr_Data <= x"00";
Rd_Enable <= '0';
 
if( Halt = '0' )then
-------------------------------------------------------------------------------
-- ALU (Arithmetic / Logic Unit)
-- Instruction/Operand caching for pipelined memory access
-------------------------------------------------------------------------------
Index := conv_integer(CPU.A_Reg);
CPU_State <= CPU_Next_State;
case Cache_Ctrl is
when CACHE_INSTR =>
Opcode <= Rd_Data(7 downto 3);
SubOp <= Rd_Data(2 downto 0);
SubOp_p1 <= Rd_Data(2 downto 0) + 1;
if( Instr_Prefetch = '1' )then
Opcode <= Prefetch(7 downto 3);
SubOp <= Prefetch(2 downto 0);
SubOp_p1 <= Prefetch(2 downto 0) + 1;
Instr_Prefetch <= '0';
end if;
 
CPU.M_Prod <= Accumulator *
CPU.Regfile(conv_integer(CPU.M_Reg));
when CACHE_OPER1 =>
Operand1 <= Rd_Data;
 
case( CPU.A_Oper )is
when ALU_INC => -- Rn = Rn + 1 : CPU.Flags N,C,Z
Temp := ("0" & x"01") +
("0" & CPU.A_Data);
Flags(FL_CARRY) <= Temp(8);
CPU.Regfile(Index) <= Temp(7 downto 0);
if( CPU.A_NoFlags = '0' )then
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
end if;
when CACHE_OPER2 =>
Operand2 <= Rd_Data;
 
when ALU_UPP2 => -- Rn = Rn + C : Flags C
Temp := ("0" & x"00") +
("0" & CPU.A_Data) +
Flags(FL_CARRY);
Flags(FL_CARRY) <= Temp(8);
CPU.Regfile(Index) <= Temp(7 downto 0);
when CACHE_PREFETCH =>
Prefetch <= Rd_Data;
Instr_Prefetch <= '1';
 
when ALU_ADC => -- R0 = R0 + Rn + C : N,C,Z
Temp := ("0" & Accumulator) +
("0" & CPU.A_Data) +
Flags(FL_CARRY);
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
when CACHE_IDLE =>
null;
end case;
 
when ALU_TX0 => -- R0 = Rn : Flags N,Z
Temp := "0" & CPU.A_Data;
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
-------------------------------------------------------------------------------
-- Program Counter
-------------------------------------------------------------------------------
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
 
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
Temp(7 downto 0) := Accumulator or CPU.A_Data;
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
case PC_Ctrl.Oper is
when PC_IDLE =>
null;
 
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
Temp(7 downto 0) := Accumulator and CPU.A_Data;
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
when PC_REV1 =>
Program_Ctr <= Program_Ctr - 1;
 
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
Temp(7 downto 0) := Accumulator xor CPU.A_Data;
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
when PC_REV2 =>
Program_Ctr <= Program_Ctr - 2;
 
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
Temp := CPU.A_Data & Flags(FL_CARRY);
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
CPU.Regfile(Index) <= Temp(7 downto 0);
when PC_INCR =>
Program_Ctr <= Program_Ctr + Offset_SX - 2;
 
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
Temp := CPU.A_Data(0) & Flags(FL_CARRY) &
CPU.A_Data(7 downto 1);
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
CPU.Regfile(Index) <= Temp(7 downto 0);
when PC_LOAD =>
Program_Ctr <= PC_Ctrl.Addr;
 
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
Temp := ("0" & CPU.A_Data) +
("0" & x"FF");
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
CPU.Regfile(Index) <= Temp(7 downto 0);
when others =>
null;
end case;
 
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
Temp := ("0" & Accumulator) +
("0" & (not CPU.A_Data)) +
Flags(FL_CARRY);
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
Accumulator <= Temp(7 downto 0);
-------------------------------------------------------------------------------
-- (Write) Data Path
-------------------------------------------------------------------------------
case DP_Ctrl.Src is
when DATA_BUS_IDLE =>
null;
 
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
Temp := ("0" & Accumulator) +
("0" & CPU.A_Data);
Flags(FL_CARRY) <= Temp(8);
Accumulator <= Temp(7 downto 0);
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
when DATA_RD_MEM =>
Rd_Enable <= '1';
 
when ALU_STP => -- Sets bit(n) in the CPU.Flags register
Flags(Index) <= '1';
when DATA_WR_REG =>
Wr_Enable <= '1';
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
 
when ALU_BTT => -- Z = !R0(N), N = R0(7)
Flags(FL_ZERO) <= not Accumulator(Index);
Flags(FL_NEG) <= Accumulator(7);
when DATA_WR_FLAG =>
Wr_Enable <= '1';
Wr_Data <= Flags;
 
when ALU_CLP => -- Clears bit(n) in the Flags register
Flags(Index) <= '0';
when DATA_WR_PC =>
Wr_Enable <= '1';
Wr_Data <= Program_Ctr(15 downto 8);
if( DP_Ctrl.Reg = ACCUM )then
Wr_Data <= Program_Ctr(7 downto 0);
end if;
 
when ALU_T0X => -- Rn = R0 : Flags N,Z
Temp := "0" & Accumulator;
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_NEG) <= Temp(7);
CPU.Regfile(Index) <= Temp(7 downto 0);
when others =>
null;
end case;
 
when ALU_CMP => -- Sets CPU.Flags on R0 - Rn : Flags N,C,Z
Temp := ("0" & Accumulator) +
("0" & (not CPU.A_Data)) +
'1';
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
-------------------------------------------------------------------------------
-- Stack Pointer
-------------------------------------------------------------------------------
case SP_Ctrl.Oper is
when SP_IDLE =>
null;
 
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
CPU.Regfile(0) <= CPU.M_Prod(7 downto 0);
CPU.Regfile(1) <= CPU.M_Prod(15 downto 8);
Flags(FL_ZERO) <= nor_reduce(CPU.M_Prod);
when SP_RSET =>
-- The original RSP instruction simply reset the stack pointer to the preset
-- address set at compile time. However, with little extra effort, we can
-- modify the instruction to allow the stack pointer to be moved anywhere in
-- the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as
-- a fixed source
Stack_Ptr <= Stack_Start_Addr;
if( Allow_Stack_Address_Move )then
Stack_Ptr <= Regfile(1) & Regfile(0);
end if;
 
when ALU_LDI => -- Rn <= Data : Flags N,Z
if( CPU.A_NoFlags = '0' )then
Flags(FL_ZERO) <= nor_reduce(CPU.A_Data);
Flags(FL_NEG) <= CPU.A_Data(7);
end if;
CPU.Regfile(Index) <= CPU.A_Data;
when SP_POP =>
Stack_Ptr <= Stack_Ptr + 1;
 
when ALU_RFLG =>
Flags <= CPU.A_Data;
when SP_PUSH =>
Stack_Ptr <= Stack_Ptr - 1;
 
when others =>
null;
end case;
when others =>
null;
 
end case;
 
-------------------------------------------------------------------------------
-- Instruction/Operand caching for pipelined memory access
-- Interrupt Controller
-------------------------------------------------------------------------------
-- The interrupt control mask is always sourced out of R0
if( INT_Ctrl.Mask_Set = '1' )then
Int_Mask <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
end if;
 
case( IC )is
when CACHE_INSTR =>
CPU.Opcode <= Rd_Data(7 downto 3);
CPU.SubOp_p0 <= Rd_Data(2 downto 0);
CPU.SubOp_p1 <= Rd_Data(2 downto 0) + 1;
if( CPU.Cache_Valid = '1' )then
CPU.Opcode <= CPU.Prefetch(7 downto 3);
CPU.SubOp_p0 <= CPU.Prefetch(2 downto 0);
CPU.SubOp_p1 <= CPU.Prefetch(2 downto 0) + 1;
CPU.Cache_Valid <= '0';
-- Combine external and internal interrupts, and mask the OR or the two
-- with the mask. Record any incoming interrupts to the pending buffer
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
Int_Mask;
if( i_Ints > 0 )then
Pending <= i_Ints;
end if;
 
-- Only mess with interrupt signals while the CPU core is not currently
-- working with, or loading, an ISR address
if( Wait_for_FSM = '0' and Pending > 0 )then
if( Pending(0) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 0))then
ISR_Addr <= INT_VECTOR_0;
Pending(0) <= '0';
History(Hst_Ptr+1) <= 0;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(1) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 1))then
ISR_Addr <= INT_VECTOR_1;
Pending(1) <= '0';
History(Hst_Ptr+1) <= 1;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(2) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 2))then
ISR_Addr <= INT_VECTOR_2;
Pending(2) <= '0';
History(Hst_Ptr+1) <= 1;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(3) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 3))then
ISR_Addr <= INT_VECTOR_3;
Pending(3) <= '0';
History(Hst_Ptr+1) <= 3;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(4) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 4))then
ISR_Addr <= INT_VECTOR_4;
Pending(4) <= '0';
History(Hst_Ptr+1) <= 4;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(5) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 5))then
ISR_Addr <= INT_VECTOR_5;
Pending(5) <= '0';
History(Hst_Ptr+1) <= 5;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(6) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 6))then
ISR_Addr <= INT_VECTOR_6;
Pending(6) <= '0';
History(Hst_Ptr+1) <= 6;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
elsif(Pending(7) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 7))then
ISR_Addr <= INT_VECTOR_7;
Pending(7) <= '0';
History(Hst_Ptr+1) <= 7;
Hst_Ptr <= Hst_Ptr + 1;
Wait_for_FSM <= '1';
end if;
end if;
 
when CACHE_OPER1 =>
CPU.Operand1 <= Rd_Data;
-- Reset the Wait_for_FSM flag on Int_Ack
Ack_Q <= Ack_D;
Ack_Q1 <= Ack_Q;
Int_Ack <= Ack_Q1;
if( Int_Ack = '1' )then
Wait_for_FSM <= '0';
end if;
 
when CACHE_OPER2 =>
CPU.Operand2 <= Rd_Data;
Int_Req <= Wait_for_FSM and (not Int_Ack);
 
when CACHE_PREFETCH =>
CPU.Prefetch <= Rd_Data;
CPU.Cache_Valid <= '1';
Int_RTI <= Int_RTI_D;
if( Int_RTI = '1' and Hst_Ptr > 0 )then
Hst_Ptr <= Hst_Ptr - 1;
end if;
 
when CACHE_PFFLUSH =>
CPU.Prefetch <= Rd_Data;
CPU.Operand1 <= x"00";
CPU.Operand2 <= x"00";
CPU.Cache_Valid <= '1';
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
-- lower half of the address.
if( INT_Ctrl.Incr_ISR = '1' )then
ISR_Addr <= ISR_Addr + 1;
end if;
 
when CACHE_INVALIDATE =>
CPU.Cache_Valid <= '0';
 
when CACHE_IDLE =>
null;
end case;
 
-------------------------------------------------------------------------------
-- Program Counter
-- ALU (Arithmetic / Logic Unit)
-------------------------------------------------------------------------------
Temp := (others => '0');
Index := conv_integer(ALU_Ctrl.Reg);
 
Offset_SX(15 downto 8) := (others => CPU.Operand1(7));
Offset_SX(7 downto 0) := CPU.Operand1;
case ALU_Ctrl.Oper is
when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z
Sum := ("0" & x"01") +
("0" & Regfile(Index));
Flags(FL_CARRY) <= Sum(8);
Regfile(Index) <= Sum(7 downto 0);
-- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP
-- doesn't set the N or Z flags. Note that the MSB can be used to
-- distinguish between the two ALU modes.
if( ALU_Ctrl.Oper(4) = '0' )then
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO)<= '1';
end if;
Flags(FL_NEG) <= Sum(7);
end if;
 
case( PC )is
when ALU_UPP2 => -- Rn = Rn + C
Sum := ("0" & x"00") +
("0" & Regfile(Index)) +
Flags(FL_CARRY);
Flags(FL_CARRY) <= Sum(8);
Regfile(Index) <= Sum(7 downto 0);
 
when PC_INCR =>
CPU.Program_Ctr <= CPU.Program_ctr + 1;
when PC_IDLE =>
--CPU.Program_Ctr <= CPU.Program_Ctr + 0;
null;
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
Sum := ("0" & Regfile(0)) +
("0" & Regfile(Index)) +
Flags(FL_CARRY);
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Sum(8);
Flags(FL_NEG) <= Sum(7);
Regfile(0) <= Sum(7 downto 0);
 
when PC_REV1 =>
CPU.Program_Ctr <= CPU.Program_Ctr - 1;
when ALU_TX0 => -- R0 = Rn : Flags N,Z
Temp := "0" & Regfile(Index);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Temp(7);
Regfile(0) <= Temp(7 downto 0);
 
when PC_REV2 =>
CPU.Program_Ctr <= CPU.Program_Ctr - 2;
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Temp(7);
Regfile(0) <= Temp(7 downto 0);
 
when PC_REV3 =>
CPU.Program_Ctr <= CPU.Program_Ctr - 3;
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Temp(7);
Regfile(0) <= Temp(7 downto 0);
 
when PC_BRANCH =>
CPU.Program_Ctr <= CPU.Program_Ctr + Offset_SX - 2;
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Temp(7);
Regfile(0) <= Temp(7 downto 0);
 
when PC_LOAD =>
CPU.Program_Ctr <= CPU.Operand2 & CPU.Operand1;
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
Temp := Regfile(Index) & Flags(FL_CARRY);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
Regfile(Index) <= Temp(7 downto 0);
 
when others =>
null;
end case;
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
Regfile(Index)(7 downto 1);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Temp(8);
Flags(FL_NEG) <= Temp(7);
Regfile(Index) <= Temp(7 downto 0);
 
-------------------------------------------------------------------------------
-- (Write) Data Path
-------------------------------------------------------------------------------
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
Sum := ("0" & Regfile(Index)) +
("0" & x"FF");
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Sum(8);
Flags(FL_NEG) <= Sum(7);
Regfile(Index) <= Sum(7 downto 0);
 
Wr_Data <= x"00";
Wr_Enable <= '0';
Rd_Enable <= '0';
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
Sum := ("0" & Regfile(0)) +
("0" & (not Regfile(Index))) +
Flags(FL_CARRY);
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Sum(8);
Flags(FL_NEG) <= Sum(7);
Regfile(0) <= Sum(7 downto 0);
 
case( DP.Src )is
when DATA_BUS_IDLE =>
null;
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
Sum := ("0" & Regfile(0)) +
("0" & Regfile(Index));
Flags(FL_CARRY) <= Sum(8);
Regfile(0) <= Sum(7 downto 0);
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Sum(7);
 
when DATA_RD_MEM =>
Rd_Enable <= '1';
when ALU_STP => -- Sets bit(n) in the Flags register
Flags(Index) <= '1';
 
when DATA_WR_REG =>
Wr_Enable <= '1';
Wr_Data <= CPU.Regfile(conv_integer(DP.Reg));
when ALU_BTT => -- Z = !R0(N), N = R0(7)
Flags(FL_ZERO) <= not Regfile(0)(Index);
Flags(FL_NEG) <= Regfile(0)(7);
 
when DATA_WR_FLAG =>
Wr_Enable <= '1';
Wr_Data <= Flags;
when ALU_CLP => -- Clears bit(n) in the Flags register
Flags(Index) <= '0';
 
when DATA_WR_PC =>
Wr_Enable <= '1';
Wr_Data <= CPU.Program_Ctr(15 downto 8);
if( DP.Reg = ACCUM )then
Wr_Data <= CPU.Program_Ctr(7 downto 0);
end if;
when ALU_T0X => -- Rn = R0 : Flags N,Z
Temp := "0" & Regfile(0);
Flags(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= Temp(7);
Regfile(Index) <= Temp(7 downto 0);
 
when others =>
null;
end case;
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
Sum := ("0" & Regfile(0)) +
("0" & (not Regfile(Index))) +
'1';
Flags(FL_ZERO) <= '0';
if( Sum(7 downto 0) = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_CARRY) <= Sum(8);
Flags(FL_NEG) <= Sum(7);
 
-------------------------------------------------------------------------------
-- Stack Pointer
-------------------------------------------------------------------------------
case( SP )is
when SP_IDLE =>
null;
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
Regfile(0) <= Mult(7 downto 0);
Regfile(1) <= Mult(15 downto 8);
Flags(FL_ZERO) <= '0';
if( Mult = 0 )then
Flags(FL_ZERO) <= '1';
end if;
 
when SP_RSET =>
CPU.Stack_Ptr <= Stack_Start_Addr;
if( Allow_Stack_Address_Move )then
CPU.Stack_Ptr <= CPU.Regfile(1) & CPU.Regfile(0);
end if;
when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z
-- The POP instruction doesn't alter the flags, so we need to check
if( ALU_Ctrl.Oper = ALU_LDI )then
Flags(FL_ZERO) <= '0';
if( ALU_Ctrl.Data = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
end if;
Regfile(Index) <= ALU_Ctrl.Data;
 
when SP_POP =>
CPU.Stack_Ptr <= CPU.Stack_Ptr + 1;
when ALU_LDX => -- R0 <= Data : Flags N,Z
Flags(FL_ZERO) <= '0';
if( ALU_Ctrl.Data = 0 )then
Flags(FL_ZERO) <= '1';
end if;
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
Regfile(0) <= ALU_Ctrl.Data;
 
when SP_PUSH =>
CPU.Stack_Ptr <= CPU.Stack_Ptr - 1;
when ALU_RFLG =>
Flags <= ALU_Ctrl.Data;
 
when others =>
null;
when others =>
null;
end case;
 
end case;
 
end if;
end if;
end process;
 

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