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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc
    from Rev 332 to Rev 333
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Rev 332 → Rev 333

/trunk/VHDL/o8_ram_1k.vhd
29,7 → 29,7
-- : from inadvertently writing outside of their designated
-- : memory space.
-- : When enabled, the write mask logically divides the memory into
-- : 16, 64 byte regions, corresponding to the 16 bits in the WPR
-- : 32, 32-byte regions, corresponding to the 32 bits in the WPR
-- : register.
--
-- WP Register Map:
36,6 → 36,10
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
-- 0x04 AAAAAAAA Fault Address 7:0 (RW*)
-- 0x05 AAAAAAAA Fault Address 15:8 (RW*)
--
-- Revision History
-- Author Date Change
42,6 → 46,8
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/12/20 Added write protect logic
-- Seth Henry 10/04/23 Modified WPR to match 4K RAM and added fault
-- address capture
 
library ieee;
use ieee.std_logic_1164.all;
54,7 → 60,7
entity o8_ram_1k is
generic(
Write_Protect : boolean := FALSE;
Default_Mask : ADDRESS_TYPE := x"0000";
Default_Mask : std_logic_vector(31 downto 0) := x"00000000";
Address_WPR : ADDRESS_TYPE := x"0400";
Address_RAM : ADDRESS_TYPE
);
70,28 → 76,32
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
alias Full_Address is Open8_Bus.Address;
alias Wr_En is Open8_Bus.Wr_En;
alias Rd_En is Open8_Bus.Rd_En;
 
constant WPR_User_Addr : std_logic_vector(15 downto 1)
:= Address_WPR(15 downto 1);
constant WPR_User_Addr : std_logic_vector(15 downto 3)
:= Address_WPR(15 downto 3);
 
constant RAM_User_Addr : std_logic_vector(15 downto 10)
:= Address_RAM(15 downto 10);
 
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 3);
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
signal WPR_Reg_Sel_q : std_logic := '0';
alias WPR_Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal WPR_Reg_Sel_q : std_logic_vector(2 downto 0) :=
(others => '0');
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal WPR_Wr_Data_q : DATA_TYPE := x"00";
 
signal Write_Mask : std_logic_vector(15 downto 0) :=
x"0000";
alias Write_Mask_0 is Write_Mask(7 downto 0);
alias Write_Mask_1 is Write_Mask(15 downto 8);
signal Write_Mask : std_logic_vector(31 downto 0) :=
x"00000000";
alias Write_Mask_0 is Write_Mask( 7 downto 0);
alias Write_Mask_1 is Write_Mask(15 downto 8);
alias Write_Mask_2 is Write_Mask(23 downto 16);
alias Write_Mask_3 is Write_Mask(31 downto 24);
 
signal WPR_Wr_En_d : std_logic := '0';
signal WPR_Wr_En_q : std_logic := '0';
101,7 → 111,7
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
 
alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 5);
 
signal RAM_Region_Match : std_logic := '0';
signal RAM_Addr_Match : std_logic := '0';
112,7 → 122,13
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
signal Write_Fault_d : std_logic := '0';
signal Write_Fault_q : std_logic := '0';
 
signal Current_Addr : ADDRESS_TYPE := x"0000";
signal Fault_Addr : ADDRESS_TYPE := x"0000";
alias Fault_Addr_l is Fault_Addr(7 downto 0);
alias Fault_Addr_h is Fault_Addr(15 downto 8);
 
begin
 
Write_Protect_On : if( Write_Protect )generate
131,10 → 147,12
 
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
 
Write_Fault <= Write_Fault_q;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
WPR_Reg_Sel_q <= '0';
WPR_Reg_Sel_q <= (others => '0');
WPR_Wr_Data_q <= x"00";
 
WPR_Wr_En_q <= '0';
146,6 → 164,7
Rd_Data <= OPEN8_NULLBUS;
 
Write_Fault <= '0';
Current_Addr <= x"0000";
 
elsif( rising_edge(Clock) )then
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
154,10 → 173,16
WPR_Wr_Data_q <= Wr_Data_d;
if( WPR_Wr_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when '0' =>
when "000" =>
Write_Mask_0 <= WPR_Wr_Data_q;
when '1' =>
when "001" =>
Write_Mask_1 <= WPR_Wr_Data_q;
when "010" =>
Write_Mask_2 <= WPR_Wr_Data_q;
when "011" =>
Write_Mask_3 <= WPR_Wr_Data_q;
when "100" | "101" =>
Fault_Addr <= (others => '0');
when others =>
null;
end case;
171,17 → 196,30
Rd_Data <= RAM_Rd_Data;
elsif( WPR_Rd_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when '0' =>
when "000" =>
Rd_Data <= Write_Mask_0;
when '1' =>
when "001" =>
Rd_Data <= Write_Mask_1;
when "010" =>
Rd_Data <= Write_Mask_2;
when "011" =>
Rd_Data <= Write_Mask_3;
when "100" =>
Rd_Data <= Fault_Addr_l;
when "101" =>
Rd_Data <= Fault_Addr_h;
when others =>
null;
end case;
end if;
 
Write_Fault <= Write_Fault_d;
Write_Fault_q <= Write_Fault_d;
 
Current_Addr <= Full_Address;
if( Write_Fault_q = '1' )then
Fault_Addr <= Current_Addr;
end if;
 
end if;
end process;
 
/trunk/VHDL/o8_ram_4k.vhd
38,12 → 38,17
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
-- 0x04 AAAAAAAA Fault Address 7:0 (RW*)
-- 0x05 AAAAAAAA Fault Address 15:8 (RW*)
--
-- Note: Writing to 0x04 or 0x05 will reset the faulting address to 0x0000
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/12/20 Added write protect logic
-- Seth Henry 10/04/23 Added faulting address register
 
library ieee;
use ieee.std_logic_1164.all;
72,20 → 77,21
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
alias Full_Address is Open8_Bus.Address;
alias Wr_En is Open8_Bus.Wr_En;
alias Rd_En is Open8_Bus.Rd_En;
 
constant WPR_User_Addr : std_logic_vector(15 downto 2)
:= Address_WPR(15 downto 2);
constant WPR_User_Addr : std_logic_vector(15 downto 3)
:= Address_WPR(15 downto 3);
 
constant RAM_User_Addr : std_logic_vector(15 downto 12)
:= Address_RAM(15 downto 12);
 
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 2);
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 3);
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal WPR_Reg_Sel_q : std_logic_vector(1 downto 0) :=
alias WPR_Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal WPR_Reg_Sel_q : std_logic_vector(2 downto 0) :=
(others => '0');
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
117,7 → 123,12
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
signal Write_Fault_d : std_logic := '0';
signal Write_Fault_q : std_logic := '0';
 
signal Current_Addr : ADDRESS_TYPE := x"0000";
signal Fault_Addr : ADDRESS_TYPE := x"0000";
alias Fault_Addr_l is Fault_Addr(7 downto 0);
alias Fault_Addr_h is Fault_Addr(15 downto 8);
begin
 
Write_Protect_On : if( Write_Protect )generate
136,6 → 147,8
 
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
 
Write_Fault <= Write_Fault_q;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
151,7 → 164,8
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Write_Fault <= '0';
Write_Fault_q <= '0';
Current_Addr <= x"0000";
 
elsif( rising_edge(Clock) )then
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
160,14 → 174,16
WPR_Wr_Data_q <= Wr_Data_d;
if( WPR_Wr_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when "00" =>
when "000" =>
Write_Mask_0 <= WPR_Wr_Data_q;
when "01" =>
when "001" =>
Write_Mask_1 <= WPR_Wr_Data_q;
when "10" =>
when "010" =>
Write_Mask_2 <= WPR_Wr_Data_q;
when "11" =>
when "011" =>
Write_Mask_3 <= WPR_Wr_Data_q;
when "100" | "101" =>
Fault_Addr <= (others => '0');
when others =>
null;
end case;
181,21 → 197,30
Rd_Data <= RAM_Rd_Data;
elsif( WPR_Rd_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when "00" =>
when "000" =>
Rd_Data <= Write_Mask_0;
when "01" =>
when "001" =>
Rd_Data <= Write_Mask_1;
when "10" =>
when "010" =>
Rd_Data <= Write_Mask_2;
when "11" =>
when "011" =>
Rd_Data <= Write_Mask_3;
when "100" =>
Rd_Data <= Fault_Addr_l;
when "101" =>
Rd_Data <= Fault_Addr_h;
when others =>
null;
end case;
end if;
 
Write_Fault <= Write_Fault_d;
Write_Fault_q <= Write_Fault_d;
 
Current_Addr <= Full_Address;
if( Write_Fault_q = '1' )then
Fault_Addr <= Current_Addr;
end if;
 
end if;
end process;
 
/trunk/VHDL/o8_sys_timer_ii.vhd
77,8 → 77,8
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias CPU_Wr_En is Open8_Bus.Wr_En
alias CPU_Rd_En is Open8_Bus.Rd_En
alias CPU_Wr_En is Open8_Bus.Wr_En;
alias CPU_Rd_En is Open8_Bus.Rd_En;
 
constant User_Addr : std_logic_vector(15 downto 2) :=
Address(15 downto 2);

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