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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/or1ksim
    from Rev 121 to Rev 122
    ↔ Reverse comparison
  •

Rev 121 → Rev 122

/cpu/or32/or32.c
350,8 → 350,8
EF (l_srl), 0, it_shift},
{"l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL",
EF (l_sra), 0, it_shift},
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI,
0, it_shift},
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL",
EF (l_ror), 0, it_shift},
 
{"l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII",
EF (l_sfeq), OR32_W_FLAG, it_compare},
473,8 → 473,8
EF (l_srl), 0, it_shift},
{"l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8",
EF (l_sra), 0, it_shift},
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI,
0, it_shift},
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8",
EF (l_ror), 0, it_shift},
{"l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9",
EF (l_div), 0, it_arith},
{"l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA",
/cpu/or32/insnset.c
417,6 → 417,12
SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
}
INSTRUCTION (l_ror) {
uorreg_t temp1;
temp1 = PARAM1 >> (PARAM2 & 0x1f);
temp1 |= PARAM1 << (32 - (PARAM2 & 0x1f));
SET_PARAM0(temp1);
}
INSTRUCTION (l_bf) {
if (config.bpb.enabled) {
int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
/NEWS
15,6 → 15,8
* Bug 1774: l.mulu not implemented.
* Bug 1775: l.jalr and l.jr don't trigger alignment exceptions.
* Bug 1776: l.addic is not implemented.
* Bug 1777: l.macrc not correctly implemented.
* Bug 1778: l.ror and l.rori are not implemented.
 
The following bugs are either cannot be reproduced or will not be fixed.
 
/ChangeLog
5,7 → 5,9
REG_PARAM0 to identify register. Corrected undef of SET_PARAM0.
* cpu/or32/insnset.c <l_jalr>: Trigger exceptions on use of link
register as destination or non-aligned effective address.
<jr>: Trigger exception on use of non-aligned effective address.
<l_jr>: Trigger exception on use of non-aligned effective address.
<l_ror>: Created.
* cpu/or32/or32.c <or32_opcodes>: l.ror and l.rori enabled.
* NEWS: Updated with new bugs fixed.
 
2010-06-13 Jeremy Bennett <jeremy.bennett@embecosm.com>
/testsuite/test-code-or1k/inst-set-test/Makefile.in
61,7 → 61,7
check_PROGRAMS = is-add-test$(EXEEXT) is-div-test$(EXEEXT) \
is-find-test$(EXEEXT) is-jump-test$(EXEEXT) \
is-lws-test$(EXEEXT) is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) \
$(am__EXEEXT_1)
is-ror-test$(EXEEXT) $(am__EXEEXT_1)
subdir = inst-set-test
DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
128,6 → 128,12
is_mul_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
$(is_mul_test_LDFLAGS) $(LDFLAGS) -o $@
am_is_ror_test_OBJECTS = is-ror-test.$(OBJEXT)
is_ror_test_OBJECTS = $(am_is_ror_test_OBJECTS)
is_ror_test_DEPENDENCIES = inst-set-test.lo
is_ror_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
$(is_ror_test_LDFLAGS) $(LDFLAGS) -o $@
DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
depcomp = $(SHELL) $(top_srcdir)/../../depcomp
am__depfiles_maybe = depfiles
150,12 → 156,13
$(is_add_test_SOURCES) $(is_div_test_SOURCES) \
$(is_find_test_SOURCES) $(is_jump_test_SOURCES) \
$(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \
$(is_mul_test_SOURCES)
$(is_mul_test_SOURCES) $(is_ror_test_SOURCES)
DIST_SOURCES = $(libinst_set_test_la_SOURCES) \
$(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \
$(is_div_test_SOURCES) $(is_find_test_SOURCES) \
$(is_jump_test_SOURCES) $(is_lws_test_SOURCES) \
$(is_mac_test_SOURCES) $(is_mul_test_SOURCES)
$(is_mac_test_SOURCES) $(is_mul_test_SOURCES) \
$(is_ror_test_SOURCES)
ETAGS = etags
CTAGS = ctags
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
321,7 → 328,12
 
is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld
is_mul_test_LDADD = inst-set-test.lo
is_ror_test_SOURCES = inst-set-test.h \
is-ror-test.S
 
is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld
is_ror_test_LDADD = inst-set-test.lo
 
# The old test which builds with warnings and runs with errors
inst_set_test_old_SOURCES = inst-set-test-old.c
inst_set_test_old_LDFLAGS = -T$(srcdir)/../default.ld
406,6 → 418,9
is-mul-test$(EXEEXT): $(is_mul_test_OBJECTS) $(is_mul_test_DEPENDENCIES)
@rm -f is-mul-test$(EXEEXT)
$(is_mul_test_LINK) $(is_mul_test_OBJECTS) $(is_mul_test_LDADD) $(LIBS)
is-ror-test$(EXEEXT): $(is_ror_test_OBJECTS) $(is_ror_test_DEPENDENCIES)
@rm -f is-ror-test$(EXEEXT)
$(is_ror_test_LINK) $(is_ror_test_OBJECTS) $(is_ror_test_LDADD) $(LIBS)
 
mostlyclean-compile:
-rm -f *.$(OBJEXT)
422,6 → 437,7
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-lws-test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mac-test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mul-test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-ror-test.Po@am__quote@
 
.S.o:
@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
/testsuite/test-code-or1k/inst-set-test/Makefile.am
48,6 → 48,7
is-lws-test \
is-mac-test \
is-mul-test \
is-ror-test \
$(INST_SET_TEST_OLD)
 
# The new instruction set tests.
86,6 → 87,11
is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld
is_mul_test_LDADD = inst-set-test.lo
 
is_ror_test_SOURCES = inst-set-test.h \
is-ror-test.S
is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld
is_ror_test_LDADD = inst-set-test.lo
 
# The old test which builds with warnings and runs with errors
inst_set_test_old_SOURCES = inst-set-test-old.c
 
/testsuite/test-code-or1k/inst-set-test/is-ror-test.S
0,0 → 1,189
/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
*
* Copyright (C) 1999-2006 OpenCores
* Copyright (C) 2010 Embecosm Limited
*
* Contributors various OpenCores participants
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of OpenRISC 1000 Architectural Simulator.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http: www.gnu.org/licenses/>.
*/
 
/* ----------------------------------------------------------------------------
* Coding conventions are described in inst-set-test.S
* ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
* Test coverage
*
* The l.ror and l.rori instructions were missing from Or1ksim.
*
* Having fixed the problem, this is (in good software engineering style), a
* regresison test to go with the fix.
*
* This is not a comprehensive test of either instruction (yet).
*
* Of course what is really needed is a comprehensive instruction test...
* ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of rotate right
*
* Arguments
* op1: First operand value
* op2: Second operand value
* res: Expected result
* ------------------------------------------------------------------------- */
#define TEST_ROR(op1, op2, res) \
LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
LOAD_CONST (r6,op2) ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
50: l.ror r4,r5,r6 ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" ROR 0x") ;\
PUTH (op2) ;\
PUTS (" = 0x") ;\
PUTH (res) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, res) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 51f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 52f ;\
l.nop ;\
;\
51: PUTS (" - exception triggered: FALSE\n") ;\
52:
/* ----------------------------------------------------------------------------
* A macro to carry out a test of rotate right immediate
*
* Arguments
* op1: First operand value
* op2: Second operand value
* res: Expected result
* ------------------------------------------------------------------------- */
#define TEST_RORI(op1, op2, res) \
LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
53: l.rori r4,r5,op2 ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" RORI 0x") ;\
PUTHQ (op2) ;\
PUTS (" = 0x") ;\
PUTH (res) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, res) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 54f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 55f ;\
l.nop ;\
;\
54: PUTS (" - exception triggered: FALSE\n") ;\
55:
/* ----------------------------------------------------------------------------
* Start of code
* ------------------------------------------------------------------------- */
.section .text
.global _start
_start:
 
/* ----------------------------------------------------------------------------
* Test of rotate right, l.ror
* ------------------------------------------------------------------------- */
_ror:
LOAD_STR (r3, "l.ror\n")
l.jal _puts
l.nop
 
/* Rotate by zero */
TEST_ROR (0xb38f0f83, 0x00000000, 0xb38f0f83)
 
/* Rotate by amounts in the 1 - 31 range. */
TEST_ROR (0xb38f0f83, 0x00000001, 0xd9c787c1)
TEST_ROR (0xb38f0f83, 0x00000004, 0x3b38f0f8)
TEST_ROR (0xb38f0f83, 0x00000010, 0x0f83b38f)
TEST_ROR (0xb38f0f83, 0x0000001f, 0x671e1f07)
 
/* Rotate by larger amounts - should be masked. */
TEST_ROR (0xb38f0f83, 0x00000021, 0xd9c787c1)
TEST_ROR (0xb38f0f83, 0x00002224, 0x3b38f0f8)
TEST_ROR (0xb38f0f83, 0x00f789f0, 0x0f83b38f)
TEST_ROR (0xb38f0f83, 0xffffffff, 0x671e1f07)
 
/* ----------------------------------------------------------------------------
* Test of rotate right immediate, l.rori
* ------------------------------------------------------------------------- */
_rori:
LOAD_STR (r3, "l.rori\n")
l.jal _puts
l.nop
 
/* Rotate by zero */
TEST_RORI (0xb38f0f83, 0x00000000, 0xb38f0f83)
 
/* Rotate by amounts in the 1 - 31 range. */
TEST_RORI (0xb38f0f83, 0x01, 0xd9c787c1)
TEST_RORI (0xb38f0f83, 0x04, 0x3b38f0f8)
TEST_RORI (0xb38f0f83, 0x10, 0x0f83b38f)
TEST_RORI (0xb38f0f83, 0x1f, 0x671e1f07)
 
/* Rotate by larger amounts (32 - 63) - should be masked. */
TEST_RORI (0xb38f0f83, 0x21, 0xd9c787c1)
TEST_RORI (0xb38f0f83, 0x24, 0x3b38f0f8)
TEST_RORI (0xb38f0f83, 0x30, 0x0f83b38f)
TEST_RORI (0xb38f0f83, 0x3f, 0x671e1f07)
 
/* ----------------------------------------------------------------------------
* All done
* ------------------------------------------------------------------------- */
_exit:
LOAD_STR (r3, "Test completed\n")
l.jal _puts
l.nop
 
TEST_EXIT
testsuite/test-code-or1k/inst-set-test/is-ror-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: testsuite/test-code-or1k/ChangeLog =================================================================== --- testsuite/test-code-or1k/ChangeLog (revision 121) +++ testsuite/test-code-or1k/ChangeLog (revision 122) @@ -4,6 +4,7 @@ : Alignment exception handler. : Illegal instruction exception handler. * inst-set-test/is-jump-test.S: Created. + * inst-set-test/is-ror-test.S: Created. * inst-set-test/Makefile.am: Updated for new tests * inst-set-test/Makefile.in: Regenerated.
/testsuite/or1ksim.tests/inst-set-test.exp
864,3 → 864,48
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-mul-test"
 
# Run the l.ror test
run_or1ksim "ror-test" \
[list "!l.ror" \
" 0xb38f0f83 ROR 0x00000000 = 0xb38f0f83: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00000001 = 0xd9c787c1: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00000004 = 0x3b38f0f8: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00000010 = 0x0f83b38f: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x0000001f = 0x671e1f07: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00000021 = 0xd9c787c1: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00002224 = 0x3b38f0f8: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0x00f789f0 = 0x0f83b38f: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ROR 0xffffffff = 0x671e1f07: OK" \
" - exception triggered: FALSE" \
"!l.rori" \
" 0xb38f0f83 RORI 0x00 = 0xb38f0f83: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x01 = 0xd9c787c1: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x04 = 0x3b38f0f8: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x10 = 0x0f83b38f: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x1f = 0x671e1f07: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x21 = 0xd9c787c1: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x24 = 0x3b38f0f8: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x30 = 0x0f83b38f: OK" \
" - exception triggered: FALSE" \
" 0xb38f0f83 RORI 0x3f = 0x671e1f07: OK" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-ror-test"
/testsuite/ChangeLog
1,6 → 1,6
2010-06-14 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Modified output from RANGE
exception. Added tests for jump instructions.
exception. Added tests for jump and rotate right instructions.
 
2010-06-13 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Added multiplication
/testsuite/README
12,8 → 12,8
Tests are provided for the standalone simulator (or1ksim) and for the library
(libsim.a).
 
At the time of writing a total of 1,793 tests compile, run and pass. That
figure is broken down into 1,529 tests of the standalone simulator and 264
At the time of writing a total of 1,829 tests compile, run and pass. That
figure is broken down into 1,565 tests of the standalone simulator and 264
tests of the library
 
Configuration and make files are provided for further test programs. These
46,7 → 46,7
Working tests
=============
 
A total of 1,529 tests of standalone Or1ksim:
A total of 1,565 tests of standalone Or1ksim:
 
basic: 8 tests of a wide range of instructions and registers.
cache: 5 tests of the Or1ksim cache modeling
73,6 → 73,7
is-lws-test: 13 tests of the l.lws instruction (Bug 1767).
is-mac-test: 189 tests of the MAC instructions (Bugs 1773, 1777).
is-mul-test: 186 tests of the l.mul* instructions (Bug 1774).
is-ror-test: 36 tests of the l.ror and l.rori instructions (Bug 1778).
mem-test: 16 tests of simple memory access.
mmu: 110 tests of the MMU.
mul: 5 tests of the multiply functionality.
/configure
1,5 → 1,5
#! /bin/sh
# From configure.ac Id: configure.ac 1037 2010-06-13 21:08:05Z jeremy using automake version AC_ACVERSION.
# From configure.ac Id: configure.ac 1039 2010-06-14 17:57:40Z jeremy using automake version AC_ACVERSION.
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.63 for or1ksim 2010-06-14.
#

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