URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/rtos
- from Rev 622 to Rev 623
- ↔ Reverse comparison
Rev 622 → Rev 623
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/support.h
10,9 → 10,9
#include <limits.h> |
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/* Register access macros */ |
#define REG8(add) *((volatile unsigned char *)(add)) |
#define REG16(add) *((volatile unsigned short *)(add)) |
#define REG32(add) *((volatile unsigned long *)(add)) |
#define REG8(add) *((volatile unsigned char *)(add)) |
#define REG16(add) *((volatile unsigned short *)(add)) |
#define REG32(add) *((volatile unsigned long *)(add)) |
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/* For writing into SPR. */ |
void mtspr(unsigned long spr, unsigned long value); |
29,24 → 29,4
/* return value by making a syscall */ |
extern void or32_exit (int i) __attribute__ ((__noreturn__)); |
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/* Timer functions */ |
extern void start_timer(int); |
extern unsigned int read_timer(int); |
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extern unsigned long excpt_buserr; |
extern unsigned long excpt_dpfault; |
extern unsigned long excpt_ipfault; |
extern unsigned long excpt_tick; |
extern unsigned long excpt_align; |
extern unsigned long excpt_illinsn; |
extern unsigned long excpt_int; |
extern unsigned long excpt_dtlbmiss; |
extern unsigned long excpt_itlbmiss; |
extern unsigned long excpt_range; |
extern unsigned long excpt_syscall; |
extern unsigned long excpt_break; |
extern unsigned long excpt_trap; |
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#endif /* SUPPORT_H */ |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/interrupts.h
12,3 → 12,9
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/* Initialize routine */ |
int int_init(void); |
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/* Disable interrupt */ |
int int_disable(unsigned long vect); |
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/* Enable interrupt */ |
int int_enable(unsigned long vect); |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/link.ld
1,7 → 1,7
MEMORY |
{ |
vectors : ORIGIN = 0x00000000, LENGTH = 0x00001100 |
ram : ORIGIN = 0x00001200, LENGTH = 0x00080000 - 0x00001200 |
vectors : ORIGIN = 0x00000000, LENGTH = 0x00001000 |
ram : ORIGIN = 0x00001000, LENGTH = 0x00080000 - 0x00001000 |
} |
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SECTIONS |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/board.h
3,19 → 3,25
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#define MC_ENABLED 0 |
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#define IC_ENABLE 1 |
#define IC_ENABLE 0 |
#define IC_SIZE 8192 |
#define DC_ENABLE 1 |
#define DC_ENABLE 0 |
#define DC_SIZE 8192 |
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#define SYS_CLK 25000000 |
#define IN_CLK 25000000 |
#define TICKS_PER_SEC 100 |
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#define UART_BAUD_RATE 115200 |
//#define UART_NUM_CORES 2 |
#undef UART_NUM_CORES |
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#define UART_BASE 0x90000000 |
#define UART0_BAUD_RATE 115200 |
#define UART0_BASE 0x90000000 |
#define UART0_IRQ 2 |
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#define UART_IRQ 2 |
//#define GPIO_NUM_CORES 2 |
#undef GPIO_NUM_CORES |
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#define GPIO0_BASE 0x91000000 |
#define GPIO0_IRQ 3 |
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#endif |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/gpio.c
0,0 → 1,58
#include "board.h" |
#include "gpio.h" |
#include "support.h" |
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#ifdef GPIO_NUM_CORES |
const int GPIO_BASE_ADR[GPIO_NUM_CORES] = {GPIO0_BASE, GPIO1_BASE}; |
#else |
const int GPIO_BASE_ADR[1] = {GPIO0_BASE}; |
#endif |
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void gpio_init(int core) |
{ |
// interrupt setup |
// global interrupt disable |
REG32(GPIO_BASE_ADR[core] + GPIO_CTRL ) = 0x0; |
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// mask all input interrupt |
REG32(GPIO_BASE_ADR[core] + GPIO_INTE ) = 0x0; |
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// clear interrupt interrupt |
REG32(GPIO_BASE_ADR[core] + GPIO_INTS ) = 0x0; |
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// set input interrupt posedge trigering mode |
REG32(GPIO_BASE_ADR[core] + GPIO_PTRIG ) = 0xFFFFFFFF; |
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// I/O setup |
// clear all GPIO output |
REG32(GPIO_BASE_ADR[core] + GPIO_OUT ) = 0x0; |
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// set all GPIO is input |
REG32(GPIO_BASE_ADR[core] + GPIO_OE ) = 0xFFFFFFFF; |
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// disable AUX input |
REG32(GPIO_BASE_ADR[core] + GPIO_AUX ) = 0x0; |
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// Input sampling mode setup |
// use system bus clock to sampling GPIO inputs |
REG32(GPIO_BASE_ADR[core] + GPIO_ECLK ) = 0x0; |
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// ECLK active posedge |
REG32(GPIO_BASE_ADR[core] + GPIO_NEC ) = 0x0; |
} |
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void set_gpio_direction(int core, unsigned int dirs) |
{ |
REG32(GPIO_BASE_ADR[core] + GPIO_OE ) = dirs; |
} |
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unsigned int gpio_read(int core) |
{ |
return REG32(GPIO_BASE_ADR[core] + GPIO_IN ); |
} |
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void gpio_write(int core, unsigned int value) |
{ |
REG32(GPIO_BASE_ADR[core] + GPIO_OUT ) = value; |
} |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/gpio.h
0,0 → 1,23
#ifndef _GPIO_H_ |
#define _GPIO_H_ |
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#define GPIO_IN 0x00 /* GPIO input data */ |
#define GPIO_OUT 0x04 /* GPIO output data */ |
#define GPIO_OE 0x08 /* GPIO output driver enable */ |
#define GPIO_INTE 0x0C /* Interrupt enable */ |
#define GPIO_PTRIG 0x10 /* Type of event that triggers an interrupt */ |
#define GPIO_AUX 0x14 /* Multiplex auxiliary inputs to GPIO outputs */ |
#define GPIO_CTRL 0x18 /* Control register */ |
#define GPIO_INTS 0x1C /* Interrupt status */ |
#define GPIO_ECLK 0x20 /* Enable gpio_eclk to latch RGPIO_IN */ |
#define GPIO_NEC 0x24 /* Select active edge of gpio_eclk */ |
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#define GPIO_CTRL_INTE 0x01 |
#define GPIO_CTRL_INTS 0x02 |
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void gpio_init(int core); |
void set_gpio_direction(int core, unsigned int dirs); |
unsigned int gpio_read(int core); |
void gpio_write(int core, unsigned int value); |
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#endif |
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/Makefile
3,7 → 3,7
INCDIR = -I../arch |
CFLAGS += $(INCDIR) -g |
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SRC_C = uart.c |
SRC_C = uart.c gpio.c |
SRC_S = |
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OBJ_C = $(SRC_C:.c=.o) |