URL
https://opencores.org/ocsvn/pcounter/pcounter/trunk
Subversion Repositories pcounter
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/pcounter/trunk
- from Rev 1 to Rev 2
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Rev 1 → Rev 2
/pdchain.vhdl
0,0 → 1,49
-- |
-- * pipelined synchronous pulse counter * |
-- pdchain -- multi-bit counter top-level entity |
-- |
-- fast counter for slow-carry architectures |
-- non-monotonic counting, value calculable by HDL/CPU |
-- |
-- idea&code by Marek Peca <mp@duch.cz> 08/2012 |
-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/ |
-- thanks to Michael Vacek <michael.vacek@vzlu.cz> for testing |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity pdchain is |
generic ( |
n: natural := 32 |
); |
port ( |
clock: in std_logic; |
en: in std_logic; |
q: out std_logic_vector (n-1 downto 0) |
); |
end pdchain; |
|
architecture behavioral of pdchain is |
component pdivtwo |
port ( |
clock: in std_logic; |
en: in std_logic; |
q, p: out std_logic |
); |
end component; |
-- |
signal b: std_logic_vector (q'range); |
begin |
q0: pdivtwo |
port map ( |
clock => clock, en => en, p => b(0), q => q(0) |
); |
ch: for k in 1 to b'high generate |
qk: pdivtwo |
port map ( |
clock => clock, en => b(k-1), p => b(k), q => q(k) |
); |
end generate; |
end behavioral; |
/doc/pcounter_sch.pdf
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doc/pcounter_sch.pdf
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Index: doc/pcounter_4bit_trace.pdf
===================================================================
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Index: doc/pcounter_4bit_trace.pdf
===================================================================
--- doc/pcounter_4bit_trace.pdf (nonexistent)
+++ doc/pcounter_4bit_trace.pdf (revision 2)
doc/pcounter_4bit_trace.pdf
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+application/octet-stream
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Index: doc/README
===================================================================
--- doc/README (nonexistent)
+++ doc/README (revision 2)
@@ -0,0 +1,85 @@
+--
+-- * pipelined synchronous pulse counter *
+--
+-- fast counter for slow-carry architectures
+-- non-monotonic counting, value calculable by HDL/CPU
+--
+-- idea&code by Marek Peca 08/2012
+-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
+-- thanks to Michael Vacek for testing
+--
+
+Pipelined Synchronous Pulse Counter
+===================================
+
+is a proposal of binary counter, designed to minimize logic path
+length in between flip-flops to one gate (MUX/AND) only, at the
+expense of not so straightforward binary counting. The reason for this
+design has emerged while using Actel (MicroSemi) ProASIC/IGLOO
+architecture, lacking any hardwired support for fast carry.
+
+During our work on Actel FPGAs (basically, 3-LUT & DFF only), we were
+aware of following types of faster counters:
+- LFSR counter
+- Johnson counter
+- "RLA counter" (as tailored using Actel's SmartGen core generator)
+
+Johnson due to its O(2^n) (n as number of bits) can not be used for
+longer counts; LFSR's are hard to invert (table lookup seems to be
+only known method), therefore also impractical for wider counters. RLA
+counter is still too slow and complex for wider counters and moderate
+speeds (e.g. > 24bits @ >100MHz).
+
+As a consequence, the proposed counter uses synchronous divide-by-two
+blocks, each using 1-bit pipeline and carry by single-clock
+pulse. Design is simple and fast, preliminary results from Synplify
+and Actel Designer shows 32bits @200MHz feasible.
+
+However, output bit lines are non-proportionaly delayed by discrete
+number of clock periods. Therefore, to obtain linear bit word, an
+inversion formula needs to be applied. Fortunately, the inversion is
+simple (unlike LFSR's), in C (pcount.c):
+
+ for (k = 1; k < n; k++)
+ if ((y & ((1<
\ No newline at end of file
Index: COPYING
===================================================================
--- COPYING (nonexistent)
+++ COPYING (revision 2)
@@ -0,0 +1,165 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. 08/2012
+-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
+-- thanks to Michael Vacek for testing
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pdivtwo is
+ port (
+ clock: in std_logic;
+ en: in std_logic;
+ q, p: out std_logic
+ );
+end pdivtwo;
+
+architecture behavioral of pdivtwo is
+ signal state: std_logic := '1';
+ signal pipe: std_logic := '0';
+ signal next_state, next_pipe: std_logic;
+begin
+ next_state <= not state when en = '1' else state;
+ next_pipe <= state and en;
+ p <= pipe;
+ q <= state;
+
+ process
+ begin
+ wait until clock'event and clock = '1';
+ state <= next_state;
+ pipe <= next_pipe;
+ end process;
+end behavioral;
Index: pcount.c
===================================================================
--- pcount.c (nonexistent)
+++ pcount.c (revision 2)
@@ -0,0 +1,41 @@
+#include
+#include
+#include
+#include
+
+typedef unsigned long count_t;
+
+count_t pcount_decode(unsigned n, count_t b) {
+ count_t y = b;
+ unsigned k;
+ for (k = 1; k < n; k++)
+ if ((y & ((1< 0; k--)
+ if ((b & ((1< %08lx -> %08lx\n", b, y, z);
+ }
+ return 0;
+}
Index: pcount_tb.vhdl
===================================================================
--- pcount_tb.vhdl (nonexistent)
+++ pcount_tb.vhdl (revision 2)
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity pcount_tb is
+end pcount_tb;
+
+architecture test of pcount_tb is
+ component pdchain
+ generic (
+ n: natural
+ );
+ port (
+ clock: in std_logic;
+ en: in std_logic;
+ q: out std_logic_vector (n-1 downto 0)
+ );
+ end component;
+ --
+ constant T: time := 5 ns;
+ signal clock: std_logic := '0';
+ signal count: std_logic_vector (23 downto 0);
+begin
+ pdchain0: pdchain
+ generic map (
+ n => count'length
+ )
+ port map (
+ clock => clock,
+ en => '1',
+ q => count
+ );
+
+ clk: process
+ variable s: line;
+ begin
+ clock <= '1';
+ wait for T/2;
+ clock <= '0';
+ wait for T/2;
+ --
+ write(s, to_bitvector(count));
+ writeline(output, s);
+ end process;
+end test;
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 2)
@@ -0,0 +1,27 @@
+UNITS=pdchain.vhdl pdivtwo.vhdl
+UNIT_TOP=pcount_tb.vhdl
+
+TOP_EXE=$(patsubst %.vhdl,%,$(UNIT_TOP))
+COPT=--ieee=synopsys -g
+ROPT=--vcd=$(TOP_EXE).vcd --stop-time=10us
+
+
+all: $(TOP_EXE) pcount
+
+testvcd: $(TOP_EXE)
+ ghdl -r $(TOP_EXE) $(ROPT)
+
+testrun: $(TOP_EXE) pcount
+ ghdl -r $(TOP_EXE) | ./pcount
+
+$(TOP_EXE): $(UNITS) $(UNIT_TOP)
+ ghdl -i $(UNITS) $(UNIT_TOP)
+ ghdl -a $(COPT) $(UNIT_TOP)
+ ghdl -m $(COPT) $(TOP_EXE)
+
+pcount: pcount.c
+ $(CC) -Wall -O -o $@ $<
+
+clean:
+ rm -rf $(TOP_EXE) pcount
+ ghdl --remove