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/trunk/math_pipelined/atan2_pipelined.sv
0,0 → 1,207
 
 
 
`define PI_x64 (68'sd57952155664616982739/4)
 
module atan2_pipelined(
input clk,
input signed [UP:0] y,
input signed [UP:0] x,
output signed [UP:0] oangle,
output signed [UP:0] odebug
);
 
parameter BITS_HIGH= 16;
parameter BITS_LOW= 16;
parameter BITS_GUARD= 0;
 
parameter IS_IBNIZ= 0;// пїЅпїЅпїЅпїЅ 0, пїЅпїЅ f=atan2 пїЅпїЅпїЅпїЅ 1, пїЅпїЅ f=atan2/2PI
// пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ, пїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ.
 
// пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ
parameter UP= BITS_HIGH +BITS_LOW -1;
 
// пїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅ- пїЅпїЅпїЅ пїЅпїЅпїЅпїЅ(пїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅ)
parameter UPL= BITS_LOW -1;
 
// пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ "пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ" пїЅпїЅпїЅ "пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ" пїЅпїЅпїЅпїЅ пїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ
parameter UPG= UP +BITS_GUARD;
parameter UPLG= UPL +BITS_GUARD;
`define BOUT (UPL) // пїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅ
 
reg signed [UPG:0] cx [`BOUT:0];
reg signed [UPG:0] csin [`BOUT:0];
reg signed [UPG:0] ccos [`BOUT:0];
 
//wire signed [UPG:0] x0= (x[UP] ? -x : x)<<<BITS_GUARD;
 
assign oangle= cx[`BOUT]>>>(BITS_GUARD);
assign odebug= csin[`BOUT]>>>BITS_GUARD;
 
// пїЅпїЅпїЅпїЅ, пїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅ 1.00...001
wire signed [63:0] C_ANGLE [63:0];
 
//
wire signed [UPG:0] cx2 [`BOUT:0];
wire signed [UPG:0] csin2 [`BOUT:0];
wire signed [UPG:0] ccos2 [`BOUT:0];
 
 
always @*
begin
integer ind;
for (ind=0; ind< `BOUT; ind=ind+1)
begin
if ( csin[ind] >0 )
begin
cx2[ind]<= cx[ind]+ (C_ANGLE[ind] >>> (62-UPLG));
csin2[ ind ]<= csin[ ind ] - (ccos[ ind ] >>>(ind) );
ccos2[ ind ]<= ccos[ ind ] + (csin[ ind ] >>>(ind) );
end
else
begin
cx2[ind]<= cx[ind]- (C_ANGLE[ind] >>> (62-UPLG));
csin2[ ind ]<= csin[ ind ] + (ccos[ ind ] >>>(ind) );
ccos2[ ind ]<= ccos[ ind ] - (csin[ ind ] >>>(ind) );
end
end
end
 
always @( posedge clk )
begin
integer ind;
 
csin[0]= {y, {BITS_GUARD{1'h0}}};
ccos[0]= {x, {BITS_GUARD{1'h0}}};
cx[0]=0;
// пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ, CORDIC
for (ind=0; ind< `BOUT; ind=ind+1)
begin
if ( csin2[ind] >0 )
begin
cx[ind+1]<= cx2[ind]+ (C_ANGLE[ind] >>> (62-UPLG));
csin[ ind +1 ]<= csin2[ ind ] - (ccos2[ ind ] >>>(ind) );
ccos[ ind +1 ]<= ccos2[ ind ] + (csin2[ ind ] >>>(ind) );
end
else
begin
cx[ind+1]<= cx2[ind]- (C_ANGLE[ind] >>> (62-UPLG));
csin[ ind +1 ]<= csin2[ ind ] + (ccos2[ ind ] >>>(ind) );
ccos[ ind +1 ]<= ccos2[ ind ] - (csin2[ ind ] >>>(ind) );
end
end
// пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅ
// begin
// ind= UP-2;
// if ( cx[ind] >0 )
// begin
// cx[ind+1]<= cx[ind]- (C_ANGLE[ind-BITS_HIGH+1] >>> (63-UPLG));
// csin[ ind +1 ]<= s_sign[ind] ?-(csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// csin[ ind ] - (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// ccos[ ind +1 ]<= c_sign[ind] ? -(ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// ccos[ ind ] + (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// end
// else
// begin
// cx[ind+1]<= cx[ind]+ (C_ANGLE[ind-BITS_HIGH+1] >>> (63-UPLG));
// csin[ ind +1 ]<= s_sign[ind] ?-(csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
//
// ccos[ ind +1 ]<= c_sign[ind] ? -(ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// end
// s_sign[ind+1]<= s_sign[ind];
// c_sign[ind+1]<= c_sign[ind];
// end
// if ( x[UP] )
// begin
// end
// else
// begin
// cx[0]= x;
// end
end
 
//for ( i=0; i<64; i++){
// double dval= atan(1./pow(2.,i)) * pow(2.,63.); //((long long)1 << i);
// unsigned long long val= dval;
// unsigned long long val_ibn= dval/6.283185307179586476925286766559;
// cout << "assign C_ANGLE[" << dec << i << "]= IS_IBNIZ?"
// " 64'h" << hex << val_ibn << ":"
// " 64'h" << hex << val << ";" << endl;
//}
 
assign C_ANGLE[0]= IS_IBNIZ? 64'h1000000000000000: 64'h6487ed5110b46000;
assign C_ANGLE[1]= IS_IBNIZ? 64'h0972028ecef98400: 64'h3b58ce0ac3769e00;
assign C_ANGLE[2]= IS_IBNIZ? 64'h4fd9c2daf71cf40: 64'h1f5b75f92c80dd00;
assign C_ANGLE[3]= IS_IBNIZ? 64'h28888ea0eeecd20: 64'h0feadd4d5617b700;
assign C_ANGLE[4]= IS_IBNIZ? 64'h14586a1872c4d80: 64'h7fd56edcb3f7a80;
assign C_ANGLE[5]= IS_IBNIZ? 64'h0a2ebf0ac823140: 64'h3ffaab7752ec4a0;
assign C_ANGLE[6]= IS_IBNIZ? 64'h517b0f2e141318: 64'h1fff555bbb729b0;
assign C_ANGLE[7]= IS_IBNIZ? 64'h28be2a88ea2158: 64'h0fffeaaadddd4b8;
assign C_ANGLE[8]= IS_IBNIZ? 64'h145f29a368619c: 64'h7fffd5556eeedc;
assign C_ANGLE[9]= IS_IBNIZ? 64'h0a2f975d98559c: 64'h3ffffaaaab7778;
assign C_ANGLE[10]= IS_IBNIZ? 64'h517cc0048dd3d: 64'h1fffff55555bbc;
assign C_ANGLE[11]= IS_IBNIZ? 64'h28be60a54065b: 64'h0fffffeaaaaade;
assign C_ANGLE[12]= IS_IBNIZ? 64'h145f3066ff630: 64'h7fffffd555557;
assign C_ANGLE[13]= IS_IBNIZ? 64'h0a2f98360b979: 64'h3ffffffaaaaaa;
assign C_ANGLE[14]= IS_IBNIZ? 64'h517cc1b57488: 64'h1fffffff55555;
assign C_ANGLE[15]= IS_IBNIZ? 64'h28be60db5d3d: 64'h0fffffffeaaaa;
assign C_ANGLE[16]= IS_IBNIZ? 64'h145f306dc2fe: 64'h7fffffffd555;
assign C_ANGLE[17]= IS_IBNIZ? 64'h0a2f9836e40a: 64'h3ffffffffaaa;
assign C_ANGLE[18]= IS_IBNIZ? 64'h517cc1b7256: 64'h1fffffffff55;
assign C_ANGLE[19]= IS_IBNIZ? 64'h28be60db935: 64'h0fffffffffea;
assign C_ANGLE[20]= IS_IBNIZ? 64'h145f306dc9c: 64'h7fffffffffd;
assign C_ANGLE[21]= IS_IBNIZ? 64'h0a2f9836e4e: 64'h3ffffffffff;
assign C_ANGLE[22]= IS_IBNIZ? 64'h517cc1b727: 64'h1ffffffffff;
assign C_ANGLE[23]= IS_IBNIZ? 64'h28be60db93: 64'h0ffffffffff;
assign C_ANGLE[24]= IS_IBNIZ? 64'h145f306dc9: 64'h7fffffffff;
assign C_ANGLE[25]= IS_IBNIZ? 64'h0a2f9836e4: 64'h3fffffffff;
assign C_ANGLE[26]= IS_IBNIZ? 64'h517cc1b72: 64'h1fffffffff;
assign C_ANGLE[27]= IS_IBNIZ? 64'h28be60db9: 64'h1000000000;
assign C_ANGLE[28]= IS_IBNIZ? 64'h145f306dc: 64'h0800000000;
assign C_ANGLE[29]= IS_IBNIZ? 64'h0a2f9836e: 64'h400000000;
assign C_ANGLE[30]= IS_IBNIZ? 64'h517cc1b7: 64'h200000000;
assign C_ANGLE[31]= IS_IBNIZ? 64'h28be60db: 64'h100000000;
assign C_ANGLE[32]= IS_IBNIZ? 64'h145f306d: 64'h080000000;
assign C_ANGLE[33]= IS_IBNIZ? 64'h0a2f9836: 64'h40000000;
assign C_ANGLE[34]= IS_IBNIZ? 64'h517cc1b: 64'h20000000;
assign C_ANGLE[35]= IS_IBNIZ? 64'h28be60d: 64'h10000000;
assign C_ANGLE[36]= IS_IBNIZ? 64'h145f306: 64'h08000000;
assign C_ANGLE[37]= IS_IBNIZ? 64'h0a2f983: 64'h4000000;
assign C_ANGLE[38]= IS_IBNIZ? 64'h517cc1: 64'h2000000;
assign C_ANGLE[39]= IS_IBNIZ? 64'h28be60: 64'h1000000;
assign C_ANGLE[40]= IS_IBNIZ? 64'h145f30: 64'h0800000;
assign C_ANGLE[41]= IS_IBNIZ? 64'h0a2f98: 64'h400000;
assign C_ANGLE[42]= IS_IBNIZ? 64'h517cc: 64'h200000;
assign C_ANGLE[43]= IS_IBNIZ? 64'h28be6: 64'h100000;
assign C_ANGLE[44]= IS_IBNIZ? 64'h145f3: 64'h080000;
assign C_ANGLE[45]= IS_IBNIZ? 64'h0a2f9: 64'h40000;
assign C_ANGLE[46]= IS_IBNIZ? 64'h517c: 64'h20000;
assign C_ANGLE[47]= IS_IBNIZ? 64'h28be: 64'h10000;
assign C_ANGLE[48]= IS_IBNIZ? 64'h145f: 64'h08000;
assign C_ANGLE[49]= IS_IBNIZ? 64'h0a2f: 64'h4000;
assign C_ANGLE[50]= IS_IBNIZ? 64'h517: 64'h2000;
assign C_ANGLE[51]= IS_IBNIZ? 64'h28b: 64'h1000;
assign C_ANGLE[52]= IS_IBNIZ? 64'h145: 64'h0800;
assign C_ANGLE[53]= IS_IBNIZ? 64'h0a2: 64'h400;
assign C_ANGLE[54]= IS_IBNIZ? 64'h51: 64'h200;
assign C_ANGLE[55]= IS_IBNIZ? 64'h28: 64'h100;
assign C_ANGLE[56]= IS_IBNIZ? 64'h14: 64'h080;
assign C_ANGLE[57]= IS_IBNIZ? 64'h0a: 64'h40;
assign C_ANGLE[58]= IS_IBNIZ? 64'h5: 64'h20;
assign C_ANGLE[59]= IS_IBNIZ? 64'h2: 64'h10;
assign C_ANGLE[60]= IS_IBNIZ? 64'h1: 64'h08;
assign C_ANGLE[61]= IS_IBNIZ? 64'h0: 64'h4;
assign C_ANGLE[62]= IS_IBNIZ? 64'h0: 64'h2;
assign C_ANGLE[63]= IS_IBNIZ? 64'h0: 64'h1;
endmodule
 
/trunk/math_pipelined/math_pipelined.sv
0,0 → 1,192
 
module mull_pipelined(
input clk,
input [7:0] x,
input [7:0] y,
output [15:0] z
);
reg [7:0] cx [7:0];
reg [7:0] cy [7:0];
reg [15:0] cz [15:0];
assign z= cz[7];
 
always @( posedge clk )
begin : multblk
integer ind;
cx[0]<= x;
cy[0]<= y;
cz[0]<= y[0]? x : 0;
for (ind=0; ind<6; ind=ind+1)
begin
cy[ind+1]<= cy[ind];
cx[ind+1]<= cx[ind];
cz[ind+1]<= cz[ind] + (cy[ind][ind+1]? (cx[ind]<<(ind+1)) : 0);
end
cz[7]<= cz[6] + (cy[6][7]? cx[6] : 0);
end
endmodule
//module div_pipelined(
// input clk,
// input [15:0] x,
// input [7:0] y,
// output [7:0] z
// );
//
//parameter BITS= 8;
//
//reg [15:0] cx [15:0];
//reg [7:0] cy [7:0];
//reg [7:0] cz [7:0];
//assign z= cz[7];
//
//wire [15:0] candidate [7:0];
//
//assign candidate[0]= x- (y<<7);
//
//`define MY_EXPR(ind) assign candidate[(ind+1)]= cx[(ind)]- (cy[(ind)]<<(6-ind))
//
//`MY_EXPR( 0 );
//`MY_EXPR( 1 );
//`MY_EXPR( 2 );
//`MY_EXPR( 3 );
//`MY_EXPR( 4 );
//`MY_EXPR( 5 );
//`MY_EXPR( 6 );
//
//always @( posedge clk )
//begin : multblk
// integer ind;
// integer j;
// cx[0]<= candidate[0][15] ? x : candidate[0];
// cy[0]<= y;
// cz[0][7]<= candidate[0][15] ? 0 : 1;
// for (ind=0; ind<6; ind=ind+1)
// begin
// cy[ind+1]<= cy[ind];
// cx[ind+1]<= candidate[ind+1][15] ? cx[ind] : candidate[ind+1];
// cz[ind+1][6-ind]<= candidate[ind+1][15] ? 0 : 1;
// for (j=7; j>6-ind; j=j-1)
// begin
// cz[ind+1][j]<= cz[ind][j];
// end
// end
// cz[7][0]<= candidate[7][15] ? 0 : 1;
// cz[7][7:1]<=cz[6][7:1];
//end
//endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module div_pipelined(
input clk,
input [D_UP:0] x,
input [UP:0] y,
output [UP:0] z
);
 
parameter BITS= 48;
// ���������� ���������, �� ��������������.
parameter UP= BITS-1;
parameter D_UP= 2*BITS-1;
reg [D_UP:0] cx [UP:0];
reg [UP:0] cy [UP:0];
reg [UP:0] cz [UP:0];
reg csign [UP:0];
 
assign z= (csign[UP] ? -cz[UP]:cz[UP]);
 
wire [D_UP:0] candidate [UP:0];
 
wire [D_UP:0] ux= ( (x[D_UP]) ? (-x):x );
wire [UP:0] uy= ( (y[UP]) ? (-y):y );
wire [D_UP:0] _uy= uy;
 
wire [D_UP:0] _cy [UP:0];
 
always @*
begin
integer ind;
candidate[0]<= ux- (_uy<<UP);
for (ind=0; ind< BITS-2 ; ind=ind+1)
begin
_cy <= cy;
candidate[ind+1]<= cx[ind]- (_cy[ind]<<(BITS-2-ind));
end
end
 
 
always @( posedge clk )
begin : multblk
integer ind;
integer j;
csign[0]= x[D_UP]^y[UP];
cx[0]<= candidate[0][D_UP] ? ux : candidate[0];
cy[0]<= uy;
cz[0][UP]<= ~candidate[0][D_UP]; // !!! sign bit?
for (ind=0; ind< BITS-1 ; ind=ind+1)
begin
cy[ind+1]<= cy[ind];
cx[ind+1]<= candidate[ind+1][D_UP] ? cx[ind] : candidate[ind+1];
cz[ind+1][ BITS-2 -ind]<= ~candidate[ind+1][D_UP];
csign[ind+1]<= csign[ind];
for (j=UP; j> BITS-2 -ind; j=j-1)
begin
cz[ind+1][j]<= cz[ind][j];
end
end
// cz[UP][0]<= ~candidate[UP][D_UP];
// cz[UP][UP:1]<=cz[ BITS-2 ][UP:1];
// csign[UP]<= csign[UP-1];
end
endmodule
 
 
module id_pipelined(
input clk,
input [UP:0] i,
output [UP:0] o
);
 
parameter BITS= 32;
parameter DELAY= 32;
// ���������� ���������, �� ��������������.
parameter UP= BITS-1;
reg [UP:0] cx [DELAY];
 
assign o= cx[DELAY-1];
 
always @( posedge clk )
begin : blk
integer ind;
cx[0]<= i;
for (ind=0; ind< DELAY-1 ; ind=ind+1)
begin
cx[ind+1]<= cx[ind];
end
end
endmodule
 
/trunk/math_pipelined/sin_pipelined.sv
0,0 → 1,280
 
 
 
`define PI_x64 (68'sd57952155664616982739/4)
`define K_DEFORM (64'h26dd3b6a10d7969a)
 
module sin_pipelined(
input clk,
input signed [UP:0] x,
output signed [UP:0] osin, //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
output signed [UP:0] ocos,
output signed [UP:0] odebug
);
 
parameter BITS_HIGH= 16;
parameter BITS_LOW= 16;
parameter BITS_GUARD= 2;
 
 
 
parameter UP= BITS_HIGH +BITS_LOW -1;
 
 
parameter UPL= BITS_LOW -1;
 
 
parameter UPG= UP +BITS_GUARD;
parameter UPLG= UPL +BITS_GUARD;
 
reg signed [UPG:0] cx [`BOUT:0];
 
reg signed [UPLG+1:0] csin [`BOUT:BITS_HIGH-1];//!!!+2!!!!
reg signed [UPLG+1:0] ccos [`BOUT:BITS_HIGH-1];
 
wire signed [UPG:0] x0= (x[UP] ? -x : x)<<<BITS_GUARD;
 
//wire [UP:0] p_osin= s_sign[BITS_HIGH-1]? (-cx[BITS_HIGH-1]>>BITS_GUARD): cx[BITS_HIGH-1]>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
//wire [UP:0] p_osin= s_sign[BITS_HIGH+1]? (-csin[BITS_HIGH+1][UPLG:BITS_GUARD]>>BITS_GUARD): csin[BITS_HIGH+1][UPLG:BITS_GUARD]>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
//wire [UPL:0] p_osin= csin[BITS_HIGH][UPLG:BITS_GUARD];
//wire [UPL:0] p_osin= csin[UPL][UPLG:BITS_GUARD] +csin[UPL][BITS_GUARD-1];
 
assign osin= csin[`BOUT]>>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
assign ocos= ccos[`BOUT]>>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
assign odebug= cx[`BOUT]>>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
 
//assign osin= s_sign[`BOUT]? (-cx[`BOUT]>>BITS_GUARD): cx[`BOUT]>>>BITS_GUARD; // !!!!!!!!!!!!!!!!!!!!!
//assign ocos= ccos[UPL][UPLG:BITS_GUARD] +ccos[UPL][BITS_GUARD-1];
 
 
wire signed [63:0] C_ANGLE [63:0];
 
reg s_sign [UP:0];
reg c_sign [UP:BITS_HIGH-2];
reg xy_swap [UP:BITS_HIGH-1];
 
always @( posedge clk )
begin
integer ind;
 
 
for (ind=0; ind< BITS_HIGH-4; ind=ind+1)
begin
end
 
// x <- x-Pi*n
// s_sign[BITS_HIGH-2]<= ( cx[BITS_HIGH-3]- (`PI_x64>>(67-(UPG-(BITS_HIGH-3)) )) >0
// ? s_sign[BITS_HIGH-3] : ~s_sign[BITS_HIGH-3] );
//
// c_sign[BITS_HIGH-2]<= ( cx[BITS_HIGH-3]- (`PI_x64>>(67-(UPG-(BITS_HIGH-3)) )) >0
// ? s_sign[BITS_HIGH-3] : ~s_sign[BITS_HIGH-3] );
// x <- x-Pi*n/2
// s_sign[BITS_HIGH-1]<= s_sign[BITS_HIGH-2];
 
 
s_sign[0]<= x[UP];
cx[0]<= ( x0- (`PI_x64>>>(65-(UPG) )) >0 ? x0- (`PI_x64>>>(65-(UPG) )) : x0 );
 
for (ind=0; ind< BITS_HIGH-4; ind=ind+1)
begin
cx[ind+1]<= ( cx[ind]- (`PI_x64>>>(66-(UPG-ind) )) >0 ? cx[ind]- (`PI_x64>>>(66-(UPG-ind) )) : cx[ind] );
s_sign[ind+1]<= s_sign[ind];
end
// for (ind=BITS_HIGH-4; ind< BITS_HIGH-1; ind=ind+1)
begin
 
ind= BITS_HIGH-4;
if ( cx[ind]- (`PI_x64>>>(66-(UPG-ind) )) >0 )
begin
cx[ind+1]<= (`PI_x64>>>(65-(UPG-ind) ))-cx[ind];
s_sign[ind+1]<= ~s_sign[ind];
end
else
begin
cx[ind+1]<= cx[ind];
s_sign[ind+1]<= s_sign[ind];
end
end
begin
ind= BITS_HIGH-3;
if ( cx[ind]- (`PI_x64>>>(66-(UPG-ind) )) >0 )
begin
cx[ind+1]<= (`PI_x64>>>(65-(UPG-ind) ))-cx[ind];
s_sign[ind+1]<= s_sign[ind];
c_sign[ind+1]<= 1'h1;
end
else
begin
cx[ind+1]<= cx[ind];
s_sign[ind+1]<= s_sign[ind];
c_sign[ind+1]<= 1'h0;
end
end
begin
ind= BITS_HIGH-2;
if ( cx[ind] > (`PI_x64>>(66-(UPG-ind) )) )
begin
cx[ind+1]<= (s_sign[ind]^c_sign[ind]) ? ((`PI_x64>>>(65-(UPG-ind) ))-cx[ind]) : -((`PI_x64>>>(65-(UPG-ind) ))-cx[ind]);
csin[ind+1]<= 0;
ccos[ind+1]<= -(`K_DEFORM>>(64-UPLG-3))
+(1<<BITS_GUARD); // to avoid results >=|1.0|, if you prefer more precision, you need to
// csin[ind+1]<= s_sign[ind] ? -(64'sh9B74) : 64'sh9B74;
// ccos[ind+1]<= 0;
end
else
begin
cx[ind+1]<= (s_sign[ind]^c_sign[ind]) ? -(cx[ind]) : (cx[ind]);
csin[ind+1]<= 0;
ccos[ind+1]<= (`K_DEFORM>>(64-UPLG-3))
-(1<<BITS_GUARD); // to avoid results >=|1.0|
// csin[ind+1]<= 0;
// ccos[ind+1]<= c_sign[ind] ? -(64'sh9B74) : 64'sh9B74;
end
s_sign[ind+1]<= 0;
c_sign[ind+1]<= 0;
end
 
`define BHm1 (BITS_HIGH-1)
 
// cx[16]<= cx[15]- 32'sh00003000;//(C_ANGLE[ind-`BHm1] >> (64-UPLG));
 
 
for (ind=`BHm1; ind< `BOUT; ind=ind+1)
 
 
 
 
begin
if ( cx[ind] >0 )
begin
 
 
 
cx[ind+1]<= cx[ind]- (C_ANGLE[ind-`BHm1] >>> (64-UPLG));
csin[ ind +1 ]<= csin[ ind ] + (ccos[ ind ] >>>(ind-`BHm1 ) );
ccos[ ind +1 ]<= ccos[ ind ] - (csin[ ind ] >>>(ind-`BHm1 ) );
end
else
begin
 
cx[ind+1]<= cx[ind]+ (C_ANGLE[ind-`BHm1] >>> (64-UPLG));
csin[ ind +1 ]<= csin[ ind ] - (ccos[ ind ] >>>(ind-`BHm1 ) );
ccos[ ind +1 ]<= ccos[ ind ] + (csin[ ind ] >>>(ind-`BHm1 ) );
end
end
 
// begin
// ind= UP-2;
// if ( cx[ind] >0 )
// begin
// cx[ind+1]<= cx[ind]- (C_ANGLE[ind-BITS_HIGH+1] >>> (63-UPLG));
// csin[ ind +1 ]<= s_sign[ind] ?-(csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// csin[ ind ] - (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// ccos[ ind +1 ]<= c_sign[ind] ? -(ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// ccos[ ind ] + (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// end
// else
// begin
// cx[ind+1]<= cx[ind]+ (C_ANGLE[ind-BITS_HIGH+1] >>> (63-UPLG));
// csin[ ind +1 ]<= s_sign[ind] ?-(csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// csin[ ind ] + (ccos[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
//
// ccos[ ind +1 ]<= c_sign[ind] ? -(ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) )) :
// ccos[ ind ] - (csin[ ind ] >>>(ind-(BITS_HIGH-1) +1) );
// end
// s_sign[ind+1]<= s_sign[ind];
// c_sign[ind+1]<= c_sign[ind];
// end
// if ( x[UP] )
// begin
// end
// else
// begin
// cx[0]= x;
// end
end
 
// for ( i=0; i<64; i++){
// double dval= atan(1./pow(2.,i)) * pow(2.,63.); //((long long)1 << i);
// unsigned long long val= dval;
// cout << "assign C_ANGLE[" << dec << i << "]= 64'h" << hex << val << ";" << endl;
// }
 
assign C_ANGLE[0] = 64'sh6487ed5110b46000;
assign C_ANGLE[1] = 64'sh3b58ce0ac3769e00;
assign C_ANGLE[2] = 64'sh1f5b75f92c80dd00;
assign C_ANGLE[3] = 64'shfeadd4d5617b700;
assign C_ANGLE[4] = 64'sh7fd56edcb3f7a80;
assign C_ANGLE[5] = 64'sh3ffaab7752ec4a0;
assign C_ANGLE[6] = 64'sh1fff555bbb729b0;
assign C_ANGLE[7] = 64'shfffeaaadddd4b8;
assign C_ANGLE[8] = 64'sh7fffd5556eeedc;
assign C_ANGLE[9] = 64'sh3ffffaaaab7778;
assign C_ANGLE[10]= 64'sh1fffff55555bbc;
assign C_ANGLE[11]= 64'shfffffeaaaaade;
assign C_ANGLE[12]= 64'sh7fffffd555557;
assign C_ANGLE[13]= 64'sh3ffffffaaaaaa;
assign C_ANGLE[14]= 64'sh1fffffff55555;
assign C_ANGLE[15]= 64'shfffffffeaaaa;
assign C_ANGLE[16]= 64'sh7fffffffd555;
assign C_ANGLE[17]= 64'sh3ffffffffaaa;
assign C_ANGLE[18]= 64'sh1fffffffff55;
assign C_ANGLE[19]= 64'shfffffffffea;
assign C_ANGLE[20]= 64'sh7fffffffffd;
assign C_ANGLE[21]= 64'sh3ffffffffff;
assign C_ANGLE[22]= 64'sh1ffffffffff;
assign C_ANGLE[23]= 64'shffffffffff;
assign C_ANGLE[24]= 64'sh7fffffffff;
assign C_ANGLE[25]= 64'sh3fffffffff;
assign C_ANGLE[26]= 64'sh1fffffffff;
assign C_ANGLE[27]= 64'sh1000000000;
assign C_ANGLE[28]= 64'sh800000000;
assign C_ANGLE[29]= 64'sh400000000;
assign C_ANGLE[30]= 64'sh200000000;
assign C_ANGLE[31]= 64'sh100000000;
assign C_ANGLE[32]= 64'sh80000000;
assign C_ANGLE[33]= 64'sh40000000;
assign C_ANGLE[34]= 64'sh20000000;
assign C_ANGLE[35]= 64'sh10000000;
assign C_ANGLE[36]= 64'sh8000000;
assign C_ANGLE[37]= 64'sh4000000;
assign C_ANGLE[38]= 64'sh2000000;
assign C_ANGLE[39]= 64'sh1000000;
assign C_ANGLE[40]= 64'sh800000;
assign C_ANGLE[41]= 64'sh400000;
assign C_ANGLE[42]= 64'sh200000;
assign C_ANGLE[43]= 64'sh100000;
assign C_ANGLE[44]= 64'sh80000;
assign C_ANGLE[45]= 64'sh40000;
assign C_ANGLE[46]= 64'sh20000;
assign C_ANGLE[47]= 64'sh10000;
assign C_ANGLE[48]= 64'sh8000;
assign C_ANGLE[49]= 64'sh4000;
assign C_ANGLE[50]= 64'sh2000;
assign C_ANGLE[51]= 64'sh1000;
assign C_ANGLE[52]= 64'sh800;
assign C_ANGLE[53]= 64'sh400;
assign C_ANGLE[54]= 64'sh200;
assign C_ANGLE[55]= 64'sh100;
assign C_ANGLE[56]= 64'sh80;
assign C_ANGLE[57]= 64'sh40;
assign C_ANGLE[58]= 64'sh20;
assign C_ANGLE[59]= 64'sh10;
assign C_ANGLE[60]= 64'sh8;
assign C_ANGLE[61]= 64'sh4;
assign C_ANGLE[62]= 64'h2;
assign C_ANGLE[63]= 64'h1;
endmodule
 
/trunk/math_pipelined/sqrt_pipelined.sv
0,0 → 1,66
 
 
 
module sqrt_pipelined(
input clk,
input [UP:0] x,
output [UP:0] osqrt,
output [UP:0] odebug
);
 
parameter BITS= 32;
 
 
 
parameter UP= BITS-1;
 
reg [UP:0] cr [UP:0];
reg [UP:0] crr [UP:0];
reg [UP:0] _crr [UP:0];
 
reg [UP:0] cx [UP:0];
 
 
 
assign osqrt= cr[`BOUT];
assign odebug= crr[`BOUT];
 
always @( posedge clk )
begin
integer ind;
 
 
 
cx[0]<= x;
// cr[0]<= 32'h00800000;
// crr[0]<= 32'h40000000;
`define MEDI (64'h0000000000000001<<(BITS-1) )
`define MEDI2 (64'h0000000000000001<<(BITS-1))
cr[0]<= `MEDI;
crr[0]<= `MEDI2;
 
for (ind=0; ind< UP; ind=ind+1)
begin
if ( cx[ind]>crr[ind] )
begin
cr [ind+1]<= cr [ind] + (`MEDI>>(ind+1));
// _crr [ind+1]<= (cr [ind] + (`MEDI>>(ind+1)) )*(cr [ind] + (`MEDI>>(ind+1)) );
crr[ind+1]<= crr [ind] + (`MEDI2>>(2*(ind+1))) + ( (cr[ind])>>(ind) );
end
else
begin
cr [ind+1]<= cr [ind] - (`MEDI>>(ind+1));
// _crr [ind+1]<= (cr [ind] - (`MEDI>>(ind+1)) )*(cr [ind] - (`MEDI>>(ind+1)) );
crr[ind+1]<= crr [ind] + (`MEDI2>>(2*(ind+1))) - ( (cr[ind])>>(ind) );
end
cx [ind+1]<= cx [ind];
end
end
 
endmodule
 
/trunk/math_pipelined/exp_pipelined.sv
0,0 → 1,139
 
module exp_pipelined(
input clk,
input signed [ARG_HIGH+ ARG_LOW-1:0] ix,
output [RES_HIGH+ RES_LOW-1:0] oexp
);
 
parameter ARG_HIGH= 4;
parameter ARG_LOW= 16;
parameter ARG_GUARD= 0;
 
parameter RES_HIGH= 16;
parameter RES_LOW= 16;
parameter RES_GUARD= 0;
 
 
parameter A_BITS= ARG_HIGH+ ARG_LOW+ ARG_GUARD;
parameter A_UP= A_BITS-1;
 
parameter R_BITS= RES_HIGH+ RES_LOW+ RES_GUARD;
parameter STEPS= RES_HIGH+ RES_LOW;
parameter R_UP= R_BITS-1;
 
bit [A_UP:0] x [STEPS:0];
bit [R_UP:0] bexp [STEPS:0];
 
assign oexp= bexp[STEPS]>>RES_GUARD;
 
`define LN2x64 (64'hB17217F7D1CF79AB)
wire signed [63:0] C_LN_10001 [63:0]; // Ln(1+1/2^x)
 
always @( posedge clk )
begin
integer ind;
 
x[0]<= ix<<<ARG_GUARD;
bexp[0]<= 64'h1<<(RES_LOW+RES_GUARD);
for (ind=0; ind<ARG_HIGH; ind++ )
begin
if ( x[ind]>(`LN2x64>>( 64-A_BITS+ind )) )
begin
x [ind+1]<= x[ind] - (`LN2x64>>( 64-A_BITS+ind ));
bexp[ind+1]<= bexp[ind]<<(64'h1<<(ARG_HIGH-ind-1));
end
else
begin
x [ind+1]<= x [ind];
bexp[ind+1]<= bexp[ind];
end
end
for (ind=ARG_HIGH; ind<STEPS; ind++ )
begin
if ( x[ind]>(C_LN_10001[ind-ARG_HIGH]>>( 67-A_BITS )) )
begin
x [ind+1]<= x[ind] - (C_LN_10001[ind-ARG_HIGH]>>( 67-A_BITS ));
bexp[ind+1]<= bexp[ind] + (bexp[ind]>>(ind-ARG_HIGH+1));
end
else
begin
x [ind+1]<= x [ind];
bexp[ind+1]<= bexp[ind];
end
end
end
 
// for ( i=0; i<64; i++){
// double dval= log(1+1./pow(2.,1+i)) * pow(2.,64.); //((long long)1 << i);
// unsigned long long val= i>30 ? 1ull<<(63-i) :dval;
// cout << "assign C_LN_10001[" << dec << i << "]= 64'h" << hex << val << ";" << endl;
// }
 
 
assign C_LN_10001[1]= 64'h391fef8f35344400;
assign C_LN_10001[2]= 64'h1e27076e2af2e600;
assign C_LN_10001[3]= 64'hf85186008b15300;
assign C_LN_10001[4]= 64'h7e0a6c39e0cc000;
assign C_LN_10001[5]= 64'h3f815161f807c80;
assign C_LN_10001[6]= 64'h1fe02a6b1067890;
assign C_LN_10001[7]= 64'hff805515885e00;
assign C_LN_10001[8]= 64'h7fe00aa6ac4398;
assign C_LN_10001[9]= 64'h3ff80155156220;
assign C_LN_10001[10]= 64'h1ffe002aa6ab11;
assign C_LN_10001[11]= 64'hfff8005551558;
assign C_LN_10001[12]= 64'h7ffe000aaa6aa;
assign C_LN_10001[13]= 64'h3fff800155515;
assign C_LN_10001[14]= 64'h1fffe0002aaa6;
assign C_LN_10001[15]= 64'hffff80005555;
assign C_LN_10001[16]= 64'h7fffe0000aaa;
assign C_LN_10001[17]= 64'h3ffff8000155;
assign C_LN_10001[18]= 64'h1ffffe00002a;
assign C_LN_10001[19]= 64'hfffff800005;
assign C_LN_10001[20]= 64'h7ffffe00000;
assign C_LN_10001[21]= 64'h3fffff80000;
assign C_LN_10001[22]= 64'h1fffffe0000;
assign C_LN_10001[23]= 64'hffffff8000;
assign C_LN_10001[24]= 64'h7fffffe000;
assign C_LN_10001[25]= 64'h3ffffff800;
assign C_LN_10001[26]= 64'h1ffffffe00;
assign C_LN_10001[27]= 64'hfffffff80;
assign C_LN_10001[28]= 64'h7ffffffe0;
assign C_LN_10001[29]= 64'h3fffffff8;
assign C_LN_10001[30]= 64'h1fffffffe;
assign C_LN_10001[31]= 64'h100000000;
assign C_LN_10001[32]= 64'h80000000;
assign C_LN_10001[33]= 64'h40000000;
assign C_LN_10001[34]= 64'h20000000;
assign C_LN_10001[35]= 64'h10000000;
assign C_LN_10001[36]= 64'h8000000;
assign C_LN_10001[37]= 64'h4000000;
assign C_LN_10001[38]= 64'h2000000;
assign C_LN_10001[39]= 64'h1000000;
assign C_LN_10001[40]= 64'h800000;
assign C_LN_10001[41]= 64'h400000;
assign C_LN_10001[42]= 64'h200000;
assign C_LN_10001[43]= 64'h100000;
assign C_LN_10001[44]= 64'h80000;
assign C_LN_10001[45]= 64'h40000;
assign C_LN_10001[46]= 64'h20000;
assign C_LN_10001[47]= 64'h10000;
assign C_LN_10001[48]= 64'h8000;
assign C_LN_10001[49]= 64'h4000;
assign C_LN_10001[50]= 64'h2000;
assign C_LN_10001[51]= 64'h1000;
assign C_LN_10001[52]= 64'h800;
assign C_LN_10001[53]= 64'h400;
assign C_LN_10001[54]= 64'h200;
assign C_LN_10001[55]= 64'h100;
assign C_LN_10001[56]= 64'h80;
assign C_LN_10001[57]= 64'h40;
assign C_LN_10001[58]= 64'h20;
assign C_LN_10001[59]= 64'h10;
assign C_LN_10001[60]= 64'h8;
assign C_LN_10001[61]= 64'h4;
assign C_LN_10001[62]= 64'h2;
assign C_LN_10001[63]= 64'h1;
 
endmodule
 
 

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