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/qaz_libs/trunk/tb_class/src/tb_clk.sv
1,6 → 1,29
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
/qaz_libs/trunk/tb_class/src/tb_base.sv
1,6 → 1,29
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
/qaz_libs/trunk/tb_class/src/tb_clk_class.sv
1,5 → 1,29
// --------------------------------------------------------------------
//
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
/qaz_libs/trunk/FIFOs/src/ohmkara/sync_fifo.v
0,0 → 1,90
///////////////////////////////////////////////
// Author: Deepak (28/03/2009 08:54)
// Module: fifo.v
// Project:
// Description: Synchronous FIFO
// data output (dout) is un-registered.
// Version: 1.1 (not icarus verilog compatible)
//
///////////////////////////////////////////////
module sync_fifo
#(
parameter DATA_WIDTH = 8,
parameter DEPTH = 8</pre>
)
(
input [DATA_WIDTH-1:0] din,
input wr_en,
input rd_en,
output [DATA_WIDTH-1:0] dout,
output reg full,
output reg empty,
input clk,
input reset
);
function integer log2;
input integer n;
begin
log2 = 0;
while(2**log2 < n) begin
log2=log2+1;
end
end
endfunction
parameter ADDR_WIDTH = log2(DEPTH);
reg [ADDR_WIDTH : 0] rd_ptr; // note MSB is not really address
reg [ADDR_WIDTH : 0] wr_ptr; // note MSB is not really address
wire [ADDR_WIDTH-1 : 0] wr_loc;
wire [ADDR_WIDTH-1 : 0] rd_loc;
reg [DATA_WIDTH-1 : 0] mem[DEPTH-1 : 0];
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
always @(posedge clk) begin
if(reset) begin
wr_ptr <= 'h0;
rd_ptr <= 'h0;
end // end if
else begin
if(wr_en & (~full))begin
wr_ptr <= wr_ptr+1;
end
if(rd_en & (~empty))
rd_ptr <= rd_ptr+1;
end //end else
end//end always
//empty if all the bits of rd_ptr and wr_ptr are the same.
//full if all bits except the MSB are equal and MSB differes
always @(rd_ptr or wr_ptr)begin
//default catch-alls
empty <= 1'b0;
full <= 1'b0;
if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
empty <= 1'b1;
else
full <= 1'b1;
end//end if
end//end always
always @(posedge clk) begin
if (wr_en)
mem[wr_loc] <= din;
end //end always
//comment if you want a registered dout
assign dout = rd_en ? mem[rd_loc]:'h0;
//uncomment if you want a registered dout
//always @(posedge clk) begin
// if (reset)
// dout <= 'h0;
// else if (rd_en)
// dout <= mem[rd_ptr];
//end
endmodule
/qaz_libs/trunk/FIFOs/src/fifo_write_if.sv
0,0 → 1,117
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
interface
fifo_write_if
#(
W = 8 // data bus width in bits
)
(
input clk,
input reset
);
wire almost_full;
wire full;
wire [W-1:0] wr_data;
wire wr_en;
 
 
// --------------------------------------------------------------------
//
default clocking cb_f @(posedge clk iff ~reset);
default output #1;
input reset;
input clk;
output almost_full;
output full;
input wr_data;
input wr_en;
endclocking
 
 
// --------------------------------------------------------------------
//
clocking cb_s @(negedge clk iff ~reset);
input reset;
input clk;
input almost_full;
input full;
output wr_data;
output wr_en;
endclocking
 
 
// --------------------------------------------------------------------
//
modport
fifo
(
input reset,
input clk,
output almost_full,
output full,
input wr_data,
input wr_en,
clocking cb_f
);
 
 
// --------------------------------------------------------------------
//
modport
source
(
input reset,
input clk,
input almost_full,
input full,
output wr_data,
output wr_en,
clocking cb_s
);
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
 
 
endinterface
 
 
/qaz_libs/trunk/FIFOs/src/sync_fifo.v
0,0 → 1,78
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
sync_fifo
(
input [12:0] fifo_wr_data,
output reg [12:0] fifo_rd_data,
input fifo_wr_en,
input fifo_rd_en,
 
output reg fifo_full,
output reg fifo_empty,
 
input fifo_clock,
input fifo_reset
);
 
// -----------------------------
//
wire wr_en = fifo_wr_en & ~fifo_full;
reg [2:0] wr_ptr;
 
always @( posedge fifo_clock )
if( fifo_reset )
wr_ptr <= 0;
else if( wr_en )
wr_ptr <= wr_ptr + 1;
 
wire rd_en = fifo_rd_en & ~fifo_empty;
reg [2:0] rd_ptr;
 
always @( posedge fifo_clock )
if( fifo_reset )
rd_ptr <= 0;
else if( rd_en )
rd_ptr <= rd_ptr + 1;
 
 
// -----------------------------
//
wire ptr_are_equal = wr_ptr[1:0] == rd_ptr[1:0];
wire ptr_msb_are_equal = ~(wr_ptr[2] ^ rd_ptr[2]);
 
always @( posedge fifo_clock )
if( fifo_reset )
fifo_full <= 0;
else
fifo_full <= ptr_are_equal & ~ptr_msb_are_equal ;
 
always @( posedge fifo_clock )
if( fifo_reset )
fifo_empty <= 1;
else
fifo_empty <= ptr_are_equal & ptr_msb_are_equal ;
 
 
// -----------------------------
//
reg [12:0] reg_file[3:0];
 
always @( posedge fifo_clock )
if( wr_en )
reg_file[wr_ptr[1:0]] <= fifo_wr_data;
 
// always @( posedge fifo_clock )
// if( rd_en )
// fifo_rd_data <= reg_file[rd_ptr[1:0]];
 
always @( * )
fifo_rd_data <= reg_file[rd_ptr[1:0]];
 
 
endmodule
 
 
/qaz_libs/trunk/FIFOs/src/fifo_read_if.sv
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
fifo_read_if
#(
W = 8 // data bus width in bits
)
(
input clk,
input reset
);
wire almost_empty;
wire empty;
wire [W-1:0] rd_data;
wire rd_en;
 
 
// --------------------------------------------------------------------
//
default clocking cb_f @(posedge clk iff ~reset);
input reset;
input clk;
output almost_empty;
output empty;
output rd_data;
input rd_en;
endclocking
 
 
// --------------------------------------------------------------------
//
clocking cb_s @(negedge clk iff ~reset);
input reset;
input clk;
input almost_empty;
input empty;
input rd_data;
output rd_en;
endclocking
 
 
// --------------------------------------------------------------------
//
modport
fifo
(
input reset,
input clk,
output almost_empty,
output empty,
output rd_data,
input rd_en,
clocking cb_f
);
 
 
// --------------------------------------------------------------------
//
modport
sink
(
input reset,
input clk,
input almost_empty,
input empty,
input rd_data,
output rd_en,
clocking cb_s
);
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
 
 
endinterface
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/wptr_full.v
0,0 → 1,33
// --------------------------------------------------------------------
//
 
 
module wptr_full #(parameter ADDRSIZE = 4)
(output reg wfull,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1],
wq2_rptr[ADDRSIZE-2:0]});
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) wfull <= 1'b0;
else wfull <= wfull_val;
endmodule
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/beh_fifo.v
0,0 → 1,38
// --------------------------------------------------------------------
//
 
 
module beh_fifo (rdata, wfull, rempty, wdata,
winc, wclk, wrst_n, rinc, rclk, rrst_n);
parameter DSIZE = 8;
parameter ASIZE = 4;
output [DSIZE-1:0] rdata;
output wfull;
output rempty;
input [DSIZE-1:0] wdata;
input winc, wclk, wrst_n;
input rinc, rclk, rrst_n;
reg [ASIZE:0] wptr, wrptr1, wrptr2, wrptr3;
reg [ASIZE:0] rptr, rwptr1, rwptr2, rwptr3;
parameter MEMDEPTH = 1<<ASIZE;
reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) wptr <= 0;
else if (winc && !wfull) begin
ex_mem[wptr[ASIZE-1:0]] <= wdata;
wptr <= wptr+1;
end
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wrptr3,wrptr2,wrptr1} <= 0;
else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr};
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rptr <= 0;
else if (rinc && !rempty) rptr <= rptr+1;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rwptr3,rwptr2,rwptr1} <= 0;
else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr};
assign rdata = ex_mem[rptr[ASIZE-1:0]];
assign rempty = (rptr == rwptr3);
assign wfull = ((wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) &&
(wptr[ASIZE] != wrptr3[ASIZE] ));
endmodule
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifomem.v
0,0 → 1,26
// --------------------------------------------------------------------
//
 
 
module fifomem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
`ifdef VENDORRAM
// instantiation of a vendor's dual-port RAM
vendor_ram mem (.dout(rdata), .din(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(wclken),
.wclken_n(wfull), .clk(wclk));
`else
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) mem[waddr] <= wdata;
`endif
endmodule
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifo1.v
0,0 → 1,36
// --------------------------------------------------------------------
//
 
 
module fifo1 #(parameter DSIZE = 8,
parameter ASIZE = 4)
(output [DSIZE-1:0] rdata,
output wfull,
output rempty,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
input rinc, rclk, rrst_n);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n));
sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n));
fifomem #(DSIZE, ASIZE) fifomem
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(ASIZE) rptr_empty
(.rempty(rempty),
.raddr(raddr),
.rptr(rptr), .rq2_wptr(rq2_wptr),
.rinc(rinc), .rclk(rclk),
.rrst_n(rrst_n));
wptr_full #(ASIZE) wptr_full
(.wfull(wfull), .waddr(waddr),
.wptr(wptr), .wq2_rptr(wq2_rptr),
.winc(winc), .wclk(wclk),
.wrst_n(wrst_n));
endmodule
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/rptr_empty.v
0,0 → 1,31
// --------------------------------------------------------------------
//
 
 
module rptr_empty #(parameter ADDRSIZE = 4)
(output reg rempty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
assign rempty_val = (rgraynext == rq2_wptr);
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_w2r.v
0,0 → 1,14
// --------------------------------------------------------------------
//
 
 
module sync_w2r #(parameter ADDRSIZE = 4)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
endmodule
 
/qaz_libs/trunk/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_r2w.v
0,0 → 1,14
// --------------------------------------------------------------------
//
 
 
module sync_r2w #(parameter ADDRSIZE = 4)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule
 
/qaz_libs/trunk/FIFOs/src/Beyond_Circuits/sync_fifo.v
0,0 → 1,162
// -*- mode: Verilog; verilog-auto-lineup-declaration: nil; -*-
//-----------------------------------------------------------------------------
// Title : Synchronous FIFO
// Project : Common
//-----------------------------------------------------------------------------
// File : sync_fifo.v
//-----------------------------------------------------------------------------
// Description : Synchronous FIFO using BRAM.
//
// Implements a variable width/depth synchronous FIFO. The synthesis
// tool may choose to implement the memory as a block RAM.
//-----------------------------------------------------------------------------
// Copyright 1994-2009 Beyond Circuits. All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
// SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//------------------------------------------------------------------------------
 
`timescale 1ns/1ns
module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
// Need the log of the parameters as parameters also due to an XST bug.
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
);
 
// log2 -- return the log base 2 of value.
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
 
// increment -- add one to value modulo depth.
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
 
// writing -- true when we write to the RAM.
wire writing = wr_enable && (rd_enable || !full);
 
// reading -- true when we are reading from the RAM.
wire reading = rd_enable && !empty;
 
// rd_ptr -- the read pointer.
reg [log2_depth-1:0] rd_ptr;
 
// next_rd_ptr -- the next value for the read pointer.
// We need to name this combinational value because it
// is needed to use the write-before-read style RAM.
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
 
always @(posedge clk)
rd_ptr <= next_rd_ptr;
 
// wr_ptr -- the write pointer
reg [log2_depth-1:0] wr_ptr;
 
// next_wr_ptr -- the next value for the write pointer.
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
 
always @(posedge clk)
wr_ptr <= next_wr_ptr;
// count -- the number of valid entries in the FIFO.
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
 
// empty -- true if the FIFO is empty.
// Note that this doesn't depend on count so if the count
// output is unused the logic for computing the count can
// be optimized away.
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
// full -- true if the FIFO is full.
// Again, this is not dependent on count.
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
// We need to infer a write first style RAM so that when
// the FIFO is empty the write data can flow through to
// the read side and be available the next clock cycle.
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
 
assign rd_data = mem[rd_ptr];
 
endmodule
 
/qaz_libs/trunk/FIFOs/src/tiny_sync_fifo.sv
0,0 → 1,102
// --------------------------------------------------------------------
//
 
 
module
tiny_sync_fifo
(
fifo_write_if.fifo source,
fifo_read_if.fifo sink
);
 
// --------------------------------------------------------------------
//
localparam W = source.W;
reg empty_r;
reg full_r;
wire writing = source.wr_en && (sink.rd_en || ~full_r);
wire reading = sink.rd_en && ~empty_r;
 
 
// --------------------------------------------------------------------
//
reg rd_ptr_r;
reg next_rd_ptr_r;
 
always_comb
if(source.reset)
next_rd_ptr_r = 0;
else if(reading)
next_rd_ptr_r = ~next_rd_ptr_r;
else
next_rd_ptr_r = rd_ptr_r;
 
always_ff @(posedge source.clk)
rd_ptr_r <= next_rd_ptr_r;
 
 
// --------------------------------------------------------------------
//
reg wr_ptr_r;
reg next_wr_ptr_r;
 
always_comb
if (source.reset)
next_wr_ptr_r = 0;
else if (writing)
next_wr_ptr_r = ~next_wr_ptr_r;
else
next_wr_ptr_r = wr_ptr_r;
 
always_ff @(posedge source.clk)
wr_ptr_r <= next_wr_ptr_r;
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge source.clk)
if (source.reset)
empty_r <= 1;
else if (reading && next_wr_ptr_r == next_rd_ptr_r && ~full_r)
empty_r <= 1;
else if (writing && ~reading)
empty_r <= 0;
else
empty_r <= empty_r;
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge source.clk)
if (source.reset)
full_r <= 0;
else if (writing && next_wr_ptr_r == next_rd_ptr_r)
full_r <= 1;
else if (reading && ~writing)
full_r <= 0;
 
 
// --------------------------------------------------------------------
//
reg [W - 1:0] data_0_r;
reg [W - 1:0] data_1_r;
wire [W - 1:0] wr_data_mux = rd_ptr_r ? data_1_r : data_0_r;
assign sink.rd_data = wr_data_mux;
 
always_ff @(posedge source.clk)
if (writing)
if(wr_ptr_r)
data_1_r <= source.wr_data;
else
data_0_r <= source.wr_data;
 
 
// --------------------------------------------------------------------
//
assign sink.empty = empty_r;
assign source.full = full_r;
 
 
endmodule
 
 
/qaz_libs/trunk/FIFOs/sim/tests/tiny_sync_fifo/wip.do
0,0 → 1,13
#
 
 
vlog -f ../../libs/FPGA_verilog/tiny_fifo.f
vlog -f ../../libs/sim_verilog/fifo_bfm.f
 
# simulation $root
vlog ../../src/tb_tiny_sync_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/FIFOs/sim/tests/tiny_sync_fifo/init_test.do
0,0 → 1,33
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all FPGA
sim_compile_all sim
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/qaz_libs/trunk/FIFOs/sim/tests/tiny_sync_fifo/the_test.sv
0,0 → 1,88
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
int data;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(1000ms);
 
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
 
repeat(10) @(posedge tb_clk);
 
repeat(100) tb_top.bfm.queue_random();
 
 
// tb_top.bfm.write(8'h22, 0);
// tb_top.bfm.write(8'haa, 0);
// tb_top.bfm.read(10);
// tb_top.bfm.write(8'hff, 5);
// tb_top.bfm.read(0);
// tb_top.bfm.read(0);
// tb_top.bfm.write(8'h11, 1);
 
 
repeat(1000) @(posedge tb_clk);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/FIFOs/sim/tests/tiny_sync_fifo/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/qaz_libs/trunk/FIFOs/sim/tests/CummingsSNUG2002SJ_FIFO1/wip.do
0,0 → 1,12
#
 
 
vlog -f ../../libs/FPGA_verilog/tb_CummingsSNUG2002SJ_FIFO1.f
 
# simulation $root
vlog ../../src/tb_CummingsSNUG2002SJ_FIFO1.sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/FIFOs/sim/tests/CummingsSNUG2002SJ_FIFO1/init_test.do
0,0 → 1,33
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all FPGA
sim_compile_all sim
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_CummingsSNUG2002SJ_FIFO1.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/qaz_libs/trunk/FIFOs/sim/tests/CummingsSNUG2002SJ_FIFO1/the_test.sv
0,0 → 1,75
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
int mismatch_count = 0;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(20us);
 
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
 
 
repeat(100) @(posedge tb_clk);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/FIFOs/sim/tests/CummingsSNUG2002SJ_FIFO1/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/qaz_libs/trunk/FIFOs/sim/src/fifo_bfm_pkg.sv
0,0 → 1,380
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package fifo_bfm_pkg;
 
typedef enum
{
SOURCE,
SINK,
BOTH
} fifo_type_t;
 
// --------------------------------------------------------------------
//
class fifo_transaction_class;
 
rand int data;
rand int write_delay = 0;
rand int read_delay = 0;
 
constraint default_write_delay
{
write_delay >= 0 && write_delay <= 4;
write_delay dist {0 := 60, [1:4] :=40 };
}
 
constraint default_read_delay
{
read_delay >= 0 && read_delay <= 4;
read_delay dist {0 := 60, [1:4] :=40 };
}
 
 
// --------------------------------------------------------------------
//
function void copy
(
ref fifo_transaction_class from
);
 
// $display("^^^ %16.t | %m", $time);
 
this.data = from.data;
this.write_delay = from.write_delay;
this.read_delay = from.read_delay;
 
endfunction: copy
 
 
// --------------------------------------------------------------------
//
extern virtual function fifo_transaction_class clone();
// virtual function fifo_transaction_class clone();
 
// $display("^^^ %16.t | %m", $time);
 
// clone = new();
// clone.copy(this);
// return(clone);
 
// endfunction: clone
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_transaction_class
 
 
// --------------------------------------------------------------------
//
function fifo_transaction_class fifo_transaction_class::clone();
 
// $display("^^^ %16.t | %m", $time);
 
clone = new();
clone.copy(this);
 
endfunction: clone
 
 
// --------------------------------------------------------------------
//
class fifo_bfm_class #(W = 8);
 
string fifo_name;
fifo_type_t fifo_type;
 
virtual fifo_write_if #(.W(W)) source = null;
virtual fifo_read_if #(.W(W)) sink = null;
fifo_transaction_class fifo_tr = new();
 
 
//--------------------------------------------------------------------
function new
(
virtual fifo_write_if #(.W(W)) source = null,
virtual fifo_read_if #(.W(W)) sink = null
);
 
if(source != null)
this.source = source;
 
if(sink != null)
this.sink = sink;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
init
(
input string fifo_name,
input fifo_type_t fifo_type
);
 
this.fifo_name = fifo_name;
this.fifo_type = fifo_type;
 
if(fifo_type == SOURCE)
source.cb_s.wr_en <= 0;
else if(fifo_type == SINK)
sink.cb_s.rd_en <= 0;
else if(fifo_type == BOTH)
if((this.source == null) | (this.sink == null))
begin
$display("^^^ %16.t | %m | ERROR! %s fifo_type == BOTH with null class", $time, fifo_type.name);
$stop;
end
else
begin
source.cb_s.wr_en <= 0;
sink.cb_s.rd_en <= 0;
end
else
begin
$display("^^^ %16.t | %m | ERROR! fifo_type %s is invalid", $time, fifo_type.name);
$stop;
end
 
$display("^^^ %16.t | %m | initialization of %s for %s", $time, fifo_name, fifo_type.name);
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
write
(
input [W-1:0] wr_data,
input int write_delay = 0
);
 
source.cb_s.wr_data <= wr_data;
source.cb_s.wr_en <= 0;
 
source.zero_cycle_delay();
 
if(write_delay != 0)
repeat(write_delay) @(source.cb_s);
 
@(source.cb_s iff (source.cb_s.full == 0));
// @(source.cb_s iff (~source.cb_s.full));
source.cb_s.wr_en <= 1;
 
@(posedge source.clk);
source.cb_s.wr_en <= 0;
 
endtask: write
 
 
// --------------------------------------------------------------------
//
task
fork_write
(
input [W-1:0] wr_data,
input int write_delay = 0
);
 
fork
write(wr_data, write_delay);
join_none
 
#0;
 
endtask: fork_write
 
 
// --------------------------------------------------------------------
//
mailbox #(int) rd_data_q = new();
 
task
read
(
input int read_delay = 0
);
 
sink.cb_s.rd_en <= 0;
 
sink.zero_cycle_delay();
 
if(read_delay != 0)
repeat(read_delay) @(sink.cb_s);
 
@(sink.cb_s iff (sink.cb_s.empty == 0));
// @(sink.cb_s iff (~sink.cb_s.empty));
sink.cb_s.rd_en <= 1;
 
@(posedge sink.clk);
 
sink.cb_s.rd_en <= 0;
 
rd_data_q.put(sink.cb_s.rd_data);
 
endtask: read
 
 
// --------------------------------------------------------------------
//
task automatic
fork_read
(
input int read_delay = 0
);
 
fork
read(read_delay);
join_none
 
#0;
 
endtask: fork_read
 
 
// --------------------------------------------------------------------
//
mailbox #(fifo_transaction_class) fifo_tr_q;
semaphore fifo_tr_q_semaphore = new(1);
 
 
// --------------------------------------------------------------------
//
event fifo_write_done;
 
task automatic
fifo_write_q;
 
if((fifo_type != SOURCE) & (fifo_type == BOTH))
begin
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time);
return;
end
 
if(fifo_tr_q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.fifo_tr_q = new();
 
fifo_write_fork : fork
forever
begin
 
fifo_tr_q.get(fifo_tr);
fork_write(fifo_tr.data, fifo_tr.write_delay);
 
wait fork;
 
->fifo_write_done;
end
join_none
 
#0;
 
endtask: fifo_write_q
 
 
// --------------------------------------------------------------------
//
fifo_transaction_class fifo_tr_clone;
event fifo_read_done;
logic [W - 1:0] rd_data;
logic [W - 1:0] rd_result;
int compare_result;
int compare_errors = 0;
 
task automatic
fifo_read_q;
 
if((fifo_type != SINK) & (fifo_type == BOTH))
begin
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time);
return;
end
 
 
if(fifo_tr_q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.fifo_tr_q = new();
fifo_tr_clone = fifo_tr.clone();
 
fifo_read_q_fork : fork
forever
begin
 
fifo_tr_q.get(fifo_tr);
fork_read(fifo_tr.read_delay);
 
wait fork;
 
->fifo_read_done;
 
rd_data_q.get(rd_result);
rd_data = fifo_tr.data;
 
if(rd_result != rd_data)
begin
$display("^^^ %16.t | %m | ERROR! rd_result != fifo_tr.data |", $time);
$display("^^^ %16.t | %m | rd_result = %h |", $time, rd_result);
$display("^^^ %16.t | %m | fifo_tr.data = %h |", $time, fifo_tr.data);
end
 
// compare_result = avf_in_frame.compare(8, f_h);
// compare_errors += compare_result;
 
end
join_none
 
#0;
 
endtask: fifo_read_q
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_bfm_class
 
endpackage: fifo_bfm_pkg
 
/qaz_libs/trunk/FIFOs/sim/src/tb_CummingsSNUG2002SJ_FIFO1.sv
0,0 → 1,116
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
wire clk_100mhz;
tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);
 
// --------------------------------------------------------------------
//
localparam DSIZE = 8;
localparam ASIZE = 4;
wire [DSIZE-1:0] rdata;
wire wfull;
wire rempty;
wire [DSIZE-1:0] wdata = 0;
wire winc = 0;
wire wclk = clk_100mhz;
wire wrst_n = ~tb_rst;
wire rinc = 0;
wire rclk = clk_200mhz;
wire rrst_n = ~tb_rst;
 
fifo1 #(.DSIZE(8), .ASIZE(4))
dut(.*);
// (
// output [DSIZE-1:0] rdata,
// output wfull,
// output rempty,
// input [DSIZE-1:0] wdata,
// input winc, wclk, wrst_n,
// input rinc, rclk, rrst_n
// );
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/FIFOs/sim/src/fifo_agent_pkg.sv
0,0 → 1,102
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package fifo_agent_pkg;
 
// --------------------------------------------------------------------
//
import fifo_bfm_pkg::*;
 
class fifo_agent_class #(W = 8);
 
fifo_bfm_class source_fifo;
fifo_bfm_class sink_fifo;
fifo_transaction_class tr_h;
fifo_transaction_class clone_h;
 
//--------------------------------------------------------------------
function
new
(
virtual fifo_write_if #(.W(W)) source,
virtual fifo_read_if #(.W(W)) sink
);
 
this.source_fifo = new(.source(source));
this.sink_fifo = new(.sink(sink));
this.tr_h = new();
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void init;
 
source_fifo.init("source", SOURCE);
sink_fifo.init("sink", SINK);
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task automatic
start_q;
 
source_fifo.fifo_write_q();
sink_fifo.fifo_read_q();
 
endtask: start_q
 
 
// --------------------------------------------------------------------
//
task automatic
queue_random;
 
if (!tr_h.randomize())
begin
$display("^^^ %16.t | %m | ERROR! randomize error", $time);
$stop;
end
 
clone_h = tr_h.clone();
source_fifo.fifo_tr_q.put(clone_h);
sink_fifo.fifo_tr_q.put(clone_h);
 
endtask: queue_random
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_agent_class
 
endpackage: fifo_agent_pkg
 
/qaz_libs/trunk/FIFOs/sim/src/tb_tiny_sync_fifo.sv
0,0 → 1,122
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
 
// wire clk_100mhz;
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);
 
 
// --------------------------------------------------------------------
//
localparam W = 8;
 
fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst);
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
tiny_sync_fifo
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
// import fifo_bfm_pkg::*;
 
// fifo_bfm_class bfm = new(source, sink);
 
// initial
// bfm.init("", BOTH);
 
 
// --------------------------------------------------------------------
//
import fifo_agent_pkg::*;
 
fifo_agent_class bfm = new(source, sink);
 
initial
begin
bfm.init();
bfm.start_q();
end
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/FIFOs/sim/libs/sim_verilog/tb_lib.f
0,0 → 1,16
#
 
-mfcu
 
${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk_class.sv
 
${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk.sv
${ROOT_DIR}/qaz_libs/tb_class/src/tb_base.sv
 
 
 
 
 
 
 
 
/qaz_libs/trunk/FIFOs/sim/libs/sim_verilog/fifo_bfm.f
0,0 → 1,6
#
 
 
${ROOT_DIR}/qaz_libs/FIFOs/sim/src/fifo_bfm_pkg.sv
${ROOT_DIR}/qaz_libs/FIFOs/sim/src/fifo_agent_pkg.sv
 
/qaz_libs/trunk/FIFOs/sim/libs/FPGA_verilog/CummingsSNUG2002SJ_FIFO1.f
0,0 → 1,26
#
 
 
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/beh_fifo.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifo1.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifomem.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/rptr_empty.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_r2w.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_w2r.v
${ROOT_DIR}/qaz_libs/FIFOs/src/CummingsSNUG2002SJ_FIFO1/wptr_full.v
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/qaz_libs/trunk/FIFOs/sim/libs/FPGA_verilog/tiny_fifo.f
0,0 → 1,8
#
 
 
${ROOT_DIR}/qaz_libs/FIFOs/src/tiny_sync_fifo.sv
${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_read_if.sv
${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_write_if.sv
 
 

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