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/qaz_libs/trunk/PCIe/sim/src/pcie_bfm_pkg.sv
0,0 → 1,331
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package pcie_bfm_pkg;
 
// --------------------------------------------------------------------
//
import pcie_common_pkg::*;
 
 
// --------------------------------------------------------------------
//
class altera_pcie_transaction;
tlp_header_class hd_h;
byte packet[];
 
 
//--------------------------------------------------------------------
//
function new(tlp_header_class hd_h, bit qword_aligned);
this.hd_h = hd_h;
if(qword_aligned & hd_h.fmt_type[5] == 0)
if(hd_h.length == 0)
this.packet = new[1024 + 1];
else
this.packet = new[hd_h.length + 1];
else
if(hd_h.length == 0)
this.packet = new[1024];
else
this.packet = new[hd_h.length];
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: altera_pcie_transaction
// // --------------------------------------------------------------------
// //
// class base_tlp_packet_class;
 
// tlp_type_t header_type = Reserved;
// tlp_routing_t routing_type = ROUTING_UNKNOWN;
// tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
// logic [7:0] fmt_type;
// logic [2:0] tc;
// logic th;
// logic [2:0] attr;
// logic td;
// logic ep;
// logic [9:0] length;
// logic [7:0] header [16];
// logic header_is_4_dw;
 
 
// // --------------------------------------------------------------------
// //
// function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
 
// casez(fmt_type)
// 8'b000_00000: get_tlp_type = MRd;
// 8'b001_00000: get_tlp_type = MRd;
// 8'b000_00001: get_tlp_type = MRdLk;
// 8'b001_00001: get_tlp_type = MRdLk;
// 8'b010_00000: get_tlp_type = MWr;
// 8'b011_00000: get_tlp_type = MWr;
// 8'b000_00010: get_tlp_type = IORd;
// 8'b010_00010: get_tlp_type = IOWr;
// 8'b000_00100: get_tlp_type = CfgRd0;
// 8'b010_00100: get_tlp_type = CfgWr0;
// 8'b000_00101: get_tlp_type = CfgRd1;
// 8'b010_00101: get_tlp_type = CfgWr1;
// 8'b000_11011: get_tlp_type = TCfgRd;
// 8'b010_11011: get_tlp_type = TCfgWr;
// 8'b001_10???: get_tlp_type = Msg;
// 8'b011_10???: get_tlp_type = MsgD;
// 8'b000_01010: get_tlp_type = Cpl;
// 8'b010_01010: get_tlp_type = CplD;
// 8'b000_01011: get_tlp_type = CplLk;
// 8'b010_01011: get_tlp_type = CplDLk;
// 8'b010_01100: get_tlp_type = FetchAdd;
// 8'b011_01100: get_tlp_type = FetchAdd;
// 8'b010_01101: get_tlp_type = Swap;
// 8'b011_01101: get_tlp_type = Swap;
// 8'b010_01110: get_tlp_type = CAS;
// 8'b011_01110: get_tlp_type = CAS;
// 8'b100_0????: get_tlp_type = LPrfx;
// 8'b100_1????: get_tlp_type = EPrfx;
// default: get_tlp_type = Reserved;
// endcase
 
// endfunction: get_tlp_type
 
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
// MWr: get_tlp_routing = ADDRESS;
// IORd: get_tlp_routing = ADDRESS;
// IOWr: get_tlp_routing = ADDRESS;
// CfgRd0: get_tlp_routing = ID;
// CfgWr0: get_tlp_routing = ID;
// CfgRd1: get_tlp_routing = ID;
// CfgWr1: get_tlp_routing = ID;
// TCfgRd: get_tlp_routing = ID;
// TCfgWr: get_tlp_routing = ID;
// Msg: get_tlp_routing = ROUTING_UNKNOWN;
// MsgD: get_tlp_routing = ROUTING_UNKNOWN;
// Cpl: get_tlp_routing = ID;
// CplD: get_tlp_routing = ID;
// CplLk: get_tlp_routing = ID;
// CplDLk: get_tlp_routing = ID;
// FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
// Swap: get_tlp_routing = ROUTING_UNKNOWN;
// CAS: get_tlp_routing = ROUTING_UNKNOWN;
// LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// default: get_tlp_routing = ROUTING_UNKNOWN;
// endcase
 
// endfunction: get_tlp_routing
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
// MWr: get_tlp_transaction = REQUESTER;
// IORd: get_tlp_transaction = REQUESTER;
// IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: get_tlp_transaction = REQUESTER;
// CfgWr0: get_tlp_transaction = REQUESTER;
// CfgRd1: get_tlp_transaction = REQUESTER;
// CfgWr1: get_tlp_transaction = REQUESTER;
// TCfgRd: get_tlp_transaction = REQUESTER;
// TCfgWr: get_tlp_transaction = REQUESTER;
// Msg: get_tlp_transaction = REQUESTER;
// MsgD: get_tlp_transaction = REQUESTER;
// Cpl: get_tlp_transaction = COMPLETER;
// CplD: get_tlp_transaction = COMPLETER;
// CplLk: get_tlp_transaction = COMPLETER;
// CplDLk: get_tlp_transaction = COMPLETER;
// FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: get_tlp_transaction = TRANSACTION_UNKNOWN;
// endcase
 
// endfunction: get_tlp_transaction
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_type_t tlp_type);
// logic [5:0] Register_Number = header[11][7:2];
// logic [3:0] Extended_Register_Number = header[10][3:0];
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
// endfunction: display_tlp_cfg
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
// // MWr: get_tlp_transaction = REQUESTER;
// // IORd: get_tlp_transaction = REQUESTER;
// // IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: display_tlp_cfg(tlp_type);
// CfgWr0: display_tlp_cfg(tlp_type);
// CfgRd1: display_tlp_cfg(tlp_type);
// CfgWr1: display_tlp_cfg(tlp_type);
// TCfgRd: display_tlp_cfg(tlp_type);
// TCfgWr: display_tlp_cfg(tlp_type);
// // Msg: get_tlp_transaction = REQUESTER;
// // MsgD: get_tlp_transaction = REQUESTER;
// // Cpl: get_tlp_transaction = COMPLETER;
// // CplD: get_tlp_transaction = COMPLETER;
// // CplLk: get_tlp_transaction = COMPLETER;
// // CplDLk: get_tlp_transaction = COMPLETER;
// // FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: return;
// endcase
 
// endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
// $stop;
// end
 
// header_is_4_dw = data[5];
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
// attr = {header[1][2], header[2][5:4]};
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
// endfunction: set_little_endian_header
 
 
// // --------------------------------------------------------------------
// //
// function void display_header(string str);
 
// $display("??? %16.t | .....................", $time);
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
// $display("??? %16.t | tag = %b", $time, header[10]);
// end
// else
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
// display_tlp_type(header_type);
// $display("??? %16.t | ---------------------", $time);
 
// endfunction: display_header
 
 
// // //--------------------------------------------------------------------
// // //
// // function new;
 
// // endfunction: new
 
 
// // --------------------------------------------------------------------
// //
// endclass: base_tlp_packet_class
 
 
// --------------------------------------------------------------------
//
endpackage: pcie_bfm_pkg
 
 
/qaz_libs/trunk/PCIe/sim/src/pcie_common_pkg.sv
0,0 → 1,303
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package pcie_common_pkg;
 
typedef enum
{
MRd, // Memory Read Request
MRdLk, // Memory Read Request-Locked
MWr, // Memory Write Request
IORd, // I/O Read Request
IOWr, // I/O Write Request
CfgRd0, // Configuration Read Type
CfgWr0, // Configuration Write Type
CfgRd1, // Configuration Read Type
CfgWr1, // Configuration Write Type
TCfgRd, // Deprecated TLP Type3
TCfgWr, // Deprecated TLP Type3
Msg, // Message Request
MsgD, // Message Request with data payload
Cpl, // Completion without Data
CplD, // Completion with Data
CplLk, // Completion for Locked Memory Read without Data
CplDLk, // Completion for Locked Memory Read
FetchAdd, // Fetch and Add AtomicOp Request
Swap, // Unconditional Swap AtomicOp Request
CAS, // Compare and Swap AtomicOp Request
LPrfx, // Local TLP Prefix
EPrfx, // End-End TLP Prefix
Reserved
} tlp_type_t;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
IMPLICIT
} tlp_routing_t;
 
typedef enum
{
TRANSACTION_UNKNOWN,
REQUESTER,
COMPLETER
} tlp_transaction_t;
 
 
// --------------------------------------------------------------------
//
class tlp_header_class;
 
tlp_type_t header_type;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
logic [2:0] attr;
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header[16];
logic header_is_4_dw;
 
 
// --------------------------------------------------------------------
//
// function logic [7:0] get_fmt_type(tlp_type_t header_type);
function logic [7:0] get_fmt_type;
casez(header_type)
MRd: get_fmt_type = 8'b000_00000;
MRd: get_fmt_type = 8'b001_00000;
MRdLk: get_fmt_type = 8'b000_00001;
MRdLk: get_fmt_type = 8'b001_00001;
MWr: get_fmt_type = 8'b010_00000;
MWr: get_fmt_type = 8'b011_00000;
IORd: get_fmt_type = 8'b000_00010;
IOWr: get_fmt_type = 8'b010_00010;
CfgRd0: get_fmt_type = 8'b000_00100;
CfgWr0: get_fmt_type = 8'b010_00100;
CfgRd1: get_fmt_type = 8'b000_00101;
CfgWr1: get_fmt_type = 8'b010_00101;
TCfgRd: get_fmt_type = 8'b000_11011;
TCfgWr: get_fmt_type = 8'b010_11011;
Msg: get_fmt_type = 8'b001_10xxx;
MsgD: get_fmt_type = 8'b011_10xxx;
Cpl: get_fmt_type = 8'b000_01010;
CplD: get_fmt_type = 8'b010_01010;
CplLk: get_fmt_type = 8'b000_01011;
CplDLk: get_fmt_type = 8'b010_01011;
FetchAdd: get_fmt_type = 8'b010_01100;
FetchAdd: get_fmt_type = 8'b011_01100;
Swap: get_fmt_type = 8'b010_01101;
Swap: get_fmt_type = 8'b011_01101;
CAS: get_fmt_type = 8'b010_01110;
CAS: get_fmt_type = 8'b011_01110;
LPrfx: get_fmt_type = 8'b100_0xxxx;
EPrfx: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
endcase
endfunction: get_fmt_type
 
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
8'b000_00001: get_tlp_type = MRdLk;
8'b001_00001: get_tlp_type = MRdLk;
8'b010_00000: get_tlp_type = MWr;
8'b011_00000: get_tlp_type = MWr;
8'b000_00010: get_tlp_type = IORd;
8'b010_00010: get_tlp_type = IOWr;
8'b000_00100: get_tlp_type = CfgRd0;
8'b010_00100: get_tlp_type = CfgWr0;
8'b000_00101: get_tlp_type = CfgRd1;
8'b010_00101: get_tlp_type = CfgWr1;
8'b000_11011: get_tlp_type = TCfgRd;
8'b010_11011: get_tlp_type = TCfgWr;
8'b001_10???: get_tlp_type = Msg;
8'b011_10???: get_tlp_type = MsgD;
8'b000_01010: get_tlp_type = Cpl;
8'b010_01010: get_tlp_type = CplD;
8'b000_01011: get_tlp_type = CplLk;
8'b010_01011: get_tlp_type = CplDLk;
8'b010_01100: get_tlp_type = FetchAdd;
8'b011_01100: get_tlp_type = FetchAdd;
8'b010_01101: get_tlp_type = Swap;
8'b011_01101: get_tlp_type = Swap;
8'b010_01110: get_tlp_type = CAS;
8'b011_01110: get_tlp_type = CAS;
8'b100_0????: get_tlp_type = LPrfx;
8'b100_1????: get_tlp_type = EPrfx;
default: get_tlp_type = Reserved;
endcase
endfunction: get_tlp_type
 
 
// --------------------------------------------------------------------
//
// function tlp_routing_t get_tlp_routing(tlp_type_t header_type);
function tlp_routing_t get_tlp_routing;
 
case(header_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
IORd: get_tlp_routing = ADDRESS;
IOWr: get_tlp_routing = ADDRESS;
CfgRd0: get_tlp_routing = ID;
CfgWr0: get_tlp_routing = ID;
CfgRd1: get_tlp_routing = ID;
CfgWr1: get_tlp_routing = ID;
TCfgRd: get_tlp_routing = ID;
TCfgWr: get_tlp_routing = ID;
Msg: get_tlp_routing = ROUTING_UNKNOWN;
MsgD: get_tlp_routing = ROUTING_UNKNOWN;
Cpl: get_tlp_routing = ID;
CplD: get_tlp_routing = ID;
CplLk: get_tlp_routing = ID;
CplDLk: get_tlp_routing = ID;
FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
Swap: get_tlp_routing = ROUTING_UNKNOWN;
CAS: get_tlp_routing = ROUTING_UNKNOWN;
LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
default: get_tlp_routing = ROUTING_UNKNOWN;
endcase
 
endfunction: get_tlp_routing
 
 
// --------------------------------------------------------------------
//
// function tlp_transaction_t get_tlp_transaction(tlp_type_t header_type);
function tlp_transaction_t get_tlp_transaction;
 
case(header_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
IORd: get_tlp_transaction = REQUESTER;
IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: get_tlp_transaction = REQUESTER;
CfgWr0: get_tlp_transaction = REQUESTER;
CfgRd1: get_tlp_transaction = REQUESTER;
CfgWr1: get_tlp_transaction = REQUESTER;
TCfgRd: get_tlp_transaction = REQUESTER;
TCfgWr: get_tlp_transaction = REQUESTER;
Msg: get_tlp_transaction = REQUESTER;
MsgD: get_tlp_transaction = REQUESTER;
Cpl: get_tlp_transaction = COMPLETER;
CplD: get_tlp_transaction = COMPLETER;
CplLk: get_tlp_transaction = COMPLETER;
CplDLk: get_tlp_transaction = COMPLETER;
FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: get_tlp_transaction = TRANSACTION_UNKNOWN;
endcase
 
endfunction: get_tlp_transaction
 
 
// --------------------------------------------------------------------
//
function void display_header(string str);
tlp_routing_t routing_type = get_tlp_routing;
tlp_transaction_t transaction_type = get_tlp_transaction;
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
$time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
else
$display("??? %16.t | address[31:0] = 0x%8.x", $time,
{ header[8], header[9], header[10], header[11][7:2], 2'b00});
else if(routing_type == ID)
$display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
header[8], header[9][7:3], header[9][2:0]);
 
if(transaction_type == COMPLETER)
begin
$display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
$display("??? %16.t | tag = %b", $time, header[10]);
end
else
begin
$display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | tag = %b", $time, header[6]);
$display("??? %16.t | last DW BE = %b | first DW BE = %b",
$time, header[7][7:4], header[7][3:0]);
end
 
// display_tlp_type(header_type);
 
$display("??? %16.t | ---------------------", $time);
 
endfunction: display_header
 
 
//--------------------------------------------------------------------
//
function new(tlp_type_t header_type, logic [9:0] length);
this.header_type = header_type;
this.fmt_type = get_fmt_type;
this.length = length;
this.header_is_4_dw = fmt_type[5];
this.header[0] = fmt_type;
this.header[3] = length[7:0];
this.header[2][1:0] = length[9:8];
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tlp_header_class
 
 
// --------------------------------------------------------------------
//
endpackage: pcie_common_pkg
 
 
/qaz_libs/trunk/PCIe/sim/src/pcie_monitor_pkg.sv
30,203 → 30,117
//
package pcie_monitor_pkg;
 
typedef enum
{
MRd, // Memory Read Request
MRdLk, // Memory Read Request-Locked
MWr, // Memory Write Request
IORd, // I/O Read Request
IOWr, // I/O Write Request
CfgRd0, // Configuration Read Type
CfgWr0, // Configuration Write Type
CfgRd1, // Configuration Read Type
CfgWr1, // Configuration Write Type
TCfgRd, // Deprecated TLP Type3
TCfgWr, // Deprecated TLP Type3
Msg, // Message Request
MsgD, // Message Request with data payload
Cpl, // Completion without Data
CplD, // Completion with Data
CplLk, // Completion for Locked Memory Read without Data
CplDLk, // Completion for Locked Memory Read
FetchAdd, // Fetch and Add AtomicOp Request
Swap, // Unconditional Swap AtomicOp Request
CAS, // Compare and Swap AtomicOp Request
LPrfx, // Local TLP Prefix
EPrfx, // End-End TLP Prefix
Reserved
} tlp_type_t;
// --------------------------------------------------------------------
//
import pcie_common_pkg::*;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
IMPLICIT
} tlp_routing_t;
 
typedef enum
{
TRANSACTION_UNKNOWN,
REQUESTER,
COMPLETER
} tlp_transaction_t;
 
 
// --------------------------------------------------------------------
//
class base_tlp_packet_class;
class tlp_monitor_class;
 
tlp_type_t header_type = Reserved;
tlp_routing_t routing_type = ROUTING_UNKNOWN;
tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
logic [2:0] attr;
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header [16];
logic header_is_4_dw;
// tlp_type_t header_type = Reserved;
// tlp_routing_t routing_type = ROUTING_UNKNOWN;
// tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
// logic [7:0] fmt_type;
// logic [2:0] tc;
// logic th;
// logic [2:0] attr;
// logic td;
// logic ep;
// logic [9:0] length;
// logic [7:0] header [16];
// logic header_is_4_dw;
 
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
// // --------------------------------------------------------------------
// //
// function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
 
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
8'b000_00001: get_tlp_type = MRdLk;
8'b001_00001: get_tlp_type = MRdLk;
8'b010_00000: get_tlp_type = MWr;
8'b011_00000: get_tlp_type = MWr;
8'b000_00010: get_tlp_type = IORd;
8'b010_00010: get_tlp_type = IOWr;
8'b000_00100: get_tlp_type = CfgRd0;
8'b010_00100: get_tlp_type = CfgWr0;
8'b000_00101: get_tlp_type = CfgRd1;
8'b010_00101: get_tlp_type = CfgWr1;
8'b000_11011: get_tlp_type = TCfgRd;
8'b010_11011: get_tlp_type = TCfgWr;
8'b001_10???: get_tlp_type = Msg;
8'b011_10???: get_tlp_type = MsgD;
8'b000_01010: get_tlp_type = Cpl;
8'b010_01010: get_tlp_type = CplD;
8'b000_01011: get_tlp_type = CplLk;
8'b010_01011: get_tlp_type = CplDLk;
8'b010_01100: get_tlp_type = FetchAdd;
8'b011_01100: get_tlp_type = FetchAdd;
8'b010_01101: get_tlp_type = Swap;
8'b011_01101: get_tlp_type = Swap;
8'b010_01110: get_tlp_type = CAS;
8'b011_01110: get_tlp_type = CAS;
8'b100_0????: get_tlp_type = LPrfx;
8'b100_1????: get_tlp_type = EPrfx;
default: get_tlp_type = Reserved;
endcase
// casez(fmt_type)
// 8'b000_00000: get_tlp_type = MRd;
// 8'b001_00000: get_tlp_type = MRd;
// 8'b000_00001: get_tlp_type = MRdLk;
// 8'b001_00001: get_tlp_type = MRdLk;
// 8'b010_00000: get_tlp_type = MWr;
// 8'b011_00000: get_tlp_type = MWr;
// 8'b000_00010: get_tlp_type = IORd;
// 8'b010_00010: get_tlp_type = IOWr;
// 8'b000_00100: get_tlp_type = CfgRd0;
// 8'b010_00100: get_tlp_type = CfgWr0;
// 8'b000_00101: get_tlp_type = CfgRd1;
// 8'b010_00101: get_tlp_type = CfgWr1;
// 8'b000_11011: get_tlp_type = TCfgRd;
// 8'b010_11011: get_tlp_type = TCfgWr;
// 8'b001_10???: get_tlp_type = Msg;
// 8'b011_10???: get_tlp_type = MsgD;
// 8'b000_01010: get_tlp_type = Cpl;
// 8'b010_01010: get_tlp_type = CplD;
// 8'b000_01011: get_tlp_type = CplLk;
// 8'b010_01011: get_tlp_type = CplDLk;
// 8'b010_01100: get_tlp_type = FetchAdd;
// 8'b011_01100: get_tlp_type = FetchAdd;
// 8'b010_01101: get_tlp_type = Swap;
// 8'b011_01101: get_tlp_type = Swap;
// 8'b010_01110: get_tlp_type = CAS;
// 8'b011_01110: get_tlp_type = CAS;
// 8'b100_0????: get_tlp_type = LPrfx;
// 8'b100_1????: get_tlp_type = EPrfx;
// default: get_tlp_type = Reserved;
// endcase
 
endfunction: get_tlp_type
// endfunction: get_tlp_type
 
// --------------------------------------------------------------------
//
function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
case(tlp_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
IORd: get_tlp_routing = ADDRESS;
IOWr: get_tlp_routing = ADDRESS;
CfgRd0: get_tlp_routing = ID;
CfgWr0: get_tlp_routing = ID;
CfgRd1: get_tlp_routing = ID;
CfgWr1: get_tlp_routing = ID;
TCfgRd: get_tlp_routing = ID;
TCfgWr: get_tlp_routing = ID;
Msg: get_tlp_routing = ROUTING_UNKNOWN;
MsgD: get_tlp_routing = ROUTING_UNKNOWN;
Cpl: get_tlp_routing = ID;
CplD: get_tlp_routing = ID;
CplLk: get_tlp_routing = ID;
CplDLk: get_tlp_routing = ID;
FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
Swap: get_tlp_routing = ROUTING_UNKNOWN;
CAS: get_tlp_routing = ROUTING_UNKNOWN;
LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
default: get_tlp_routing = ROUTING_UNKNOWN;
endcase
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
// MWr: get_tlp_routing = ADDRESS;
// IORd: get_tlp_routing = ADDRESS;
// IOWr: get_tlp_routing = ADDRESS;
// CfgRd0: get_tlp_routing = ID;
// CfgWr0: get_tlp_routing = ID;
// CfgRd1: get_tlp_routing = ID;
// CfgWr1: get_tlp_routing = ID;
// TCfgRd: get_tlp_routing = ID;
// TCfgWr: get_tlp_routing = ID;
// Msg: get_tlp_routing = ROUTING_UNKNOWN;
// MsgD: get_tlp_routing = ROUTING_UNKNOWN;
// Cpl: get_tlp_routing = ID;
// CplD: get_tlp_routing = ID;
// CplLk: get_tlp_routing = ID;
// CplDLk: get_tlp_routing = ID;
// FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
// Swap: get_tlp_routing = ROUTING_UNKNOWN;
// CAS: get_tlp_routing = ROUTING_UNKNOWN;
// LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// default: get_tlp_routing = ROUTING_UNKNOWN;
// endcase
 
endfunction: get_tlp_routing
// endfunction: get_tlp_routing
// --------------------------------------------------------------------
//
function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
case(tlp_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
IORd: get_tlp_transaction = REQUESTER;
IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: get_tlp_transaction = REQUESTER;
CfgWr0: get_tlp_transaction = REQUESTER;
CfgRd1: get_tlp_transaction = REQUESTER;
CfgWr1: get_tlp_transaction = REQUESTER;
TCfgRd: get_tlp_transaction = REQUESTER;
TCfgWr: get_tlp_transaction = REQUESTER;
Msg: get_tlp_transaction = REQUESTER;
MsgD: get_tlp_transaction = REQUESTER;
Cpl: get_tlp_transaction = COMPLETER;
CplD: get_tlp_transaction = COMPLETER;
CplLk: get_tlp_transaction = COMPLETER;
CplDLk: get_tlp_transaction = COMPLETER;
FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: get_tlp_transaction = TRANSACTION_UNKNOWN;
endcase
 
endfunction: get_tlp_transaction
// --------------------------------------------------------------------
//
function void display_tlp_cfg(tlp_type_t tlp_type);
logic [5:0] Register_Number = header[11][7:2];
logic [3:0] Extended_Register_Number = header[10][3:0];
// $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
$display("??? %16.t | config offset = 0x%5.x",
$time, {Extended_Register_Number, Register_Number, 2'b00});
endfunction: display_tlp_cfg
// --------------------------------------------------------------------
//
function void display_tlp_type(tlp_type_t tlp_type);
case(tlp_type)
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
// MWr: get_tlp_transaction = REQUESTER;
// IORd: get_tlp_transaction = REQUESTER;
// IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: display_tlp_cfg(tlp_type);
CfgWr0: display_tlp_cfg(tlp_type);
CfgRd1: display_tlp_cfg(tlp_type);
CfgWr1: display_tlp_cfg(tlp_type);
TCfgRd: display_tlp_cfg(tlp_type);
TCfgWr: display_tlp_cfg(tlp_type);
// CfgRd0: get_tlp_transaction = REQUESTER;
// CfgWr0: get_tlp_transaction = REQUESTER;
// CfgRd1: get_tlp_transaction = REQUESTER;
// CfgWr1: get_tlp_transaction = REQUESTER;
// TCfgRd: get_tlp_transaction = REQUESTER;
// TCfgWr: get_tlp_transaction = REQUESTER;
// Msg: get_tlp_transaction = REQUESTER;
// MsgD: get_tlp_transaction = REQUESTER;
// Cpl: get_tlp_transaction = COMPLETER;
238,86 → 152,134
// CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: return;
endcase
// default: get_tlp_transaction = TRANSACTION_UNKNOWN;
// endcase
 
endfunction: display_tlp_type
// endfunction: get_tlp_transaction
// --------------------------------------------------------------------
//
function void set_little_endian_header( logic [127:0] data);
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_header_class hd_h);
// logic [5:0] Register_Number = hd_h.header[11][7:2];
// logic [3:0] Extended_Register_Number = hd_h.header[10][3:0];
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
// endfunction: display_tlp_cfg
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
// // MWr: get_tlp_transaction = REQUESTER;
// // IORd: get_tlp_transaction = REQUESTER;
// // IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: display_tlp_cfg(tlp_type);
// CfgWr0: display_tlp_cfg(tlp_type);
// CfgRd1: display_tlp_cfg(tlp_type);
// CfgWr1: display_tlp_cfg(tlp_type);
// TCfgRd: display_tlp_cfg(tlp_type);
// TCfgWr: display_tlp_cfg(tlp_type);
// // Msg: get_tlp_transaction = REQUESTER;
// // MsgD: get_tlp_transaction = REQUESTER;
// // Cpl: get_tlp_transaction = COMPLETER;
// // CplD: get_tlp_transaction = COMPLETER;
// // CplLk: get_tlp_transaction = COMPLETER;
// // CplDLk: get_tlp_transaction = COMPLETER;
// // FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: return;
// endcase
 
logic [2:0] fmt = data[7:5];
// endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
if(fmt > 3'b011)
begin
$display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
$stop;
end
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
// $stop;
// end
 
header_is_4_dw = data[5];
// header_is_4_dw = data[5];
for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
{header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
header_type = get_tlp_type(header[0]);
routing_type = get_tlp_routing(header_type);
transaction_type = get_tlp_transaction(header_type);
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
fmt_type = header[0];
tc = header[1][6:4];
th = header[1][0];
attr = {header[1][2], header[2][5:4]};
td = header[2][7];
ep = header[2][6];
length = {header[2][1:0], header[3]};
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
// attr = {header[1][2], header[2][5:4]};
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
endfunction: set_little_endian_header
// endfunction: set_little_endian_header
 
 
// --------------------------------------------------------------------
//
function void display_header(string str);
// // --------------------------------------------------------------------
// //
// function void display_header(string str);
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
$time, tc, th, attr, td, ep);
// $display("??? %16.t | .....................", $time);
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
else
$display("??? %16.t | address[31:0] = 0x%8.x", $time,
{ header[8], header[9], header[10], header[11][7:2], 2'b00});
else if(routing_type == ID)
$display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
header[8], header[9][7:3], header[9][2:0]);
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
if(transaction_type == COMPLETER)
begin
$display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
$display("??? %16.t | tag = %b", $time, header[10]);
end
else
begin
$display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | tag = %b", $time, header[6]);
$display("??? %16.t | last DW BE = %b | first DW BE = %b",
$time, header[7][7:4], header[7][3:0]);
end
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
// $display("??? %16.t | tag = %b", $time, header[10]);
// end
// else
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
display_tlp_type(header_type);
// display_tlp_type(header_type);
$display("??? %16.t | ---------------------", $time);
// $display("??? %16.t | ---------------------", $time);
 
endfunction: display_header
// endfunction: display_header
 
 
// //--------------------------------------------------------------------
329,7 → 291,7
 
// --------------------------------------------------------------------
//
endclass: base_tlp_packet_class
endclass: tlp_monitor_class
 
 
// --------------------------------------------------------------------
/qaz_libs/trunk/PCIe/sim/src/riffa_agent_class_pkg.sv
0,0 → 1,107
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package riffa_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
class riffa_agent_class #(N);
 
riffa_transaction_class #(N) tr_h;
rp_tx_bfm_class #(N) tx_h;
rp_rx_bfm_class #(N) rx_h;
mailbox #(riffa_transaction_class #(N)) q;
 
 
// --------------------------------------------------------------------
//
task queue_tx(riffa_transaction_class #(N) tr_h);
tx_h.put(tr_h);
q.put(tr_h);
endtask: queue_tx
 
 
// --------------------------------------------------------------------
//
task queue_tx_random(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.random(len, off, last);
tx_h.put(tr_h);
q.put(tr_h);
endtask: queue_tx_random
 
 
// --------------------------------------------------------------------
//
task queue_rx(int len, int off, bit last);
tr_h = new(len, off, last);
rx_h.put(tr_h);
endtask: queue_rx
 
 
// --------------------------------------------------------------------
//
task wait_for_tx;
@(tx_h.tx_done);
endtask: wait_for_tx
 
 
// --------------------------------------------------------------------
//
task wait_for_rx;
@(rx_h.rx_done);
endtask: wait_for_rx
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
tx_h = new(chnl_bus);
rx_h = new(chnl_bus);
this.q = new;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: riffa_agent_class
 
 
// --------------------------------------------------------------------
//
endpackage: riffa_agent_class_pkg
 
 
 
 
 
/qaz_libs/trunk/PCIe/sim/src/riffa_bfm_class_pkg.sv
0,0 → 1,239
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package riffa_bfm_class_pkg;
 
// --------------------------------------------------------------------
//
import q_pkg::*;
 
 
// --------------------------------------------------------------------
//
class riffa_transaction_class #(N);
 
rand logic [31:0] len;
rand logic [30:0] off;
rand logic last;
rand logic [(8*N)-1:0] data[];
 
 
//--------------------------------------------------------------------
//
function int get_data_size(int len);
// int words = $ceil(len/(N/4)); // need to fix
int words = len/(N/4);
// $display("^^^ %16.t | words = %d", $time, words);
return(words);
endfunction: get_data_size
 
 
//--------------------------------------------------------------------
//
function void random(int len, int off, bit last);
this.data = new[get_data_size(len)];
assert(this.randomize() with
{
this.len == len; // why not working?
this.off == off;
this.last == last;
});
this.len = len;
this.off = off;
this.last = last;
endfunction: random
 
 
// // --------------------------------------------------------------------
// //
// function void copy(ref riffa_transaction_class #(N) from);
// this.len = from.len;
// this.off = from.off;
// this.last = from.last;
// endfunction: copy
 
 
// // --------------------------------------------------------------------
// //
// function riffa_transaction_class #(N) clone();
// clone = new(0, 0, 0);
// clone.copy(this);
// endfunction: clone
 
 
//--------------------------------------------------------------------
function new(int len, int off, bit last);
this.data = new[get_data_size(len)];
this.len = len;
this.off = off;
this.last = last;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: riffa_transaction_class
 
 
// --------------------------------------------------------------------
// root port tx
class rp_tx_bfm_class #(N)
extends blocking_transmission_q_class #(riffa_transaction_class #(N));
 
virtual riffa_chnl_if #(.N(N)) chnl_bus;
 
// --------------------------------------------------------------------
//
task set_default;
 
chnl_bus.cb_rp_tx.rx <= 0;
chnl_bus.cb_rp_tx.rx_last <= 'bx;
chnl_bus.cb_rp_tx.rx_len <= 'bx;
chnl_bus.cb_rp_tx.rx_off <= 'bx;
chnl_bus.cb_rp_tx.rx_data <= 'bx;
chnl_bus.cb_rp_tx.rx_data_valid <= 0;
 
endtask: set_default
 
 
// --------------------------------------------------------------------
//
event tx_done;
 
task transmit(ref Q_T tr_h);
 
@(chnl_bus.cb_rp_tx);
chnl_bus.cb_rp_tx.rx_len <= tr_h.len; // must be => 4
chnl_bus.cb_rp_tx.rx_off <= tr_h.off;
chnl_bus.cb_rp_tx.rx_last <= tr_h.last;
chnl_bus.cb_rp_tx.rx <= 1;
 
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_tx.rx_ack);
chnl_bus.cb_rp_tx.rx_data_valid <= 1;
 
foreach(tr_h.data[i])
begin
chnl_bus.cb_rp_tx.rx_data <= tr_h.data[i];
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_tx.rx_data_ren);
end
 
set_default();
->tx_done;
endtask: transmit
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
this.chnl_bus = chnl_bus;
fork
set_default();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: rp_tx_bfm_class
 
 
// --------------------------------------------------------------------
// root port rx
class rp_rx_bfm_class #(N)
extends blocking_transmission_q_class #(riffa_transaction_class #(N));
 
virtual riffa_chnl_if #(.N(N)) chnl_bus;
mailbox #(riffa_transaction_class #(N)) rx_q;
 
 
// --------------------------------------------------------------------
//
task set_default;
 
chnl_bus.cb_rp_rx.tx_ack <= 0;
chnl_bus.cb_rp_rx.tx_data_ren <= 0;
 
endtask: set_default
 
 
// --------------------------------------------------------------------
//
event rx_done;
 
task automatic transmit(ref Q_T tr_h);
int last;
int len;
int off;
 
@(chnl_bus.cb_rp_rx iff chnl_bus.cb_rp_rx.tx);
 
last = chnl_bus.cb_rp_rx.tx_last;
len = chnl_bus.cb_rp_rx.tx_len; // must be => 4
off = chnl_bus.cb_rp_rx.tx_off;
tr_h = new(len, off, last);
 
chnl_bus.cb_rp_rx.tx_ack <= 1;
chnl_bus.cb_rp_rx.tx_data_ren <= 1;
fork
@(chnl_bus.cb_rp_tx)
chnl_bus.cb_rp_rx.tx_ack <= 0;
join_none
foreach(tr_h.data[i])
@(chnl_bus.cb_rp_tx)
if(~chnl_bus.cb_rp_rx.tx)
break;
else if(chnl_bus.cb_rp_rx.tx_data_valid)
tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
 
rx_q.put(tr_h);
set_default();
->rx_done;
endtask: transmit
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
this.chnl_bus = chnl_bus;
this.rx_q = new();
fork
set_default();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: rp_rx_bfm_class
 
// --------------------------------------------------------------------
//
endpackage: riffa_bfm_class_pkg
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_chnl_convolution
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/src/RIFFA_example_readme.txt
0,0 → 1,6
 
Download example from link below.
 
https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/v6_pcie_convolution.zip?attredirects=0&d=1
 
files are from ./v6_pcie_convolution/hdl/verilog
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/tb_chnl_convolution.f
0,0 → 1,18
#
 
+incdir+./src
 
./src/accumulate_bytes.v
./src/chnl_convolution.v
./src/distribute_bytes.v
./src/ram_1clk_1w_1r.v
./src/sliding_window.v
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl/chnl_tester.v
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/tb_chnl_convolution.sv
0,0 → 1,166
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_chnl_convolution_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus();
 
 
// --------------------------------------------------------------------
//
wire CLK = tb_clk;
wire RST = tb_rst_s;
assign chnl_bus.rx_clk = CLK;
assign chnl_bus.tx_clk = CLK;
 
chnl_convolution #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
dut
(
.CHNL_RX_CLK(chnl_bus.rx_clk),
.CHNL_RX(chnl_bus.rx),
.CHNL_RX_ACK(chnl_bus.rx_ack),
.CHNL_RX_LAST(chnl_bus.rx_last),
.CHNL_RX_LEN(chnl_bus.rx_len),
.CHNL_RX_OFF(chnl_bus.rx_off),
.CHNL_RX_DATA(chnl_bus.rx_data),
.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
.CHNL_TX_CLK(chnl_bus.tx_clk),
.CHNL_TX(chnl_bus.tx),
.CHNL_TX_ACK(chnl_bus.tx_ack),
.CHNL_TX_LAST(chnl_bus.tx_last),
.CHNL_TX_LEN(chnl_bus.tx_len),
.CHNL_TX_OFF(chnl_bus.tx_off),
.CHNL_TX_DATA(chnl_bus.tx_data),
.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren),
.*
);
 
 
// --------------------------------------------------------------------
//
tb_chnl_convolution_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/tb_chnl_convolution_pkg.sv
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_chnl_convolution_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam C_PCI_DATA_WIDTH = 64;
localparam N = C_PCI_DATA_WIDTH / 8;
 
// --------------------------------------------------------------------
//
class tb_chnl_convolution_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_chnl_convolution_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_chnl_convolution_pkg
 
 
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/the_test.sv
0,0 → 1,105
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_chnl_convolution_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
// --------------------------------------------------------------------
//
task automatic send_frame;
riffa_transaction_class #(N) tr_h;
int width = 32;
int height = 16;
int len = (width * height) / 4;
tr_h = new(len, 0, 1);
tr_h.random(len, 0, 1);
tr_h.data[0] = 0;
tr_h.data[0][10:0] = width; // rFrameWidth
tr_h.data[0][42:32] = height; // rFrameHeight
$display("^^^ %16.t | %m | %d", $time, tr_h.data.size());
tb_top.a_h.queue_tx(tr_h);
endtask
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(500us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
send_frame();
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#1us;
send_frame();
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#1us;
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_convolution/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_chnl_tester
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/tb_chnl_tester.f
0,0 → 1,13
#
 
+incdir+${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl/chnl_tester.v
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/tb_chnl_tester.sv
0,0 → 1,139
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_chnl_tester_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus();
 
 
// --------------------------------------------------------------------
//
wire CLK = tb_clk;
wire RST = tb_rst_s;
assign chnl_bus.rx_clk = CLK;
assign chnl_bus.tx_clk = CLK;
 
chnl_tester #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
dut
(
.CHNL_RX_CLK(chnl_bus.rx_clk),
.CHNL_RX(chnl_bus.rx),
.CHNL_RX_ACK(chnl_bus.rx_ack),
.CHNL_RX_LAST(chnl_bus.rx_last),
.CHNL_RX_LEN(chnl_bus.rx_len),
.CHNL_RX_OFF(chnl_bus.rx_off),
.CHNL_RX_DATA(chnl_bus.rx_data),
.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
.CHNL_TX_CLK(chnl_bus.tx_clk),
.CHNL_TX(chnl_bus.tx),
.CHNL_TX_ACK(chnl_bus.tx_ack),
.CHNL_TX_LAST(chnl_bus.tx_last),
.CHNL_TX_LEN(chnl_bus.tx_len),
.CHNL_TX_OFF(chnl_bus.tx_off),
.CHNL_TX_DATA(chnl_bus.tx_data),
.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren),
.*
);
 
 
// --------------------------------------------------------------------
//
tb_chnl_tester_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/tb_chnl_tester_pkg.sv
0,0 → 1,83
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_chnl_tester_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
// localparam C_NUM_CHNL = 1;
// localparam C_NUM_LANES = 8;
localparam C_PCI_DATA_WIDTH = 128;
// localparam C_MAX_PAYLOAD_BYTES = 256;
// localparam C_LOG_NUM_TAGS = 5;
// localparam SIG_CFG_STS_W = 53;
// localparam SIG_CFG_CTL_W = 32;
// localparam SIG_CFG_ADD_W = 4;
// localparam SIG_KO_CPLD_W = 12;
// localparam SIG_KO_CPLH_W = 8;
// localparam SIG_CHNL_OFFSET_W = 31;
// localparam SIG_CHNL_LENGTH_W = 32;
 
localparam N = C_PCI_DATA_WIDTH / 8;
 
// --------------------------------------------------------------------
//
class tb_chnl_tester_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new
(
virtual riffa_chnl_if #(.N(N)) chnl_bus
);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_chnl_tester_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_chnl_tester_pkg
 
 
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/the_test.sv
0,0 → 1,76
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(50us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(24, 0, 1);
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(24, 0, 1);
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/PCIe/sim/tests/tb_chnl_tester/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.f
0,0 → 1,14
#
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.sv
0,0 → 1,146
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_register_if #(.N(N), .MW(MW)) r_if(.*);
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.A(A), .N(N), .MW(MW))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < MI; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
// --------------------------------------------------------------------
//
tb_riffa_register_file_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
 
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_in.rx_data_valid & chnl_in.rx_data_ren;
 
always_ff @(posedge chnl_in.rx_clk)
if(chnl_in.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_in.tx_data_valid & chnl_in.tx_data_ren;
 
always_ff @(posedge chnl_in.tx_clk)
if(chnl_in.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_register_file_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 16; // width of the bus in bytes
localparam MW = 3; // mux select width
localparam MI = 2 ** MW; // mux inputs
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
class tb_riffa_register_file_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_register_file_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_register_file_pkg
 
 
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(5us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*MI, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*MI, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_downsizer.sv
0,0 → 1,99
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_downsizer
#(
N, // PCIe IP data in width in bytes
S // data out size divisor
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_out
);
 
// --------------------------------------------------------------------
//
riffa_chnl_xx_downsizer #(.N(N), .S(S))
riffa_chnl_xx_downsizer_i
(
.xx_in(chnl_in.rx),
.ack_in(chnl_in.rx_ack),
.last_in(chnl_in.rx_last),
.len_in(chnl_in.rx_len),
.off_in(chnl_in.rx_off),
.data_in(chnl_in.rx_data),
.data_valid_in(chnl_in.rx_data_valid),
.data_ren_in(chnl_in.rx_data_ren),
 
.last_out(chnl_out.rx_last),
.len_out(chnl_out.rx_len),
.off_out(chnl_out.rx_off),
.data_out(chnl_out.rx_data),
.data_valid_out(chnl_out.rx_data_valid),
.data_ren_out(chnl_out.rx_data_ren),
.reset(chnl_in.rx_reset),
.clk(chnl_in.rx_clk)
);
// --------------------------------------------------------------------
//
riffa_chnl_xx_upsizer #(.N(N/S), .S(S))
riffa_chnl_xx_upsizer_i
(
.xx_in(chnl_in.tx),
.ack_in(chnl_in.tx_ack),
.last_in(chnl_out.tx_last),
.len_in(chnl_out.tx_len),
.off_in(chnl_out.tx_off),
.data_in(chnl_out.tx_data),
.data_valid_in(chnl_out.tx_data_valid),
.data_ren_in(chnl_out.tx_data_ren),
 
.last_out(chnl_in.tx_last),
.len_out(chnl_in.tx_len),
.off_out(chnl_in.tx_off),
.data_out(chnl_in.tx_data),
.data_valid_out(chnl_in.tx_data_valid),
.data_ren_out(chnl_in.tx_data_ren),
.reset(chnl_in.tx_reset),
.clk(chnl_in.tx_clk)
);
 
 
// --------------------------------------------------------------------
//
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_if.sv
0,0 → 1,112
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
riffa_chnl_if #(N); // data bus width in bytes
 
wire rx_clk;
wire rx_reset;
wire rx;
wire rx_ack;
wire rx_last;
wire [31:0] rx_len;
wire [30:0] rx_off;
wire [(8*N)-1:0] rx_data;
wire rx_data_valid;
wire rx_data_ren;
 
wire tx_clk;
wire tx_reset;
wire tx;
wire tx_ack;
wire tx_last;
wire [31:0] tx_len;
wire [30:0] tx_off;
wire [(8*N)-1:0] tx_data;
wire tx_data_valid;
wire tx_data_ren;
 
 
// --------------------------------------------------------------------
// synthesis translate_off
 
// from the RIFFA channel
clocking cb_ep_rx @(posedge rx_clk);
input rx;
output rx_ack;
input rx_last;
input rx_len;
input rx_off;
input rx_data;
input rx_data_valid;
output rx_data_ren;
endclocking
 
// from the RIFFA channel
clocking cb_ep_tx @(posedge tx_clk);
output tx;
input tx_ack;
output tx_last;
output tx_len;
output tx_off;
output tx_data;
output tx_data_valid;
input tx_data_ren;
endclocking
 
// from the PCIe
clocking cb_rp_tx @(posedge rx_clk);
output rx;
input rx_ack;
output rx_last;
output rx_len;
output rx_off;
output rx_data;
output rx_data_valid;
input rx_data_ren;
endclocking
 
// from the PCIe
clocking cb_rp_rx @(posedge tx_clk);
input tx;
output tx_ack;
input tx_last;
input tx_len;
input tx_off;
input tx_data;
input tx_data_valid;
output tx_data_ren;
endclocking
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
endinterface: riffa_chnl_if
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_rx.sv
0,0 → 1,104
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chn_rx
#(
N // data bus width in bytes
)
(
riffa_chnl_if chnl_in,
output rx_done,
output reg [31:0] rx_index,
output reg rx_last,
output reg [31:0] rx_len,
output reg [30:0] rx_off,
output rx_data_ren,
output rd_empty,
output [(8*N)-1:0] rd_data,
input rd_en,
 
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
riffa_chnl_rx_fsm
riffa_chnl_rx_fsm_i
(
.rx(chnl_in.rx),
.rx_data_valid(chnl_in.rx_data_valid),
.rx_ack(chnl_in.rx_ack),
.*
);
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(chnl_in.rx & chnl_in.rx_ack)
begin
rx_last <= chnl_in.rx_last;
rx_len <= chnl_in.rx_len;
rx_off <= chnl_in.rx_off;
end
 
 
// --------------------------------------------------------------------
//
wire [(8*N)-1:0] wr_data = chnl_in.rx_data;
wire wr_full;
wire wr_en = chnl_in.rx_data_ren & chnl_in.rx_data_valid;
 
tiny_sync_fifo #(.W((8*N)))
tiny_sync_fifo_i(.*);
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | rx_done)
rx_index = 0;
else if(rd_en)
rx_index <= rx_index + RW;
 
 
// --------------------------------------------------------------------
//
assign rx_data_ren = ~wr_full;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_rx_fsm.sv
0,0 → 1,100
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_rx_fsm
(
input rx,
input rx_data_valid,
output rx_ack,
output rx_done,
 
input reset,
input clk
);
 
//---------------------------------------------------
// state machine binary definitions
enum reg [4:0]
{
IDLE = 5'b0_0001,
ACK = 5'b0_0010,
RX = 5'b0_0100,
PENDING = 5'b0_1000,
ERROR = 5'b1_0000
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge clk)
if(reset)
state <= IDLE;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
IDLE: if(rx)
next_state <= ACK;
else
next_state <= IDLE;
 
ACK: next_state <= RX;
 
RX: if(rx)
next_state <= RX;
else if(rx_data_valid)
next_state <= PENDING;
else
next_state <= IDLE;
 
PENDING: if(rx_data_valid)
next_state <= PENDING;
else
next_state <= IDLE;
 
ERROR: next_state <= IDLE;
 
default: next_state <= ERROR;
 
endcase
 
 
// --------------------------------------------------------------------
//
assign rx_ack = (state == ACK);
assign rx_done = (state != IDLE) & (next_state == IDLE);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_tx.sv
0,0 → 1,75
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chn_tx
#(
N, // data bus width in bytes
D = 2 // TX data fifo depth
)
(
riffa_chnl_if chnl_in,
input tx_ready,
input tx_done,
output reg [31:0] tx_index,
input tx_last,
input [31:0] tx_len,
input [30:0] tx_off,
 
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
riffa_chnl_tx_fsm
riffa_chnl_tx_fsm_i
(
.tx(chnl_in.tx),
.tx_ack(chnl_in.tx_ack),
.*
);
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | ~chnl_in.tx)
tx_index = 0;
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
tx_index <= tx_index + RW;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_tx_fsm.sv
0,0 → 1,94
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_tx_fsm
(
input tx_ready,
output tx,
input tx_ack,
input tx_done,
 
input reset,
input clk
);
 
//---------------------------------------------------
// state machine binary definitions
enum reg [3:0]
{
IDLE = 4'b0001,
ACK = 4'b0010,
TX = 4'b0100,
ERROR = 4'b1000
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge clk)
if(reset)
state <= IDLE;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
IDLE: if(tx_ready)
next_state <= ACK;
else
next_state <= IDLE;
 
ACK: if(tx_ack)
next_state <= TX;
else
next_state <= ACK;
 
TX: if(~tx_done)
next_state <= TX;
else
next_state <= IDLE;
 
ERROR: next_state <= IDLE;
 
default: next_state <= ERROR;
 
endcase
 
 
// --------------------------------------------------------------------
//
assign tx = (state == ACK) | (state == TX);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_w.sv
0,0 → 1,116
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
riffa_chnl_w
#(
parameter C_NUM_CHNL,
parameter C_PCI_DATA_WIDTH,
parameter SIG_CHNL_LENGTH_W,
parameter SIG_CHNL_OFFSET_W
)
(
// RIFFA Interface Signals
output [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
input [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
output [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
input [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
input [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
input [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been received
 
output [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
output [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
input [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgment signal
output [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
output [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
output [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN, // Channel write data has been received
 
riffa_chnl_if chnl_in[C_NUM_CHNL]
);
 
// --------------------------------------------------------------------
//
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1)
begin : channels
assign CHNL_RX_CLK[i] = chnl_in[i].rx_clk;
assign chnl_in[i].rx = CHNL_RX[i];
assign CHNL_RX_ACK[i] = chnl_in[i].rx_ack;
assign chnl_in[i].rx_last = CHNL_RX_LAST[i];
assign chnl_in[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
assign chnl_in[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
assign chnl_in[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
assign chnl_in[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
assign CHNL_RX_DATA_REN[i] = chnl_in[i].rx_data_ren;
 
assign CHNL_TX_CLK[i] = chnl_in[i].tx_clk;
assign CHNL_TX[i] = chnl_in[i].tx;
assign chnl_in[i].tx_ack = CHNL_TX_ACK[i];
assign CHNL_TX_LAST[i] = chnl_in[i].tx_last;
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_in[i].tx_len;
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_in[i].tx_off;
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_in[i].tx_data;
assign CHNL_TX_DATA_VALID[i] = chnl_in[i].tx_data_valid;
assign chnl_in[i].tx_data_ren = CHNL_TX_DATA_REN[i];
end
endgenerate
 
 
// // --------------------------------------------------------------------
// //
// wire [C_NUM_CHNL-1:0] CHNL_RX_CLK;
// wire [C_NUM_CHNL-1:0] CHNL_RX;
// wire [C_NUM_CHNL-1:0] CHNL_RX_ACK;
// wire [C_NUM_CHNL-1:0] CHNL_RX_LAST;
// wire [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN;
// wire [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF;
// wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA;
// wire [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID;
// wire [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN;
// wire [C_NUM_CHNL-1:0] CHNL_TX_CLK;
// wire [C_NUM_CHNL-1:0] CHNL_TX;
// wire [C_NUM_CHNL-1:0] CHNL_TX_ACK;
// wire [C_NUM_CHNL-1:0] CHNL_TX_LAST;
// wire [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN;
// wire [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF;
// wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA;
// wire [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID;
// wire [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer.sv
0,0 → 1,137
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_downsizer
#(
N, // PCIe IP data in width in bytes
S // data out size divisor
)
(
input xx_in,
output ack_in,
input last_in,
input [31:0] len_in,
input [30:0] off_in,
input [(8*N)-1:0] data_in,
input data_valid_in,
output data_ren_in,
 
output last_out,
output reg [31:0] len_out,
output reg [30:0] off_out,
output [(8*N/S)-1:0] data_out,
output data_valid_out,
input data_ren_out,
 
input reset,
input clk
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_divisor: assert(S > 1) else $fatal;
a_data_mod: assert(N % S == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
wire [(8*N)-1:0] wr_data = data_in;
wire wr_full;
wire wr_en = data_ren_in & data_valid_in;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
 
tiny_sync_fifo #(.W((8*N)))
tiny_sync_fifo_i(.*);
 
 
// --------------------------------------------------------------------
//
localparam M_A = $clog2(S);
localparam M_D = 2 ** M_A;
localparam M_NW = (N*8)/ S;
 
wire [M_A-1:0] select;
 
riffa_chnl_xx_downsizer_fsm #(.N(N), .S(S), .M_A(M_A))
riffa_chnl_xx_downsizer_fsm_i(.*);
 
 
// --------------------------------------------------------------------
//
wire [M_NW-1:0] mux_in [M_D-1:0];
 
recursive_mux #(.A(M_A), .W(M_NW))
tdata_mux_i(.data_in(mux_in), .data_out(data_out), .*);
 
 
// --------------------------------------------------------------------
//
generate
begin: rd_data_gen
for(genvar j = 0; j < M_D; j++)
assign mux_in[j] = rd_data[j*M_NW +: M_NW];
end
endgenerate
 
 
// --------------------------------------------------------------------
//
reg last_in_r;
 
always_ff @(posedge clk)
if(xx_in & ack_in)
begin
last_in_r <= last_in;
len_out <= len_in;
off_out <= off_in;
end
 
 
// --------------------------------------------------------------------
//
riffa_chnl_fsm
riffa_chnl_fsm_i(.*);
// --------------------------------------------------------------------
//
assign last_out = (select == S - 1) ? last_in_r : 0; // need to fix
assign data_ren_in = ~wr_full;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer_fsm.sv
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_downsizer_fsm
#(
N, // PCIe IP data in width in bytes
S, // data out size divisor
M_A
)
(
input rd_empty,
input data_ren_out,
 
output rd_en,
output data_valid_out,
output reg [M_A-1:0] select,
 
input reset,
input clk
);
 
// --------------------------------------------------------------------
//
wire almost_last_word;
 
 
//---------------------------------------------------
// state machine binary definitions
enum reg [2:0]
{
GET_WORD_IN = 3'b001,
MUX_WORD_OUT = 3'b010,
LAST_WORD_OUT = 3'b100
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge clk)
if(reset)
state <= GET_WORD_IN;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
GET_WORD_IN: if(~rd_empty)
next_state <= MUX_WORD_OUT;
else
next_state <= GET_WORD_IN;
 
MUX_WORD_OUT: if(rd_empty)
next_state <= GET_WORD_IN;
else if(almost_last_word & data_ren_out)
next_state <= LAST_WORD_OUT;
else
next_state <= MUX_WORD_OUT;
 
LAST_WORD_OUT: if(~data_ren_out)
next_state <= LAST_WORD_OUT;
else
next_state <= MUX_WORD_OUT;
 
default: next_state <= GET_WORD_IN;
 
endcase
 
 
// --------------------------------------------------------------------
//
assign almost_last_word = (select == S - 2);
 
always_ff @(posedge clk)
if(reset | (state == GET_WORD_IN))
select <= 0;
else if(data_valid_out & data_ren_out)
select <= select + 1;
 
 
// --------------------------------------------------------------------
//
wire changing_state = (state != next_state);
assign rd_en = (state == LAST_WORD_OUT) & changing_state;
assign data_valid_out = (state != GET_WORD_IN) & ~rd_empty;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_upsizer.sv
0,0 → 1,73
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_upsizer
#(
N, // PCIe IP data in width in bytes
S // data out size multiplier
)
(
input xx_in,
output ack_in,
input last_in,
input [31:0] len_in,
input [30:0] off_in,
input [(8*N)-1:0] data_in,
input data_valid_in,
output data_ren_in,
 
output last_out,
output [31:0] len_out,
output [30:0] off_out,
output [(8*N*S)-1:0] data_out,
output data_valid_out,
input data_ren_out,
input reset,
input clk
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_multiplier: assert((S > 1) & (S % 2 == 0))else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_file.sv
0,0 → 1,138
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_register_file
#(
A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
)
(
riffa_chnl_if chnl_in,
riffa_register_if r_if,
input clk, // must be same clock domain as rx_clk & tx_clk
input reset // must be same clock domain as rx_clk & tx_clk
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
a_data_bus_mod: assert(N % 4 == 0) else $fatal;
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
localparam MI = 2 ** MW; // mux inputs
localparam LB = $clog2(RW);
localparam UB = LB + MW;
 
 
// --------------------------------------------------------------------
//
wire rx_done;
wire [31:0] rx_index;
wire rx_last;
wire [31:0] rx_len;
wire [30:0] rx_off;
wire rx_data_ren;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.*);
 
 
// --------------------------------------------------------------------
//
wire register_select [MI-1:0];
genvar j;
 
generate
for(j = 0; j < MI; j = j + 1)
begin: decoder_gen
assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;
 
always_ff @(posedge clk)
if(reset)
r_if.register_out[j] <= 0;
else if(rd_en & register_select[j])
r_if.register_out[j] <= rd_data;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
 
 
// --------------------------------------------------------------------
//
wire tx_ready = 1;
wire tx_last = 1;
wire [31:0] tx_len = RW*MI;
wire [30:0] tx_off = 0;
wire [31:0] tx_index;
wire tx_done = (tx_index >= chnl_in.tx_len - RW);
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
 
 
// --------------------------------------------------------------------
//
recursive_mux #(.A(MW), .W(N*8))
recursive_mux_i
(
.select(tx_index[UB:LB]),
.data_in(r_if.register_in),
.data_out(chnl_in.tx_data)
);
 
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = 1;
assign chnl_in.tx_len = RW*MI;
assign chnl_in.tx_off = 0;
assign chnl_in.tx_data_valid = 1;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_if.sv
0,0 → 1,49
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
riffa_register_if
#(
N, // data bus width in bytes
MW, // mux select width
MI = 2 ** MW // mux inputs
)
(
input clk,
input reset
);
 
wire [(N*8)-1:0] register_in [MI-1:0];
reg [(N*8)-1:0] register_out [MI-1:0];
 
 
// --------------------------------------------------------------------
//
endinterface
 
 
/qaz_libs/trunk/avalon_lib/sim/src/ast_monitor.sv
0,0 → 1,99
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1 ps
 
module
ast_monitor
#(
ST_SYMBOL_W,
ST_NUMSYMBOLS,
USE_PACKET,
ST_READY_LATENCY,
USE_CHANNEL = 0,
USE_ERROR = 0,
USE_READY = 1,
USE_VALID = 1,
USE_EMPTY = 1,
ST_ERROR_W = 1,
ST_MAX_PACKET_SIZE = 1,
ST_MAX_CHANNELS = 0,
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS),
ST_EMPTY_W = (ST_NUMSYMBOLS == 1) ? 1 : $clog2(ST_NUMSYMBOLS)
)
(
ast_if src,
ast_if sink,
input clk,
input reset
);
 
altera_avalon_st_monitor
#(
.USE_PACKET (USE_PACKET),
.USE_CHANNEL (USE_CHANNEL),
.USE_ERROR (USE_ERROR),
.USE_READY (USE_READY),
.USE_VALID (USE_VALID),
.USE_EMPTY (USE_EMPTY),
.ST_SYMBOL_W (ST_SYMBOL_W),
.ST_NUMSYMBOLS (ST_NUMSYMBOLS),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ST_ERROR_W (ST_ERROR_W),
.ST_EMPTY_W (ST_EMPTY_W),
.ST_READY_LATENCY (ST_READY_LATENCY),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (ST_MAX_CHANNELS),
.ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE),
.VHDL_ID (0)
)
altera_avalon_st_monitor_i
(
.clk (clk), // clk.clk
.reset (reset), // clk_reset.reset
.src_data (src.data), // src.data
.src_valid (src.valid), // .valid
.src_ready (src.ready), // .ready
.src_startofpacket (src.startofpacket), // .startofpacket
.src_endofpacket (src.endofpacket), // .endofpacket
.src_empty (src.empty), // .empty
.src_channel (src.channel), // .channel
.src_error (src.error), // .error
.sink_data (sink.data), // sink.data
.sink_valid (sink.valid), // .valid
.sink_ready (sink.ready), // .ready
.sink_startofpacket (sink.startofpacket), // .startofpacket
.sink_endofpacket (sink.endofpacket), // .endofpacket
.sink_empty (sink.empty), // .empty
.sink_channel (sink.channel), // .channel
.sink_error (sink.error) // .error
);
 
 
// --------------------------------------------------------------------
//
endmodule
/qaz_libs/trunk/avalon_lib/sim/src/ast_sink.sv
0,0 → 1,87
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1 ps
 
module
ast_sink
#(
ST_SYMBOL_W,
ST_NUMSYMBOLS,
USE_PACKET,
ST_READY_LATENCY,
USE_CHANNEL = 0,
USE_ERROR = 0,
USE_READY = 1,
USE_VALID = 1,
USE_EMPTY = 1,
ST_ERROR_W = 1,
ST_MAX_CHANNELS = 0,
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS),
ST_EMPTY_W = $clog2(ST_NUMSYMBOLS)
)
(
ast_if sink,
input clk,
input reset
);
 
altera_avalon_st_sink_bfm
#(
.USE_PACKET (USE_PACKET),
.USE_CHANNEL (USE_CHANNEL),
.USE_ERROR (USE_ERROR),
.USE_READY (USE_READY),
.USE_VALID (USE_VALID),
.USE_EMPTY (USE_EMPTY),
.ST_SYMBOL_W (ST_SYMBOL_W),
.ST_NUMSYMBOLS (ST_NUMSYMBOLS),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ST_ERROR_W (ST_ERROR_W),
.ST_EMPTY_W (ST_EMPTY_W),
.ST_READY_LATENCY (ST_READY_LATENCY),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (ST_MAX_CHANNELS),
.VHDL_ID (0)
)
bfm
(
.clk (clk), // clk.clk
.reset (reset), // clk_reset.reset
.sink_data (sink.data), // sink.data
.sink_valid (sink.valid), // .valid
.sink_ready (sink.ready), // .ready
.sink_startofpacket (sink.startofpacket), // .startofpacket
.sink_endofpacket (sink.endofpacket), // .endofpacket
.sink_empty (sink.empty), // .empty
.sink_channel (sink.channel), // .channel
.sink_error (sink.error) // .error
);
 
// --------------------------------------------------------------------
//
endmodule
/qaz_libs/trunk/avalon_lib/sim/src/ast_source.sv
0,0 → 1,87
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1 ps
 
module
ast_source
#(
ST_SYMBOL_W,
ST_NUMSYMBOLS,
USE_PACKET,
ST_READY_LATENCY,
USE_CHANNEL = 0,
USE_ERROR = 0,
USE_READY = 1,
USE_VALID = 1,
USE_EMPTY = 1,
ST_ERROR_W = 1,
ST_MAX_CHANNELS = 0,
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS),
ST_EMPTY_W = $clog2(ST_NUMSYMBOLS)
)
(
ast_if src,
input clk,
input reset
);
 
altera_avalon_st_source_bfm
#(
.USE_PACKET (USE_PACKET),
.USE_CHANNEL (USE_CHANNEL),
.USE_ERROR (USE_ERROR),
.USE_READY (USE_READY),
.USE_VALID (USE_VALID),
.USE_EMPTY (USE_EMPTY),
.ST_SYMBOL_W (ST_SYMBOL_W),
.ST_NUMSYMBOLS (ST_NUMSYMBOLS),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ST_ERROR_W (ST_ERROR_W),
.ST_EMPTY_W (ST_EMPTY_W),
.ST_READY_LATENCY (ST_READY_LATENCY),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (ST_MAX_CHANNELS),
.VHDL_ID (0)
)
bfm
(
.clk (clk), // clk.clk
.reset (reset), // clk_reset.reset
.src_data (src.data), // src.data
.src_valid (src.valid), // .valid
.src_ready (src.ready), // .ready
.src_startofpacket (src.startofpacket), // .startofpacket
.src_endofpacket (src.endofpacket), // .endofpacket
.src_empty (src.empty), // .empty
.src_channel (src.channel), // .channel
.src_error (src.error) // .error
);
 
// --------------------------------------------------------------------
//
endmodule
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_ast_monitor
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) avalon_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
# vsim -f ./sim.f work.tb_top
 
# log all signals
# log -r *
 
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/tb_ast_monitor.f
0,0 → 1,8
#
 
${PROJECT_DIR}/src/ast_if.sv
 
${PROJECT_DIR}/sim/src/ast_monitor.sv
${PROJECT_DIR}/sim/src/ast_sink.sv
${PROJECT_DIR}/sim/src/ast_source.sv
 
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/tb_ast_monitor.sv
0,0 → 1,162
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire clk = tb_clk;
wire reset = tb_rst_s;
 
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_ast_monitor_pkg::*;
 
 
// --------------------------------------------------------------------
//
ast_if #(EW, CW, SW, NSW) src(.*);
ast_if #(EW, CW, SW, NSW) sink(.*);
 
 
// --------------------------------------------------------------------
//
 
 
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
 
// --------------------------------------------------------------------
//
ast_monitor
#(
.ST_SYMBOL_W(ST_SYMBOL_W),
.ST_NUMSYMBOLS(ST_NUMSYMBOLS),
.USE_PACKET(USE_PACKET),
.ST_READY_LATENCY(ST_READY_LATENCY),
.USE_CHANNEL(USE_CHANNEL),
.USE_ERROR(USE_ERROR),
.USE_READY(USE_READY),
.USE_VALID(USE_VALID),
.USE_EMPTY(USE_EMPTY),
.ST_ERROR_W(ST_ERROR_W),
.ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE),
.ST_MAX_CHANNELS(ST_MAX_CHANNELS)
)
ast_monitor_i(.sink(src), .src(sink), .*);
 
// --------------------------------------------------------------------
//
ast_source
#(
.ST_SYMBOL_W(ST_SYMBOL_W),
.ST_NUMSYMBOLS(ST_NUMSYMBOLS),
.USE_PACKET(USE_PACKET),
.ST_READY_LATENCY(ST_READY_LATENCY),
.USE_CHANNEL(USE_CHANNEL),
.USE_ERROR(USE_ERROR),
.USE_READY(USE_READY),
.USE_VALID(USE_VALID),
.USE_EMPTY(USE_EMPTY),
.ST_ERROR_W(ST_ERROR_W),
.ST_MAX_CHANNELS(ST_MAX_CHANNELS)
)
ast_source_i(.*);
 
 
// --------------------------------------------------------------------
//
ast_sink
#(
.ST_SYMBOL_W(ST_SYMBOL_W),
.ST_NUMSYMBOLS(ST_NUMSYMBOLS),
.USE_PACKET(USE_PACKET),
.ST_READY_LATENCY(ST_READY_LATENCY),
.USE_CHANNEL(USE_CHANNEL),
.USE_ERROR(USE_ERROR),
.USE_READY(USE_READY),
.USE_VALID(USE_VALID),
.USE_EMPTY(USE_EMPTY),
.ST_ERROR_W(ST_ERROR_W),
.ST_MAX_CHANNELS(ST_MAX_CHANNELS)
)
ast_sink_i(.*);
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/tb_ast_monitor_pkg.sv
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_ast_monitor_pkg;
 
// --------------------------------------------------------------------
//
localparam EW = 1;
localparam CW = 1;
localparam SW = 8;
localparam NSW = 4;
localparam ST_SYMBOL_W = SW;
localparam ST_NUMSYMBOLS = NSW;
localparam USE_PACKET = 1;
localparam ST_READY_LATENCY = 3;
localparam USE_CHANNEL = 0;
localparam USE_ERROR = 0;
localparam USE_READY = 1;
localparam USE_VALID = 1;
localparam USE_EMPTY = 1;
localparam ST_ERROR_W = EW;
localparam ST_MAX_PACKET_SIZE = 1;
localparam ST_MAX_CHANNELS = 0;
 
// --------------------------------------------------------------------
//
class tb_ast_monitor_class;
 
 
 
// --------------------------------------------------------------------
//
endclass: tb_ast_monitor_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_ast_monitor_pkg
 
 
 
 
 
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/the_test.sv
0,0 → 1,102
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import verbosity_pkg::*;
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(50us);
// --------------------------------------------------------------------
// set_verbosity(VERBOSITY_DEBUG);
tb_top.ast_source_i.st_source_bfm_i.init();
tb_top.ast_sink_i.st_sink_bfm_i.init();
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(1);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(1);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(2);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(1);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
 
// --------------------------------------------------------------------
#200ns;
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
 
 
// --------------------------------------------------------------------
#1us;
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/avalon_lib/src/ast_if.sv
0,0 → 1,57
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
ast_if
#(
EW = 1, // error signal width in bits.
CW = 1, // channel width in bits.
SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces.
NSW, // Numbers of symbols per word
NSW_L = (NSW == 1) ? 1 : $clog2(NSW)
)
(
input reset,
input clk
);
 
wire [(SW*NSW)-1:0] data;
wire valid;
wire ready;
wire startofpacket;
wire endofpacket;
wire [NSW_L-1:0] empty;
wire [CW-1:0] channel;
wire [EW-1:0] error;
 
 
// --------------------------------------------------------------------
//
endinterface
 
 
/qaz_libs/trunk/avalon_lib/src/ast_ready_cycle_fsm.sv
0,0 → 1,106
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
ast_ready_cycle_fsm
(
input axis_en,
output axis_tvalid,
input axis_tready,
 
input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also
input fifo_empty,
output fifo_rd_en,
 
output data_to_axis_fsm_error,
 
input aclk,
input aresetn
);
 
//---------------------------------------------------
// state machine binary definitions
enum reg [3:0] {
IDLE_STATE = 4'b0001,
TVALID = 4'b0010,
TREADY = 4'b0100,
ERROR_STATE = 4'b1000
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= IDLE_STATE;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty)
if(axis_tready)
next_state <= TREADY;
else
next_state <= TVALID;
else
next_state <= IDLE_STATE;
 
TVALID: if(axis_tready) // wait for slave to be ready
next_state <= TREADY;
else
next_state <= TVALID;
 
TREADY: if(fifo_empty) // slave can accept data
next_state <= IDLE_STATE;
else if(axis_tready)
next_state <= TREADY;
else
next_state <= TVALID;
 
ERROR_STATE: next_state <= IDLE_STATE;
 
default: next_state <= ERROR_STATE;
 
endcase
 
 
//---------------------------------------------------
// outputs
assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY);
assign fifo_rd_en = axis_tvalid & axis_tready;
assign data_to_axis_fsm_error = (state == ERROR_STATE);
 
 
//---------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/misc/src/bram_tdp.v
0,0 → 1,87
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
 
// --------------------------------------------------------------------
// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
 
module
bram_tdp
#(
parameter W,
parameter A
)
(
// Port A
input a_clk,
input a_wr,
input [A-1:0] a_addr,
input [W-1:0] a_din,
output reg [W-1:0] a_dout,
 
// Port B
input b_clk,
input b_wr,
input [A-1:0] b_addr,
input [W-1:0] b_din,
output reg [W-1:0] b_dout
);
 
// --------------------------------------------------------------------
// Shared memory
reg [W-1:0] mem [(2**A)-1:0];
 
 
// --------------------------------------------------------------------
// Port A
always @(posedge a_clk)
begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
 
 
// --------------------------------------------------------------------
// Port B
always @(posedge b_clk)
begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/misc/src/ram/asym_ram_sdp_read_wider.v
0,0 → 1,63
// Asymmetric port RAM
// Read Wider than Write. Read Statement in loop
//asym_ram_sdp_read_wider.v
module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkA)
begin
if (enaA) begin
if (weA)
RAM[addrA] <= diA;
end
end
always @(posedge clkB)
begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (enaB) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
end
end
end
assign doB = readB;
endmodule
/qaz_libs/trunk/misc/src/ram/asym_ram_sdp_write_wider.v
0,0 → 1,63
// Asymmetric port RAM
// Write wider than Read. Write Statement in a loop.
// asym_ram_sdp_write_wider.v
module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
doB);
parameter WIDTHB = 4;
parameter SIZEB = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA = 16;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
readB <= RAM[addrB];
end
end
assign doB = readB;
always @(posedge clkA)
begin : ramwrite
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i=0; i< RATIO; i= i+ 1) begin : write1
lsbaddr = i;
if (enaA) begin
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
endmodule
/qaz_libs/trunk/misc/src/ram/bram_tdp.v
0,0 → 1,87
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
 
// --------------------------------------------------------------------
// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
 
module
bram_tdp
#(
parameter W,
parameter A
)
(
// Port A
input a_clk,
input a_wr,
input [A-1:0] a_addr,
input [W-1:0] a_din,
output reg [W-1:0] a_dout,
 
// Port B
input b_clk,
input b_wr,
input [A-1:0] b_addr,
input [W-1:0] b_din,
output reg [W-1:0] b_dout
);
 
// --------------------------------------------------------------------
// Shared memory
reg [W-1:0] mem [(2**A)-1:0];
 
 
// --------------------------------------------------------------------
// Port A
always @(posedge a_clk)
begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
 
 
// --------------------------------------------------------------------
// Port B
always @(posedge b_clk)
begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/misc/src/ram/byte_enabled_simple_dual_port_ram.sv
0,0 → 1,22
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be, // 4 bytes per word
input [31:0] wdata, // byte width = 8, 4 bytes per word
output reg [31:0] q // byte width = 8, 4 bytes per word
);
// use a multi-dimensional packed array
//to model individual bytes within the word
logic [3:0][7:0] ram[0:63]; // # words = 1 << address width
always_ff@(posedge clk)
begin
if(we) begin
if(be[0]) ram[waddr][0] <= wdata[7:0];
if(be[1]) ram[waddr][1] <= wdata[15:8];
if(be[2]) ram[waddr][2] <= wdata[23:16];
if(be[3]) ram[waddr][3] <= wdata[31:24];
end
q <= ram[raddr];
end
endmodule
/qaz_libs/trunk/misc/src/ram/read_mixed_width_ram.sv
0,0 → 1,17
module
read_mixed_width_ram // 256x32 write and 1024x8 read
(
input [7:0] waddr,
input [31:0] wdata,
input we, clk,
input [9:0] raddr,
output logic [7:0] q
);
logic [3:0][7:0] ram[0:255];
always_ff@(posedge clk)
begin
if(we)
ram[waddr] <= wdata;
q <= ram[raddr / 4][raddr % 4];
end
endmodule
/qaz_libs/trunk/misc/src/ram/write_mixed_width_ram.sv
0,0 → 1,18
module
write_mixed_width_ram // 1024x8 write and 256x32 read
(
input [7:0] waddr,
input [31:0] wdata,
input we, clk,
input [9:0] raddr,
output logic [7:0] q
);
logic [3:0][7:0] ram[0:255];
always_ff@(posedge clk)
begin
if(we)
ram[waddr / 4][waddr % 4] <= wdata;
q <= ram[raddr];
end
endmodule
 
/qaz_libs/trunk/sim/libs/avalon_lib_verilog/avalon_lib_base.f
0,0 → 1,5
#
 
 
${LIB_BASE_DIR}/avalon_lib/src/ast_if.sv
 
/qaz_libs/trunk/sim/libs/avalon_lib_verilog/avalon_lib_checker.f
0,0 → 1,17
#
 
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/avalon_utilities_pkg.sv
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_coverage.sv
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv
${LIB_BASE_DIR}/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv
 
${LIB_BASE_DIR}/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv
 
${LIB_BASE_DIR}/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv
 
${LIB_BASE_DIR}/avalon_lib/sim/src/ast_monitor.sv
${LIB_BASE_DIR}/avalon_lib/sim/src/ast_sink.sv
${LIB_BASE_DIR}/avalon_lib/sim/src/ast_source.sv
 
/qaz_libs/trunk/sim/libs/qaz_lib_verilog/misc.f
1,5 → 1,6
#
 
${LIB_BASE_DIR}/misc/src/ram/bram_tdp.v
 
${LIB_BASE_DIR}/misc/src/recursive_mux.sv
${LIB_BASE_DIR}/misc/src/one_hot_encoder.sv

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