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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 36 to Rev 37
    Reverse comparison

Rev 36 → Rev 37

/qaz_libs/trunk/PCIe/sim/src/riffa_agent_class_pkg.sv
57,8 → 57,7
task queue_tx_constant(int len, int off, bit last, logic [(8*N)-1:0] value);
tr_h = new(len, off, last);
tr_h.constant(len, off, last, value);
tx_h.put(tr_h);
tx_q.put(tr_h);
queue_tx(tr_h);
endtask: queue_tx_constant
 
 
67,8 → 66,7
task queue_tx_counting(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.counting(len, off, last);
tx_h.put(tr_h);
tx_q.put(tr_h);
queue_tx(tr_h);
endtask: queue_tx_counting
 
 
77,8 → 75,7
task queue_tx_random(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.random(len, off, last);
tx_h.put(tr_h);
tx_q.put(tr_h);
queue_tx(tr_h);
endtask: queue_tx_random
 
 
/qaz_libs/trunk/PCIe/sim/src/riffa_bfm_class_pkg.sv
111,7 → 111,7
begin
if(error_count > max_mismatches)
break;
if(this.data[i] != to.data[i])
if(this.data[i] !== to.data[i])
begin
$display("!!! %16.t | ERROR! | 0x%x | this != to | 0x%x != 0x%x", $time, i, this.data[i], to.data[i]);
error_count++;
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv
67,9 → 67,15
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*B, 0, 1);
tb_top.a_h.wait_for_rx();
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.tr_h = new(RW, 0, 1);
tb_top.a_h.tr_h.constant(RW, 0, 1, 1);
tb_top.a_h.queue_tx(tb_top.a_h.tr_h);
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
58,8 → 58,7
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
 
// axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern #(.W(W), .WPB(WPB))
axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern_i(.*);
 
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_file.sv
82,12 → 82,13
begin: register_j_gen
for(k = 0; k < RW; k = k + 1)
begin: register_k_gen
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
assign r_if.wr_en[(j*RW) + k] = rd_en & register_select[(j*RW) + k];
 
always_ff @(posedge clk)
if(reset)
r_if.register_out[(j*RW) + k] <= 0;
else if(rd_en & register_select[(j*RW) + k])
else if(r_if.wr_en[(j*RW) + k])
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
end
end
102,7 → 103,8
 
// --------------------------------------------------------------------
//
wire tx_ready = 1;
// write to register[0][0] to enable reading
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_if.sv
39,8 → 39,9
input reset
);
 
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
reg wr_en [RC-1:0];
 
 
// --------------------------------------------------------------------
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_file.sv
73,11 → 73,12
for(j = 0; j < MI; j = j + 1)
begin: decoder_gen
assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
assign r_if.wr_en[j] = rf_wr_en & register_select[j];
 
always_ff @(posedge aclk)
if(~aresetn)
r_if.register_out[j] <= 0;
else if(rf_wr_en & register_select[j])
else if(r_if.wr_en[j])
r_if.register_out[j] <= axi4_write_fifo.wdata;
end
endgenerate
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_if.sv
40,6 → 40,7
 
wire [(N*8)-1:0] register_in [MI-1:0];
reg [(N*8)-1:0] register_out [MI-1:0];
wire wr_en [MI-1:0];
 
 
// --------------------------------------------------------------------
46,8 → 47,8
// synthesis translate_off
initial
a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
 
 
// synthesis translate_on
// --------------------------------------------------------------------
 
/qaz_libs/trunk/axi4_stream_lib/src/axis_catenate.sv
92,6 → 92,55
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*);
genvar j;
 
generate
if(U_IS_EOP > -1)
begin: u_is_eop_gen
for(j = 0; j < U; j++)
begin: for_tuser_gen
if(j == U_IS_EOP)
begin: choped_tuser_gen
assign axis_bus[0].tuser[j] = 0;
end
else
begin: tuser_gen
assign axis_bus[0].tuser[j] = axis_in[0].tuser[j];
end
end
end
else
if(U_IS_EOP > -1)
begin: tlast_gen
assign axis_bus[0].tlast = axis_in[0].tlast;
end
else
begin: choped_tlast_gen
assign axis_bus[0].tlast = 0;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_in[0].tready = axis_bus[0].tready;
assign axis_bus[0].tvalid = axis_in[0].tvalid;
assign axis_bus[0].tdata = axis_in[0].tdata;
assign axis_bus[0].tstrb = axis_in[0].tstrb;
assign axis_bus[0].tkeep = axis_in[0].tkeep;
assign axis_bus[0].tid = axis_in[0].tid;
assign axis_bus[0].tdest = axis_in[0].tdest;
 
 
// --------------------------------------------------------------------
//
axis_alias
axis_alias_i(axis_in[1], axis_bus[1]);
 
 
// --------------------------------------------------------------------
//
defparam axis_mux_i.N = N; // why are needed these for recursive modules?
defparam axis_mux_i.I = I;
defparam axis_mux_i.D = D;
98,7 → 147,7
defparam axis_mux_i.U = U;
axis_mux
// axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i(.axis_in(axis_in), .*);
axis_mux_i(.axis_in(axis_bus), .*);
 
 
// --------------------------------------------------------------------
/qaz_libs/trunk/axi4_stream_lib/src/axis_map_fifo.sv
29,12 → 29,12
axis_map_fifo
#(
N, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0, // set to 1 to enable, 0 to disable
USE_XID = 0, // set to 1 to enable, 0 to disable
// USE_XID = 0, // set to 1 to enable, 0 to disable
W = 0
)
(
50,9 → 50,9
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
a_xid_unsuported: assert(USE_XID == 0) else $fatal;
// a_tid_unsuported: assert(I == 0) else $fatal;
// a_tdest_unsuported: assert(D == 0) else $fatal;
// a_xid_unsuported: assert(USE_XID == 0) else $fatal;
a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
end
// synthesis translate_on
67,19 → 67,19
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb,
axis_in.tkeep
axis_in.tkeep,
axis_in.tdata
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
axis_out.tkeep,
axis_out.tdata
} = rd_data;
end
else if(USE_TSTRB)
86,17 → 86,17
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb
axis_in.tstrb,
axis_in.tdata
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
axis_out.tstrb,
axis_out.tdata
} = rd_data;
end
else if(USE_TKEEP)
103,17 → 103,17
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tkeep
axis_in.tkeep,
axis_in.tdata
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
axis_out.tkeep,
axis_out.tdata
} = rd_data;
end
else
120,15 → 120,15
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser
axis_in.tuser,
axis_in.tdata
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
axis_out.tuser,
axis_out.tdata
} = rd_data;
end
end
/qaz_libs/trunk/axi4_stream_lib/src/axis_mux.sv
45,7 → 45,12
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
defparam axis_mux_out.N = N; // why are needed these for recursive modules?
defparam axis_mux_out.I = I;
defparam axis_mux_out.D = D;
defparam axis_mux_out.U = U;
axis_if axis_mux_out(.*);
// axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
 
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready;
assign axis_in[1].tready = select ? axis_mux_out.tready : 0;
62,15 → 67,19
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_i.I = I;
defparam axis_register_slice_i.D = D;
defparam axis_register_slice_i.U = U;
axis_register_slice
#(
.N(N),
.I(I),
.D(D),
.U(U),
.USE_TSTRB(0),
.USE_TKEEP(0)
)
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(0),
// .USE_TKEEP(0)
// )
axis_register_slice_i
(
.axis_in(axis_mux_out), // slave
/qaz_libs/trunk/axi4_stream_lib/src/axis_switch_allocator.sv
46,21 → 46,6
 
// --------------------------------------------------------------------
//
wire eop_in;
 
axis_eop_set #(U_IS_EOP)
axis_eop_set_i
(
.axis_in(axis_in),
.tready(axis_switch_in.tready),
.tvalid(axis_in.tvalid),
.axis_eop(eop_in),
.*
);
 
 
// --------------------------------------------------------------------
//
wire eop_out_mux;
reg [SA-1:0] select;
 
82,6 → 67,21
 
 
// --------------------------------------------------------------------
//
wire eop_in;
 
axis_eop_set #(U_IS_EOP)
axis_eop_set_i
(
.axis_in(axis_in),
.tready(axis_switch_in.tready),
.tvalid(axis_in.tvalid),
.axis_eop(eop_in),
.*
);
 
 
// --------------------------------------------------------------------
// state machine binary definitions
enum reg [3:0]
{
116,9 → 116,9
next_state <= FLUSH;
 
SWITCH: next_state <= SETTLE;
SETTLE: next_state <= ALLOT; // let select propagate to the switches
 
SETTLE: next_state <= ALLOT; // let select propagate to the switches
 
default: next_state <= ALLOT;
endcase
 
/qaz_libs/trunk/basal/src/RAM/bram_tdp.v
60,25 → 60,25
// --------------------------------------------------------------------
// Port A
always @(posedge a_clk)
if(a_wr)
begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
a_dout <= a_din;
mem[a_addr] <= a_din;
end
else
a_dout <= mem[a_addr];
 
 
// --------------------------------------------------------------------
// Port B
always @(posedge b_clk)
if(b_wr)
begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
b_dout <= b_din;
mem[b_addr] <= b_din;
end
else
b_dout <= mem[b_addr];
 
 
// --------------------------------------------------------------------
/qaz_libs/trunk/basal/src/synchronize/pulse_synchronizer.v
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
pulse_synchronizer
(
input in,
output out,
output busy,
input in_clk,
input in_reset,
input out_clk,
input out_reset
);
// --------------------------------------------------------------------
//
reg [1:0] in_s;
reg in_r;
wire in_w = in ? 1 : (in_s[1] ? 0 : in_r);
always @(posedge in_clk)
if(in_reset)
in_r <= 0;
else
in_r <= in_w;
 
// --------------------------------------------------------------------
//
reg [2:0] out_r;
always @(posedge out_clk)
if(out_reset)
out_r <= 0;
else
out_r <= {out_r[1:0], in_r};
 
// --------------------------------------------------------------------
//
always @(posedge in_clk)
if(in_reset)
in_s <= 0;
else
in_s <= {in_s[0], out_r[1]};
 
// --------------------------------------------------------------------
//
assign out = out_r[1] & ~out_r[2];
assign busy = in_s[1] | in_r;
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/sim/libs/axi4_lib_verilog/axi4_stream_base.f
6,6 → 6,7
${LIB_BASE_DIR}/axi4_stream_lib/src/data_to_axis_fsm.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_register_slice.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_map_fifo.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_mux.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_alias.sv
15,3 → 16,6
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_set.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_mux.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_catenate.sv
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_switch.sv
/qaz_libs/trunk/sim/libs/qaz_lib_verilog/basal.f
34,4 → 34,5
 
${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v
${LIB_BASE_DIR}/basal/src/synchronize/pulse_synchronizer.v
 

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