URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 43 to Rev 42
- ↔ Reverse comparison
Rev 43 → Rev 42
/qaz_libs/trunk/BFM/src/video_frame/video_frame_pkg.sv
30,20 → 30,16
import logger_pkg::*; |
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typedef struct |
{ |
int pixel[]; |
} line_s; |
{ |
int pixel[]; |
} line_s; |
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typedef struct |
{ |
int x; |
int y; |
} frame_coordinate_t; |
typedef struct |
{ |
int x; |
int y; |
} frame_coordinate_t; |
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typedef int flattened_frame_t[]; |
typedef int unsigned video_array_t[][]; |
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// -------------------------------------------------------------------- |
class video_frame_class; |
logger_class log; |
rand int frame_id; |
116,8 → 112,6
input frame_coordinate_t coordinate |
); |
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extern function flattened_frame_t flatten_frame(); |
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extern virtual function void make_constant |
( |
input int pixel |
134,8 → 128,6
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extern virtual function void make_random(); |
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extern virtual function void shift_right(ref line_s column); |
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extern virtual function void copy |
( |
ref video_frame_class from |
198,21 → 190,7
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endfunction: read_pixel |
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// -------------------------------------------------------------------- |
// |
function flattened_frame_t video_frame_class::flatten_frame(); |
int i = 0; |
log.info($sformatf("%m")); |
flatten_frame = new[lines_per_frame*pixels_per_line]; |
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foreach(this.lines[l]) |
foreach(this.lines[l].pixel[p]) |
begin |
flatten_frame[i] = this.lines[l].pixel[p]; |
i++; |
end |
endfunction: flatten_frame |
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// -------------------------------------------------------------------- |
// |
function void video_frame_class::make_constant |
405,22 → 383,12
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foreach(tail.lines[l].pixel[p]) |
catenate_horizontally.lines[l].pixel[p + this.pixels_per_line] = tail.lines[l].pixel[p]; |
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end |
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endfunction: catenate_horizontally |
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// -------------------------------------------------------------------- |
// |
function void video_frame_class::shift_right(ref line_s column); |
log.info($sformatf("%m")); |
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foreach(this.lines[l]) |
for(int p = pixels_per_line - 1; p > 0; p--) |
this.lines[l].pixel[p] = this.lines[l].pixel[p - 1]; |
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foreach(this.lines[l]) |
this.lines[l].pixel[0] = column.pixel[l]; |
endfunction: shift_right |
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// -------------------------------------------------------------------- |
// |
function int video_frame_class::compare_line |
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_tx.sv
59,7 → 59,7
// |
always_ff @(posedge clk) |
if(reset | ~chnl_bus.tx | tx_done) |
tx_index <= 0; |
tx_index = 0; |
else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren) |
tx_index <= tx_index + (N/4); // increment by 32 bit words |
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/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_rx.sv
84,7 → 84,7
// |
always_ff @(posedge clk) |
if(reset | rx_done) |
rx_index <= 0; |
rx_index = 0; |
else if(rd_en) |
rx_index <= rx_index + (N/4); // increment by 32 bit words |
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/qaz_libs/trunk/basal/src/FIFOs/tiny_sync_fifo.v
File deleted
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_file.sv
28,10 → 28,10
module |
axi4_lite_register_file |
#( |
A, // address bus width, must be 32 or greater for axi lite |
N, // data bus width in bytes, must be 4 or 8 for axi lite |
I = 1, // ID width |
MW // mux select width |
A = 32, // address bus width, must be 32 or greater for axi lite |
N = 8, // data bus width in bytes, must be 4 or 8 for axi lite |
I = 1, // ID width |
MW = 3 // mux select width |
) |
( |
axi4_if axi4_s, |
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_if.sv
32,6 → 32,10
N = 8, // data bus width in bytes, must be 4 or 8 for axi lite |
MW = 3, // mux select width |
MI = 2 ** MW // mux inputs |
) |
( |
input aclk, |
input aresetn |
); |
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wire [(N*8)-1:0] register_in [MI-1:0]; |
38,10 → 42,13
reg [(N*8)-1:0] register_out [MI-1:0]; |
wire wr_en [MI-1:0]; |
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// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal; |
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// synthesis translate_on |
// -------------------------------------------------------------------- |
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/qaz_libs/trunk/axi4_lite_lib/sim/src/tb_axi4_lite_register_file.sv
74,8 → 74,7
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// -------------------------------------------------------------------- |
// |
// axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10)) |
axi4_checker #(.A(A), .N(N)) |
axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10)) |
axi4_s_check(.axi4_in(axi4_s)); |
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/qaz_libs/trunk/axi4_lite_lib/sim/tests/debug_axi4_lite_register_file/init_test.do
4,30 → 4,30
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global env |
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# setup environment |
do ../../../../scripts/sim_env.do |
set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_recursive_axis_mux |
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# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
sim_compile_all packages |
sim_compile_all sim |
sim_compile_all axi4_lib |
sim_compile_all axi4_lite_lib |
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# simulation $root |
vlog $env(LIB_BASE_DIR)/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv |
vlog $env(LIB_BASE_DIR)/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv |
vlog $env(PROJECT_DIR)/sim/src/axi4_lite_agent_pkg.sv |
vlog $env(PROJECT_DIR)/sim/src/tb_axi4_lite_register_file.sv |
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# compile test last |
vlog ./the_test.sv |
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# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
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# run the sim |
sim_run_test |
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/qaz_libs/trunk/axi4_lib/src/axi4_m_to_read_fifos.sv
28,11 → 28,11
module |
axi4_m_to_read_fifos |
#( |
A, // address bus width |
N, // data bus width in bytes |
I, // ID width |
R_D, |
AR_D, |
A = 32, // address bus width |
N = 8, // data bus width in bytes |
I = 1, // ID width |
R_D = 32, |
AR_D = 2, |
WATERMARK = 0, |
USE_ADVANCED_PROTOCOL = 0 |
) |
183,18 → 183,18
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assign r_wr_data = |
{ |
axi4_m.rdata, |
axi4_m.rid, |
axi4_m.rresp, |
axi4_m.rlast, |
axi4_m.rdata |
axi4_m.rresp |
}; |
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assign |
{ |
axi4_read_fifo.rdata, |
axi4_read_fifo.rid, |
axi4_read_fifo.rresp, |
axi4_read_fifo.rlast, |
axi4_read_fifo.rdata |
axi4_read_fifo.rresp |
} = r_rd_data; |
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