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Rev 50 → Rev 49

/qaz_libs/trunk/BFM/sim/tests/tb_video_frame_dpi/py_raw_to_frame.py
0,0 → 1,92
#
# ////////////////////////////////////////////////////////////////////
# // ////
# // Copyright (C) 2018 Authors and OPENCORES.ORG ////
# // ////
# // This source file may be used and distributed without ////
# // restriction provided that this copyright statement is not ////
# // removed from the file and that any derivative work contains ////
# // the original copyright notice and the associated disclaimer. ////
# // ////
# // This source file is free software; you can redistribute it ////
# // and/or modify it under the terms of the GNU Lesser General ////
# // Public License as published by the Free Software Foundation; ////
# // either version 2.1 of the License, or (at your option) any ////
# // later version. ////
# // ////
# // This source is distributed in the hope that it will be ////
# // useful, but WITHOUT ANY WARRANTY; without even the implied ////
# // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
# // PURPOSE. See the GNU Lesser General Public License for more ////
# // details. ////
# // ////
# // You should have received a copy of the GNU Lesser General ////
# // Public License along with this source; if not, download it ////
# // from http://www.opencores.org/lgpl.shtml ////
# // ////
# ////////////////////////////////////////////////////////////////////
import sys
# import sv_video
import numpy as np
# import matplotlib.pyplot as plt
 
print("^^^ | py_raw_to_frame |")
print('Number of arguments:', len(sys.argv), 'arguments.')
print('Argument List:', str(sys.argv))
 
# dataSend = np.arange(1, 9 + 1, dtype=np.uint32)
 
# tiny_frame = np.arange(32, 32 + 32, dtype=np.uint32)
# data_list = tiny_frame.flatten()
# data_list = tiny_frame.tolist()
 
# sv_video.py_list_to_c_array(data_list)
 
# ---------------------------------------------------------
v_frames = 1
v_width = 8
v_height = 16
 
# # fname = sys.argv[0]
# fname = 'count.raw'
# print("file name: ", fname)
 
# with open(fname, 'r') as infile:
# data = np.fromfile(infile, dtype='uint16').reshape(v_frames, v_height, v_width)
 
# np.set_printoptions(formatter={'int':hex})
 
# for i in range(v_frames):
# print(data[i])
# fig, ax = plt.subplots()
# im = ax.imshow(data[i], cmap='gray')
# ax.set(xticks=[], yticks=[])
# fig.colorbar(im)
# plt.show()
 
# from __future__ import print_function
# with open('out.txt', 'w') as f:
# print('qqq\n', file=f)
# print(data[0], file=f)
# f = open('out.txt','w')
# print >>f,'some Text'
# print >>f, data[0].flatten()
# for i in range(v_frames*v_height*v_width):
# print >>f, data[0].flatten()[i]
 
# data = np.arange(v_frames*v_width*v_height, dtype='uint16')
# data = data.reshape(v_frames, v_height, v_width)
 
# f = open('count.raw','r')
data = np.fromfile('count.raw', dtype='uint16')
 
print(data)
print(data.shape)
# with open('init_test.do') as fp:
# for line in fp:
# print line
/qaz_libs/trunk/BFM/src/axis_video_frame/axis_video_frame_bfm_pkg.sv
0,0 → 1,617
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axis_video_frame_bfm_pkg;
 
typedef enum
{
RIGHT_DOWN,
RIGHT_UP,
LEFT_DOWN,
LEFT_UP
} avf_direction_t;
 
typedef struct
{
avf_direction_t direction;
int delay = 0;
} avf_tile_config_t;
 
// --------------------------------------------------------------------
//
import q_pkg::*;
import video_frame_pkg::*;
 
 
// --------------------------------------------------------------------
//
class avf_config_class;
 
int width;
int height;
int bytes_per_pixel;
int bits_per_pixel;
int pixels_per_clk;
string name;
int vertical_blanking;
 
avf_tile_config_t tile[];
 
 
//--------------------------------------------------------------------
function
new
(
int width,
int height,
int bytes_per_pixel,
int bits_per_pixel,
int pixels_per_clk,
string name,
int vertical_blanking,
avf_tile_config_t tile[]
);
 
this.width = width;
this.height = height;
this.bytes_per_pixel = bytes_per_pixel;
this.bits_per_pixel = bits_per_pixel;
this.pixels_per_clk = pixels_per_clk;
this.name = name;
this.vertical_blanking = vertical_blanking;
this.tile = tile;
 
$display("^^^ %16.t | %m", $time);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
task automatic
avf_direction
(
input avf_direction_t direction,
output frame_coordinate_t inc
);
 
case(direction)
RIGHT_DOWN: inc = '{ 1, 1};
RIGHT_UP: inc = '{ 1, -1};
LEFT_DOWN: inc = '{-1, 1};
LEFT_UP: inc = '{-1, -1};
default: $display("^^^ %16.t | %m | ERROR!!! Incorrect AVF direction.", $time );
endcase
 
endtask: avf_direction
 
 
// --------------------------------------------------------------------
//
task automatic
avf_calculate
(
input avf_direction_t direction,
output frame_coordinate_t start,
output frame_coordinate_t inc,
output int x_end,
output int y_end,
output int x_eol
);
 
case(direction)
RIGHT_DOWN: start = '{0 , 0 };
RIGHT_UP: start = '{0 , height - 1 };
LEFT_DOWN: start = '{width - 1 , 0 };
LEFT_UP: start = '{width - 1 , height - 1 };
default: $display("^^^ %16.t | %m | [%04d, %04d] | ERROR!!! Incorrect AVF direction.", $time, start.x, start.y );
endcase
 
avf_direction(direction, inc);
 
x_end = (start.x + (width * inc.x));
y_end = (start.y + (height * inc.y));
 
inc.x *= pixels_per_clk; // increment stride by number of outputs
x_eol = x_end - inc.x;
 
endtask: avf_calculate
 
endclass: avf_config_class
 
 
//--------------------------------------------------------------------
//
class avf_tx_bfm_class #(BYTES_PER_PIXEL, PIXELS_PER_CLK, AVF_U)
extends blocking_transmission_q_class #(video_frame_class);
 
localparam AVF_N = BYTES_PER_PIXEL * PIXELS_PER_CLK; // data bus width in bytes
localparam AVF_B = BYTES_PER_PIXEL * 8; // bits per pixel on TDATA
 
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_if;
 
string avf_name = "";
string avf_type = "";
 
avf_config_class c_h;
avf_tile_config_t tile;
video_frame_class f_h;
 
// --------------------------------------------------------------------
//
function void axis_default;
 
avf_axis_if.cb_m.tvalid <= 0;
avf_axis_if.cb_m.tdata <= 'hx;
avf_axis_if.cb_m.tlast <= 'hx;
avf_axis_if.cb_m.tuser <= 'hx;
 
endfunction: axis_default
 
 
// --------------------------------------------------------------------
//
task automatic
output_pixels(input int l, input int p);
 
for(int i = 0; i < PIXELS_PER_CLK; i++)
avf_axis_if.cb_m.tdata[i*AVF_B +: AVF_B] <= f_h.lines[l].pixel[p + i];
 
endtask: output_pixels
 
 
// --------------------------------------------------------------------
//
task automatic
avf_tx(input avf_direction_t direction, input int unsigned avf_delay);
 
frame_coordinate_t start;
frame_coordinate_t inc;
int x_end;
int y_end;
int x_eol;
int pixel_count = 0;
int l;
int p;
 
c_h.avf_calculate
(
.start(start),
.direction(direction),
.inc(inc),
.x_end(x_end),
.y_end(y_end),
.x_eol(x_eol)
);
 
@(avf_axis_if.cb_m);
 
repeat(avf_delay) @(avf_axis_if.cb_m);
 
avf_axis_if.cb_m.tvalid <= 1; // assert first pixel
avf_axis_if.cb_m.tuser[0] <= 1;
avf_axis_if.cb_m.tuser[1] <= 1;
avf_axis_if.cb_m.tuser[2] <= 0;
avf_axis_if.cb_m.tlast <= 0;
 
output_pixels(start.y, start.x);
 
for(l = start.y; y_end != l; l = l + inc.y)
for(p = start.x; x_end != p; p = p + inc.x)
begin
 
if((l == start.y) & (p == start.x)) // first pixel already asserted
continue;
 
@(avf_axis_if.cb_m iff avf_axis_if.cb_m.tready)
begin
avf_axis_if.cb_m.tvalid <= 1;
output_pixels(l, p);
 
avf_axis_if.cb_m.tuser[0] <= 0;
 
if(p == start.x)
avf_axis_if.cb_m.tuser[1] <= 1;
else
avf_axis_if.cb_m.tuser[1] <= 0;
 
if(p == x_eol)
avf_axis_if.cb_m.tlast <= 1;
else
avf_axis_if.cb_m.tlast <= 0;
 
if((l == y_end - 1) && (p == x_eol))
avf_axis_if.cb_m.tuser[2] <= 1;
end
end
 
@(avf_axis_if.cb_m);
wait(avf_axis_if.cb_m.tready);
axis_default();
 
endtask: avf_tx
 
 
// --------------------------------------------------------------------
//
task
avf_fork_tx;
 
fork
avf_tx(tile.direction, tile.delay);
join_none
 
#0;
 
endtask: avf_fork_tx
 
 
// --------------------------------------------------------------------
//
event tx_frame_done;
 
task automatic
transmit(ref Q_T tr_h);
 
f_h = tr_h;
 
avf_fork_tx();
wait fork;
 
repeat(c_h.vertical_blanking) @(avf_axis_if.cb_m);
->tx_frame_done;
 
endtask: transmit
 
 
//--------------------------------------------------------------------
//
function
new
(
int index,
avf_config_class c_h,
input string avf_type,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_if
);
 
super.new();
 
this.avf_axis_if = avf_axis_if;
 
this.c_h = c_h;
this.tile = c_h.tile[index];
this.avf_name = $sformatf("%s%0d", c_h.name, index);
this.avf_type = avf_type.toupper();
 
f_h = new();
 
f_h.init
(
.pixels_per_line(c_h.width),
.lines_per_frame(c_h.height),
.bits_per_pixel(c_h.bits_per_pixel),
.name(avf_name)
);
 
axis_default();
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: avf_tx_bfm_class
 
 
//--------------------------------------------------------------------
//
class avf_rx_bfm_class #(BYTES_PER_PIXEL, PIXELS_PER_CLK, AVF_U)
extends blocking_receiver_q_class #(video_frame_class);
 
localparam AVF_N = BYTES_PER_PIXEL * PIXELS_PER_CLK; // data bus width in bytes
localparam AVF_B = BYTES_PER_PIXEL * 8; // bits per pixel on TDATA
 
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_if;
 
string avf_name = "";
string avf_type = "";
 
avf_config_class c_h;
avf_tile_config_t tile;
video_frame_class f_h;
 
// --------------------------------------------------------------------
//
function void axis_default;
 
avf_axis_if.cb_s.tready <= 1;
 
endfunction: axis_default
 
 
// --------------------------------------------------------------------
//
task automatic
set_tready(input tready);
 
avf_axis_if.cb_s.tready <= tready;
 
endtask: set_tready
 
 
// --------------------------------------------------------------------
//
task automatic
avf_rx(input avf_direction_t direction);
 
frame_coordinate_t start;
frame_coordinate_t inc;
int x_end;
int y_end;
int x_eol;
int pixel_count = 0;
int l;
int p;
 
c_h.avf_calculate
(
.start(start),
.direction(direction),
.inc(inc),
.x_end(x_end),
.y_end(y_end),
.x_eol(x_eol)
);
 
wait(avf_axis_if.cb_s.tuser[0] & avf_axis_if.cb_s.tvalid & avf_axis_if.cb_m.tready);
 
for(l = start.y; y_end != l; l = l + inc.y)
for(p = start.x; x_end != p; p = p + inc.x)
begin
 
wait(avf_axis_if.cb_s.tvalid & avf_axis_if.cb_m.tready);
 
for(int i = 0; i < PIXELS_PER_CLK; i++)
f_h.lines[l].pixel[p + i] = avf_axis_if.cb_s.tdata[i*AVF_B +: AVF_B];
 
if(p == x_eol)
if(~avf_axis_if.cb_s.tlast)
$display("^^^ %16.t | %m | [%04d, %04d] | %s_%s | ERROR! x_eol without tlast | x_eol = %04d | 0x%06x", $time, p, l, avf_name, avf_type, x_eol, f_h.lines[l].pixel[p]);
 
if(avf_axis_if.cb_s.tlast)
if(p != x_eol)
$display("^^^ %16.t | %m | [%04d, %04d] | %s_%s | ERROR! tlast without x_eol | x_eol = %04d | 0x%06x", $time, p, l, avf_name, avf_type, x_eol, f_h.lines[l].pixel[p]);
 
@(avf_axis_if.cb_s);
 
end
 
endtask: avf_rx
 
 
// --------------------------------------------------------------------
//
task automatic
avf_fork_rx;
 
fork
avf_rx(tile.direction);
join_none
 
#0;
 
endtask: avf_fork_rx
 
 
// --------------------------------------------------------------------
//
event rx_frame_done;
 
virtual task
receive(ref Q_T tr_h);
 
avf_fork_rx();
wait fork;
 
tr_h = f_h.clone();
->rx_frame_done;
 
endtask: receive
 
 
//--------------------------------------------------------------------
//
function
new
(
int index,
avf_config_class c_h,
input string avf_type,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_if
);
 
super.new();
 
this.avf_axis_if = avf_axis_if;
 
this.c_h = c_h;
this.tile = c_h.tile[index];
this.avf_name = $sformatf("%s%0d", c_h.name, index);
this.avf_type = avf_type.toupper();
 
f_h = new();
 
f_h.init
(
.pixels_per_line(c_h.width),
.lines_per_frame(c_h.height),
.bits_per_pixel(c_h.bits_per_pixel),
.name(avf_name)
);
 
axis_default();
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: avf_rx_bfm_class
 
// --------------------------------------------------------------------
//
class avf_tx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U);
 
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes
localparam AVF_B = BYTES_PER_PIXEL * 8; // bits per pixel on TDATA
 
int number_of_tx_tiles;
 
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if[];
 
avf_tx_bfm_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) tx_bfm_h[];
 
video_frame_class clone_h;
 
 
// --------------------------------------------------------------------
//
virtual task automatic
make_frame
(
string pattern,
int pixel = 0
);
 
case(pattern.tolower)
"constant": foreach(tx_bfm_h[i]) tx_bfm_h[i].f_h.make_constant(pixel);
"counting": foreach(tx_bfm_h[i]) tx_bfm_h[i].f_h.make_counting();
"horizontal": foreach(tx_bfm_h[i]) tx_bfm_h[i].f_h.make_horizontal();
"vertical": foreach(tx_bfm_h[i]) tx_bfm_h[i].f_h.make_vertical();
"random": foreach(tx_bfm_h[i]) tx_bfm_h[i].f_h.make_random();
default: $display("^^^ %16.t | %m | ERROR! %s pattern not supported", $time, pattern);
endcase
 
endtask: make_frame
 
 
// --------------------------------------------------------------------
//
virtual task
wait_for_tx_frames
(
input int unsigned count
);
 
repeat(count)
@(tx_bfm_h[0].tx_frame_done);
 
endtask: wait_for_tx_frames
 
 
//--------------------------------------------------------------------
//
function new
(
avf_config_class c_h,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if[]
);
 
this.number_of_tx_tiles = $size(avf_axis_out_if);
this.avf_axis_out_if = avf_axis_out_if;
 
this.tx_bfm_h = new[number_of_tx_tiles];
foreach(tx_bfm_h[i])
tx_bfm_h[i] = new(i, c_h, "TX", avf_axis_out_if[i]);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: avf_tx_class
 
 
// --------------------------------------------------------------------
//
class avf_rx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U);
 
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes
localparam AVF_B = BYTES_PER_PIXEL * 8; // bits per pixel on TDATA
 
int number_of_rx_tiles;
 
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_in_if[];
 
avf_rx_bfm_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) rx_bfm_h[];
 
video_frame_class clone_h;
 
 
// --------------------------------------------------------------------
//
virtual task
wait_for_rx_frames
(
input int unsigned count
);
 
repeat(count)
@(rx_bfm_h[0].rx_frame_done);
 
endtask: wait_for_rx_frames
 
 
//--------------------------------------------------------------------
//
function new
(
avf_config_class c_h,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_in_if[]
);
 
this.number_of_rx_tiles = $size(avf_axis_in_if);
this.avf_axis_in_if = avf_axis_in_if;
 
this.rx_bfm_h = new[number_of_rx_tiles];
foreach(rx_bfm_h[i])
rx_bfm_h[i] = new(i, c_h, "RX", avf_axis_in_if[i]);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: avf_rx_class
 
 
// --------------------------------------------------------------------
//
endpackage: axis_video_frame_bfm_pkg
 
/qaz_libs/trunk/BFM/src/axis_video_frame/avf_agent_class_pkg.sv
0,0 → 1,166
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package avf_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import video_frame_pkg::*;
import axis_video_frame_bfm_pkg::*;
 
 
// --------------------------------------------------------------------
//
class avf_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE = 1, AVF_U = 3);
 
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes
localparam AVF_B = BYTES_PER_PIXEL * 8; // bits per pixel on TDATA
 
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_in_if[];
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if[];
 
avf_config_class c_h;
 
avf_tx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) tx_h;
avf_rx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) rx_h;
 
video_frame_class clone_h;
video_frame_class sent_f_h;
video_frame_class rx_f_h;
 
mailbox #(video_frame_class) q[];
 
 
// --------------------------------------------------------------------
//
virtual task
queue_frame
(
string pattern = "",
int pixel = 0
);
 
if(pattern != "")
tx_h.make_frame(pattern, pixel);
 
foreach(tx_h.tx_bfm_h[i])
begin
clone_h = tx_h.tx_bfm_h[i].f_h.clone();
tx_h.tx_bfm_h[i].put(clone_h);
q[i].put(clone_h);
end
 
$display("^^^ %16.t | %m | using %s pattern", $time, pattern);
 
endtask: queue_frame
 
 
// --------------------------------------------------------------------
//
virtual task automatic
compare_frame;
 
int mismatch_count;
 
$display("^^^ %16.t | %m", $time);
 
foreach(rx_h.rx_bfm_h[i])
begin
q[i].get(sent_f_h);
rx_h.rx_bfm_h[i].get(rx_f_h);
mismatch_count = sent_f_h.compare(8, rx_f_h);
end
 
endtask: compare_frame
 
 
// --------------------------------------------------------------------
//
virtual task set_tready(input tready);
$display("^^^ %16.t | %m", $time);
foreach(rx_h.rx_bfm_h[i])
rx_h.rx_bfm_h[i].set_tready(tready);
endtask: set_tready
 
 
// --------------------------------------------------------------------
//
virtual task flush_sent_frame;
$display("^^^ %16.t | %m", $time);
foreach(rx_h.rx_bfm_h[i])
q[i].get(sent_f_h);
endtask: flush_sent_frame
 
 
// --------------------------------------------------------------------
//
virtual task rx_flush_frame;
$display("^^^ %16.t | %m", $time);
foreach(rx_h.rx_bfm_h[i])
rx_h.rx_bfm_h[i].get(rx_f_h);
endtask: rx_flush_frame
 
 
//--------------------------------------------------------------------
//
function void init(avf_config_class c_h);
 
rx_h = new(c_h, avf_axis_in_if);
tx_h = new(c_h, avf_axis_out_if);
 
this.q = new[$size(avf_axis_out_if)];
foreach(q[i])
this.q[i] = new();
 
endfunction: init
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_in_if[],
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if[]
);
 
this.avf_axis_in_if = avf_axis_in_if;
this.avf_axis_out_if = avf_axis_out_if;
endfunction: new
 
 
// --------------------------------------------------------------------
//
 
endclass: avf_agent_class
 
endpackage: avf_agent_class_pkg
 
 
 
 
 
/qaz_libs/trunk/BFM/src/axis_video_frame/avf_agent.sv
0,0 → 1,105
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
import axis_video_frame_bfm_pkg::*;
 
module
avf_agent
#(
BYTES_PER_PIXEL = 2,
AVF_OUTPUTS = 4,
AVF_TILES = 1,
AVF_WIDTH = 32,
AVF_HEIGHT = 16,
AVF_BITS_PER_PIXEL = 16
)
(
axis_if axis_out[AVF_TILES],
axis_if axis_in[AVF_TILES]
);
 
// --------------------------------------------------------------------
//
axis_video_frame_bfm_class #(BYTES_PER_PIXEL, AVF_OUTPUTS) f_tx_h[AVF_TILES];
 
for(genvar j = 0; j < AVF_TILES; j++)
initial
begin
f_tx_h[j] = new(axis_out[j]);
 
f_tx_h[j].init
(
.avf_width(AVF_WIDTH),
.avf_height(AVF_HEIGHT),
.avf_bits_per_pixel(AVF_BITS_PER_PIXEL),
.avf_name($psprintf("AVF_%0d", j)),
.avf_type("TX")
);
end
 
 
// --------------------------------------------------------------------
//
axis_video_frame_bfm_class #(BYTES_PER_PIXEL, AVF_OUTPUTS) f_rx_h[AVF_TILES];
 
for(genvar j = 0; j < AVF_TILES; j++)
initial
begin
f_rx_h[j] = new(axis_in[j]);
 
f_rx_h[j].init
(
.avf_width(AVF_WIDTH),
.avf_height(AVF_HEIGHT),
.avf_bits_per_pixel(AVF_BITS_PER_PIXEL),
.avf_name($psprintf("AVF_%0d", j)),
.avf_type("RX")
);
end
 
 
// --------------------------------------------------------------------
//
avf_tx #(BYTES_PER_PIXEL, AVF_OUTPUTS, AVF_TILES)
avf_tx_bfm(.*);
 
 
// --------------------------------------------------------------------
//
avf_rx #(BYTES_PER_PIXEL, AVF_OUTPUTS, AVF_TILES)
avf_rx_bfm(.*);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
 
 
 
/qaz_libs/trunk/BFM/src/axis_video_frame/avf_rx.sv
0,0 → 1,134
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
import axis_video_frame_bfm_pkg::*;
 
module
avf_rx
#(
BYTES_PER_PIXEL = 2,
AVF_OUTPUTS = 4,
AVF_TILES = 1
)
(
ref axis_video_frame_bfm_class f_tx_h[AVF_TILES],
ref axis_video_frame_bfm_class f_rx_h[AVF_TILES]
);
 
// --------------------------------------------------------------------
//
localparam AVF_VERTICAL_BLANKING = 20;
 
task automatic
init_avf_rx;
 
f_rx_h[0].run_rx_q(RIGHT_DOWN);
f_rx_h[1].run_rx_q(RIGHT_UP);
f_rx_h[2].run_rx_q(LEFT_DOWN);
f_rx_h[3].run_rx_q(LEFT_UP);
 
endtask: init_avf_rx
 
 
// --------------------------------------------------------------------
//
task
wait_for_rx_frames
(
input int unsigned count
);
 
repeat(count)
@(f_rx_h[0].rx_frame_done);
 
endtask: wait_for_rx_frames
 
 
// --------------------------------------------------------------------
//
semaphore get_frame_semaphore = new(1);
logic get_frame_active = 0;
 
task automatic
get_frame;
 
if(get_frame_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Already getting a frame.", $time);
return;
end
 
$display("^^^ %16.t | %m | getting a frame.", $time);
get_frame_active = 1;
 
fork
begin
 
f_rx_h[0].avf_fork_rx(RIGHT_DOWN);
f_rx_h[1].avf_fork_rx(RIGHT_UP);
f_rx_h[2].avf_fork_rx(LEFT_DOWN);
f_rx_h[3].avf_fork_rx(LEFT_UP);
 
wait fork;
get_frame_active = 0;
$display("^^^ %16.t | %m | Got a frame.", $time);
get_frame_semaphore.put();
 
end
join_none
 
 
endtask: get_frame
 
 
// --------------------------------------------------------------------
//
import video_frame_pkg::*;
 
function automatic
int compare_frame;
 
int mismatch_count[AVF_TILES];
 
$display("^^^ %16.t | %m", $time);
 
foreach(f_rx_h[i])
mismatch_count[i] = f_rx_h[i].f_h.compare(8, f_tx_h[i].f_h);
 
 
endfunction: compare_frame
 
 
// --------------------------------------------------------------------
//
 
 
endmodule
 
 
 
 
/qaz_libs/trunk/BFM/src/axis_video_frame/avf_tx.sv
0,0 → 1,171
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
import axis_video_frame_bfm_pkg::*;
 
module
avf_tx
#(
BYTES_PER_PIXEL = 2,
AVF_OUTPUTS = 4,
AVF_TILES = 1
)
(
ref axis_video_frame_bfm_class f_tx_h[AVF_TILES],
ref axis_video_frame_bfm_class f_rx_h[AVF_TILES]
);
 
// --------------------------------------------------------------------
//
localparam AVF_VERTICAL_BLANKING = 20;
 
task automatic
init_avf_tx;
 
foreach(f_tx_h[i])
f_tx_h[i].avf_vertical_blanking = AVF_VERTICAL_BLANKING;
 
f_tx_h[0].run_tx_q(RIGHT_DOWN, 0);
f_tx_h[1].run_tx_q(RIGHT_UP, 0);
f_tx_h[2].run_tx_q(LEFT_DOWN, 0);
f_tx_h[3].run_tx_q(LEFT_UP, 0);
 
endtask: init_avf_tx
 
 
// --------------------------------------------------------------------
//
import video_frame_pkg::*;
 
video_frame_class clone_h;
 
 
// --------------------------------------------------------------------
//
task automatic
make_frame
(
string pattern,
int pixel = 0
);
 
case(pattern.tolower)
"constant": foreach(f_tx_h[i]) f_tx_h[i].f_h.make_constant(pixel);
"counting": foreach(f_tx_h[i]) f_tx_h[i].f_h.make_counting();
"horizontal": foreach(f_tx_h[i]) f_tx_h[i].f_h.make_horizontal();
"vertical": foreach(f_tx_h[i]) f_tx_h[i].f_h.make_vertical();
"random": foreach(f_tx_h[i]) f_tx_h[i].f_h.make_random();
default: $display("^^^ %16.t | %m | ERROR! %s pattern not supported", $time, pattern);
endcase
 
endtask: make_frame
 
 
// --------------------------------------------------------------------
//
 
task automatic
queue_frame
(
string pattern = ""
);
 
if(pattern != "")
make_frame(pattern);
 
foreach(f_tx_h[i])
begin
clone_h = f_tx_h[i].f_h.clone();
f_tx_h[i].avf_q.put(clone_h);
f_rx_h[i].avf_q.put(clone_h);
end
 
$display("^^^ %16.t | %m | using %s pattern", $time, pattern);
 
endtask: queue_frame
 
 
// --------------------------------------------------------------------
//
task
wait_for_tx_frames
(
input int unsigned count
);
 
repeat(count)
@(f_tx_h[0].tx_frame_done);
 
endtask: wait_for_tx_frames
 
 
// --------------------------------------------------------------------
//
logic put_frame_active = 0;
semaphore put_frame_semaphore = new(1);
 
task automatic
put_frame;
 
if(put_frame_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Already put a frame.", $time);
return;
end
 
$display("^^^ %16.t | %m | Putting a frame.", $time);
put_frame_active = 1;
 
fork
begin
 
f_tx_h[0].avf_fork_tx(RIGHT_DOWN, 0);
f_tx_h[1].avf_fork_tx(RIGHT_UP, 0);
f_tx_h[2].avf_fork_tx(LEFT_DOWN, 0);
f_tx_h[3].avf_fork_tx(LEFT_UP, 0);
 
wait fork;
put_frame_active = 0;
$display("^^^ %16.t | %m | Put a frame.", $time);
put_frame_semaphore.put();
 
end
join_none
 
endtask: put_frame
 
 
// --------------------------------------------------------------------
//
 
 
endmodule
 
 
 
 
/qaz_libs/trunk/BFM/src/video_frame/video_frame_class.svh
27,6 → 27,7
 
// --------------------------------------------------------------------
class video_frame_class;
logger_class log;
rand int frame_id;
rand int pixels_per_line;
rand int lines_per_frame;
58,6 → 59,7
 
//--------------------------------------------------------------------
function new;
this.log = new;
this.frame_id = 0;
endfunction: new
 
70,6 → 72,7
int pixels_per_clk = 1,
string name = ""
);
log.info($sformatf("%m"));
this.pixels_per_line = pixels_per_line;
this.lines_per_frame = lines_per_frame;
this.bits_per_pixel = bits_per_pixel;
110,6 → 113,7
 
// --------------------------------------------------------------------
function void make_constant(int pixel);
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
125,6 → 129,7
 
// --------------------------------------------------------------------
function void make_counting(int offset = 0);
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
140,6 → 145,7
 
// --------------------------------------------------------------------
function void make_horizontal();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
155,6 → 161,7
 
// --------------------------------------------------------------------
function void make_vertical();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
170,6 → 177,7
 
// --------------------------------------------------------------------
function void make_random();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
185,6 → 193,7
 
// --------------------------------------------------------------------
function void copy(video_frame_class from);
log.info($sformatf("%m"));
this.frame_id = from.frame_id;
this.pixels_per_line = from.pixels_per_line;
this.lines_per_frame = from.lines_per_frame;
203,6 → 212,7
 
// --------------------------------------------------------------------
virtual function video_frame_class clone;
log.info($sformatf("%m"));
clone = new();
clone.copy(this);
endfunction: clone
209,6 → 219,7
 
// --------------------------------------------------------------------
function video_frame_class catenate_horizontally(video_frame_class tail);
log.info($sformatf("%m"));
 
if(this.lines_per_frame != tail.lines_per_frame)
return(null);
237,6 → 248,7
 
// --------------------------------------------------------------------
function void shift_right(ref line_s column);
log.info($sformatf("%m"));
 
foreach(this.lines[l])
for(int p = pixels_per_line - 1; p > 0; p--)
246,127 → 258,114
this.lines[l].pixel[0] = column.pixel[l];
endfunction: shift_right
 
// // --------------------------------------------------------------------
// function int compare_line
// ( int line
// , int max_mismatches
// , video_frame_class to
// );
// int mismatch_count = 0;
// --------------------------------------------------------------------
function int compare_line
( int line
, int max_mismatches
, video_frame_class to
);
int mismatch_count = 0;
 
// if(to.bits_per_pixel != this.bits_per_pixel)
// begin
// log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
// return(-3);
// end
if(to.bits_per_pixel != this.bits_per_pixel)
begin
log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
return(-3);
end
 
// foreach(this.lines[line].pixel[p])
// if(to.lines[line].pixel[p] != this.lines[line].pixel[p])
// begin
foreach(this.lines[line].pixel[p])
if(to.lines[line].pixel[p] != this.lines[line].pixel[p])
begin
 
// if(max_mismatches > 0)
// mismatch_count++;
if(max_mismatches > 0)
mismatch_count++;
 
// log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s",
// line, p, to.lines[line].pixel[p], this.lines[line].pixel[p], name));
log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s",
line, p, to.lines[line].pixel[p], this.lines[line].pixel[p], name));
 
// if(mismatch_count > max_mismatches)
// return(mismatch_count);
// end
if(mismatch_count > max_mismatches)
return(mismatch_count);
end
 
// return(mismatch_count);
// endfunction: compare_line
return(mismatch_count);
endfunction: compare_line
 
// // --------------------------------------------------------------------
// function int compare(int max_mismatches, video_frame_class to);
// int mismatch_count = 0;
// log.info($sformatf("%m"));
// --------------------------------------------------------------------
function int compare(int max_mismatches, video_frame_class to);
int mismatch_count = 0;
log.info($sformatf("%m"));
 
// if(to.pixels_per_line != this.pixels_per_line)
// begin
// log.error($sformatf("to.pixels_per_line != this.pixels_per_line | %s", name));
// return(-1);
// end
if(to.pixels_per_line != this.pixels_per_line)
begin
log.error($sformatf("to.pixels_per_line != this.pixels_per_line | %s", name));
return(-1);
end
 
// if(to.lines_per_frame != this.lines_per_frame)
// begin
// log.error($sformatf("to.lines_per_frame != this.lines_per_frame | %s", name));
// return(-2);
// end
if(to.lines_per_frame != this.lines_per_frame)
begin
log.error($sformatf("to.lines_per_frame != this.lines_per_frame | %s", name));
return(-2);
end
 
// if(to.bits_per_pixel != this.bits_per_pixel)
// begin
// log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
// return(-3);
// end
if(to.bits_per_pixel != this.bits_per_pixel)
begin
log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
return(-3);
end
 
// foreach(this.lines[l])
// begin
// foreach(this.lines[l].pixel[p])
// if(to.lines[l].pixel[p] != this.lines[l].pixel[p])
// begin
// if(max_mismatches > 0)
// mismatch_count++;
foreach(this.lines[l])
begin
foreach(this.lines[l].pixel[p])
if(to.lines[l].pixel[p] != this.lines[l].pixel[p])
begin
if(max_mismatches > 0)
mismatch_count++;
 
// log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s", l, p, to.lines[l].pixel[p], this.lines[l].pixel[p], name));
log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s", l, p, to.lines[l].pixel[p], this.lines[l].pixel[p], name));
 
// if(mismatch_count > max_mismatches)
// return(mismatch_count);
// end
// end
if(mismatch_count > max_mismatches)
return(mismatch_count);
end
end
 
// return(mismatch_count);
// endfunction: compare
return(mismatch_count);
endfunction: compare
 
// // --------------------------------------------------------------------
// function void print_line(int line, int pixel, int count);
// log.info($sformatf("%m"));
// --------------------------------------------------------------------
function void print_line(int line, int pixel, int count);
log.info($sformatf("%m"));
 
// for(int i = 0; i < count; i++)
// log.display($sformatf("%4h @ frame[%4h][%4h] | %s", this.lines[line].pixel[(pixel + i)], line, (pixel + i), name));
// endfunction: print_line
for(int i = 0; i < count; i++)
log.display($sformatf("%4h @ frame[%4h][%4h] | %s", this.lines[line].pixel[(pixel + i)], line, (pixel + i), name));
endfunction: print_line
 
// // --------------------------------------------------------------------
// function void print_config();
// log.display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
// log.display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
// log.display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
// log.display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
// log.display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
// log.display($sformatf("%m | pattern = %s | %s", pattern, name));
// endfunction: print_config
 
// --------------------------------------------------------------------
function void print_config();
$display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
$display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
$display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
$display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
$display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
$display($sformatf("%m | pattern = %s | %s", pattern, name));
log.display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
log.display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
log.display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
log.display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
log.display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
log.display($sformatf("%m | pattern = %s | %s", pattern, name));
endfunction: print_config
 
// --------------------------------------------------------------------
function string convert2string(int grid=8);
string s0, s1;
string s;
string f ="";
int nibbles = ( bits_per_pixel % 4 == 0)
? bits_per_pixel / 4
: (bits_per_pixel / 4) + 1;
string fs = $sformatf("%%s%%%0d.h" , (bits_per_pixel % 4 == 0)
? bits_per_pixel / 4
: (bits_per_pixel / 4) + 1
);
foreach(this.lines[l])
begin
s = $sformatf("[%4.d]", l);
foreach(this.lines[l].pixel[p])
s = {s, $sformatf(fs, (p % grid == 0) ? "!" : "|", this.lines[l].pixel[p])};
 
foreach(this.lines[l]) begin
s0 = $sformatf("[%4.d]", l);
foreach(this.lines[l].pixel[p]) begin
s1 = $sformatf("%.h", this.lines[l].pixel[p]);
s1 = s1.substr(nibbles, s1.len()-1);
s0 = {s0, (p % grid == 0) ? "!" : "|", s1};
end
 
f = {f, s0, "|\n"};
f = {f, s, "|\n"};
end
 
return f;
endfunction: convert2string
 
// --------------------------------------------------------------------
endclass
endclass: video_frame_class
/qaz_libs/trunk/BFM/src/video_frame/video_frame_config.svh
57,4 → 57,4
endfunction : init
 
// --------------------------------------------------------------------
endclass
endclass: video_frame_config
/qaz_libs/trunk/BFM/src/video_frame/video_frame_pkg.sv
26,6 → 26,7
//////////////////////////////////////////////////////////////////////
 
package video_frame_pkg;
import logger_pkg::*;
 
// --------------------------------------------------------------------
typedef struct
49,4 → 50,4
`include "video_frame_class.svh"
 
// --------------------------------------------------------------------
endpackage
endpackage: video_frame_pkg
/qaz_libs/trunk/BFM/src/SPI/spi_driver.svh
25,17 → 25,17
//// ////
//////////////////////////////////////////////////////////////////////
 
class spi_driver #(N)
class spi_driver
extends uvm_driver #(spi_sequence_item);
`uvm_component_param_utils(spi_driver #(N))
`uvm_component_utils(spi_driver)
 
// --------------------------------------------------------------------
virtual spi_if #(N) vif;
virtual spi_if vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.sclk <= 0;
vif.ss_n <= '1;
vif.ss_n <= 1;
vif.mosi <= 'x;
endfunction: set_default
 
51,8 → 51,7
index = 0;
seq_item_port.get_next_item(item);
 
vif.ss_n <= ~(1 << item.ss_index);
 
vif.ss_n <= 0;
vif.mosi <= item.mosi_data[index];
#(vif.period / 2);
 
76,7 → 75,7
end
 
#(vif.period / 2);
vif.ss_n <= '1;
vif.ss_n <= 1;
 
set_default();
seq_item_port.item_done();
90,4 → 89,4
endfunction
 
// --------------------------------------------------------------------
endclass
endclass : spi_driver
/qaz_libs/trunk/BFM/src/SPI/spi_sequence_item.svh
35,7 → 35,6
// --------------------------------------------------------------------
logic miso_data[]; // data from slave to master
logic mosi_data[]; // data from master to slave
int ss_index = 0;
bit read;
bit write;
 
57,34 → 56,38
mosi_data[i] = 0;
endfunction : init
 
// --------------------------------------------------------------------
function void load_mosi_from_file(string file_name);
byte buffer;
integer fd;
integer code;
integer size;
// // --------------------------------------------------------------------
// function bit do_compare(uvm_object rhs, uvm_comparer comparer);
// spi_sequence_item tested;
// bit same;
 
fd = $fopen(file_name, "rb");
code = $fseek(fd, 0, 2); // SEEK_END
size = $ftell(fd);
code = $rewind(fd);
data_width = size*8;
mosi_data = new[data_width];
write = 1;
// if (rhs==null)
// `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer");
 
for(int i = 0; i < size; i++) begin
code = $fread(buffer, fd);
mosi_data[i*8 +: 8] = {>>{buffer}};
end
// if (!$cast(tested,rhs))
// same = 0;
// else
// same = super.do_compare(rhs, comparer);
 
$fclose(fd);
endfunction
// return same;
// endfunction : do_compare
 
// --------------------------------------------------------------------
function void load_mosi_from_byte_array(byte byte_array[]);
foreach(byte_array[i])
mosi_data[i*8 +: 8] = {>>{byte_array[i]}};
endfunction
// // --------------------------------------------------------------------
// function void do_copy(uvm_object rhs);
// spi_sequence_item item;
// assert(rhs != null) else
// `uvm_fatal(get_type_name(), "| %m | copy null transaction");
// super.do_copy(rhs);
// assert($cast(item,rhs)) else
// `uvm_fatal(get_type_name(), "| %m | failed cast");
// delay = item.delay;
// command = item.command;
// wr_full = item.wr_full;
// rd_empty = item.rd_empty;
// wr_data = item.wr_data;
// rd_data = item.rd_data;
// count = item.count;
// endfunction : do_copy
 
// --------------------------------------------------------------------
function string convert2string();
99,7 → 102,8
);
s0 = {s0, s1};
 
if(read) begin
if(read)
begin
data = {>>{miso_data}};
 
foreach(data[i])
109,7 → 113,8
s0 = {s0, s2};
end
 
if(write) begin
if(write)
begin
data = {>>{mosi_data}};
 
foreach(data[i])
123,4 → 128,4
endfunction : convert2string
 
// --------------------------------------------------------------------
endclass
endclass : spi_sequence_item
/qaz_libs/trunk/BFM/src/SPI/spi_agent.svh
25,24 → 25,32
//// ////
//////////////////////////////////////////////////////////////////////
 
class spi_agent #(N=1)
class spi_agent
extends uvm_agent;
`uvm_component_param_utils(spi_agent #(N))
`uvm_component_utils(spi_agent)
 
// --------------------------------------------------------------------
virtual spi_if #(N) vif;
spi_driver #(N) driver_h;
virtual spi_if vif;
spi_driver driver_h;
spi_sequencer sequencer_h;
// spi_monitor monitor_h;
 
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
driver_h = spi_driver #(N)::type_id::create("driver_h", this);
// super.build_phase(phase);
driver_h = spi_driver::type_id::create("driver_h", this);
// monitor_h = spi_monitor ::type_id::create("monitor_h", this);
sequencer_h = spi_sequencer::type_id::create("sequencer_h", this);
 
endfunction
 
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
// super.connect_phase(phase);
 
driver_h.vif = vif;
// monitor_h.vif = vif;
 
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
 
52,4 → 60,4
endfunction
 
// --------------------------------------------------------------------
endclass
endclass : spi_agent
/qaz_libs/trunk/BFM/src/SPI/spi_if.sv
25,7 → 25,8
//// ////
//////////////////////////////////////////////////////////////////////
 
interface spi_if #(N=1);
interface
spi_if();
import uvm_pkg::*;
`include "uvm_macros.svh"
import tb_spi_pkg::*;
32,7 → 33,7
 
// --------------------------------------------------------------------
logic sclk;
logic [N-1:0] ss_n;
logic ss_n;
logic mosi;
logic miso;
 
/qaz_libs/trunk/BFM/src/SPI/tb_spi_pkg.sv
28,12 → 28,28
package tb_spi_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import bfm_pkg::*;
 
// // --------------------------------------------------------------------
// localparam W = 16;
// localparam D = 8;
// localparam UB = $clog2(D);
 
// --------------------------------------------------------------------
// typedef enum {FIFO_RD, FIFO_WR, FIFO_BOTH, FIFO_NULL} fifo_command_t;
 
// --------------------------------------------------------------------
`include "spi_sequence_item.svh"
typedef uvm_sequencer #(spi_sequence_item) spi_sequencer;
`include "spi_driver.svh"
// `include "spi_monitor.svh"
// `include "spi_scoreboard.svh"
`include "spi_agent.svh"
// `include "tb_env.svh"
// `include "s_debug.svh"
// `include "t_top_base.svh"
// `include "t_debug.svh"
 
// --------------------------------------------------------------------
endpackage
endpackage : tb_spi_pkg
/qaz_libs/trunk/BFM/src/tb/legacy/tb_bfm_pkg.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/tb_clk.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/tb_clk_pkg.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/tb_base.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/logger_pkg.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/q_pkg.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/tb_clk_class.sv File deleted
/qaz_libs/trunk/BFM/src/tb/legacy/bfm_pkg.sv File deleted
/qaz_libs/trunk/BFM/src/tb/tb_pkg.sv
31,4 → 31,4
`include "random_delay.svh"
 
// --------------------------------------------------------------------
endpackage
endpackage : tb_pkg
/qaz_libs/trunk/BFM/src/tb/bfm_pkg.sv
0,0 → 1,106
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package bfm_pkg;
 
// --------------------------------------------------------------------
//
typedef enum
{
NONE,
REGULAR
// BURSTY
} traffic_type_e;
 
// --------------------------------------------------------------------
//
class delay_class;
 
rand int unsigned delay = 0;
 
// --------------------------------------------------------------------
//
virtual function void set_delay(traffic_type_e kind = REGULAR);
case(kind)
NONE: delay = 0;
REGULAR: assert(this.randomize() with{delay dist {0 := 60, [1:3] := 30, [4:7] := 10};});
default: delay = 0;
endcase
endfunction: set_delay
 
// --------------------------------------------------------------------
//
virtual function int next(traffic_type_e kind = REGULAR);
set_delay(kind);
return(delay);
endfunction: next
 
// --------------------------------------------------------------------
//
endclass: delay_class
 
// --------------------------------------------------------------------
//
virtual class transaction_class #(parameter type TR_T);
 
delay_class delay_h;
 
// --------------------------------------------------------------------
//
function void random;
assert(this.randomize());
endfunction: random
 
//--------------------------------------------------------------------
//
function new;
delay_h = new();
endfunction: new
 
// --------------------------------------------------------------------
//
pure virtual function void copy(TR_T from);
 
// --------------------------------------------------------------------
//
function automatic TR_T clone;
TR_T child;
clone = new();
$cast(child, this);
clone.copy(child);
return(clone);
endfunction: clone
 
// --------------------------------------------------------------------
//
endclass: transaction_class
 
//--------------------------------------------------------------------
//
endpackage: bfm_pkg
 
/qaz_libs/trunk/BFM/src/tb/logger_pkg.sv
0,0 → 1,136
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package logger_pkg;
 
// --------------------------------------------------------------------
//
typedef enum
{
FATAL,
ERROR,
WARNING,
INFO
} logger_severity_t;
 
 
// --------------------------------------------------------------------
//
class logger_class;
 
logger_severity_t verbosity = WARNING;
bit log_debug = 0;
string time_string;
int error_count = 0;
int max_error_display = 8;
bit stop_at_max_error = 1;
 
// --------------------------------------------------------------------
//
function void
set_verbosity(logger_severity_t level);
verbosity = level;
endfunction: set_verbosity
 
 
// --------------------------------------------------------------------
//
function void
debug_enable;
log_debug = 1;
endfunction: debug_enable
 
 
// --------------------------------------------------------------------
//
function void debug(string message);
time_string = $sformatf("??? %16.t | ", $time);
if(log_debug == 1)
$display({time_string, message});
endfunction: debug
 
 
// --------------------------------------------------------------------
//
function void display(string message);
time_string = $sformatf("--- %16.t | ", $time);
$display({time_string, message});
endfunction: display
 
 
// --------------------------------------------------------------------
//
function void info(string message);
time_string = $sformatf("^^^ %16.t | ", $time);
if(verbosity >= INFO)
$display({time_string, message});
endfunction: info
 
 
// --------------------------------------------------------------------
//
function void warning(string message);
time_string = $sformatf("*** %16.t | ", $time);
if(verbosity >= WARNING)
$display({time_string, message});
endfunction: warning
 
 
// --------------------------------------------------------------------
//
function void error(string message);
time_string = $sformatf("!!! %16.t | ", $time);
error_count++;
if(error_count > max_error_display)
if(stop_at_max_error)
$stop;
else
return;
if(verbosity >= ERROR)
$display({time_string, message});
endfunction: error
 
 
// --------------------------------------------------------------------
//
function void fatal(string message);
if(verbosity >= FATAL)
$fatal(1, message);
endfunction: fatal
 
 
//--------------------------------------------------------------------
//
endclass: logger_class
 
 
//--------------------------------------------------------------------
//
endpackage: logger_pkg
 
/qaz_libs/trunk/BFM/src/tb/q_pkg.sv
0,0 → 1,147
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package q_pkg;
 
// --------------------------------------------------------------------
//
virtual class q_base_class #(parameter type Q_T = logic);
 
Q_T tr_h;
mailbox #(Q_T) q;
 
// --------------------------------------------------------------------
//
pure virtual task run_q;
 
 
// --------------------------------------------------------------------
//
task put(ref Q_T tr_h);
q.put(tr_h);
endtask: put
 
 
// --------------------------------------------------------------------
//
task get(ref Q_T tr_h);
q.get(tr_h);
endtask: get
 
 
//--------------------------------------------------------------------
function new;
this.q = new();
fork
forever
run_q();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: q_base_class
 
 
// --------------------------------------------------------------------
//
virtual class nonblocking_transmission_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task transmit(ref Q_T tr_h);
pure virtual task idle();
 
 
// --------------------------------------------------------------------
//
task automatic run_q;
if(q.try_get(tr_h) != 0)
transmit(tr_h);
else
idle();
endtask: run_q
 
 
// --------------------------------------------------------------------
//
endclass: nonblocking_transmission_q_class
 
 
// --------------------------------------------------------------------
//
virtual class blocking_transmission_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task transmit(ref Q_T tr_h);
 
 
// --------------------------------------------------------------------
//
task run_q;
q.get(tr_h);
transmit(tr_h);
endtask: run_q
 
 
// --------------------------------------------------------------------
//
endclass: blocking_transmission_q_class
 
 
// --------------------------------------------------------------------
//
virtual class blocking_receiver_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task receive(ref Q_T tr_h);
 
 
// --------------------------------------------------------------------
//
task run_q;
receive(tr_h);
q.put(tr_h);
endtask: run_q
 
 
//--------------------------------------------------------------------
//
endclass: blocking_receiver_q_class
 
 
//--------------------------------------------------------------------
//
endpackage: q_pkg
 
/qaz_libs/trunk/BFM/src/tb/tb_base.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
25,62 → 25,82
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
import tb_clk_pkg::*;
 
 
module
tb_base
#(
N = 1,
realtime PERIODS[N],
realtime ASSERT_TIME = (PERIODS[0] * 5) + (PERIODS[0] / 3)
parameter PERIOD = 0,
parameter ASSERT_TIME = 0
)
(
output bit tb_clk[N],
output bit tb_aresetn,
output bit tb_reset[N]
output clock,
output reg reset
);
timeunit 1ns;
timeprecision 100ps;
 
// --------------------------------------------------------------------
function void assert_reset(realtime reset_assert=ASSERT_TIME);
//
task assert_reset
(
input time reset_assert
);
 
reset = 1;
$display( "-#- %16.t | %m | reset asserted!", $time );
 
#reset_assert;
 
reset = 0;
$display( "-#- %16.t | %m | reset deasserted!", $time );
 
endtask
 
 
// --------------------------------------------------------------------
//
task timeout_stop
(
input time timeout
);
 
$display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);
 
fork
begin
tb_aresetn = 0;
#reset_assert;
tb_aresetn = 1;
end
#(timeout) $stop;
join_none
endfunction
 
// --------------------------------------------------------------------
bit disable_clks[N];
endtask
 
generate
for(genvar j = 0; j < N; j++) begin
always
if(disable_clks[j])
tb_clk[j] = 0;
else
#(PERIODS[j]/2) tb_clk[j] = ~tb_clk[j];
end
endgenerate
 
// --------------------------------------------------------------------
generate
for(genvar j = 0; j < N; j++) begin
bit reset = 1;
assign tb_reset[j] = reset;
//
tb_clk_class tb_clk_c;
tb_clk_if tb_clk_driver();
assign clock = tb_clk_driver.clk;
time reset_assert = (PERIOD * 5) + (PERIOD / 3);
logic init_done = 0;
 
always @(posedge tb_clk[j] or negedge tb_aresetn)
if(~tb_aresetn)
reset = 1;
else
reset = 0;
initial
begin
 
reset = 1;
 
tb_clk_c = new( tb_clk_driver );
 
if( PERIOD != 0 )
tb_clk_c.init_basic_clock( PERIOD );
 
if( ASSERT_TIME != 0 )
assert_reset( ASSERT_TIME );
else if( reset_assert != 0 )
assert_reset( reset_assert );
 
init_done = 1;
 
end
endgenerate
endmodule
 
// --------------------------------------------------------------------
initial
assert_reset();
 
// --------------------------------------------------------------------
endmodule
/qaz_libs/trunk/BFM/src/tb/tb_bfm_pkg.sv
0,0 → 1,230
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_bfm_pkg;
 
// --------------------------------------------------------------------
//
class tb_nonblocking_transaction_q_class #(parameter type T = logic);
 
T tr_h;
mailbox #(T) q;
semaphore q_semaphore;
 
//--------------------------------------------------------------------
function new;
 
this.q = new();
this.q_semaphore = new(1);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
event start;
event done;
 
virtual task automatic
transaction
(
ref T tr_h
);
 
->start;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
->done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
virtual task automatic
idle;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
endtask: idle
 
 
// --------------------------------------------------------------------
//
task
put
(
ref T tr_h
);
 
$display("^^^ %16.t | %m | ", $time);
 
q.put(tr_h);
 
endtask: put
 
 
// --------------------------------------------------------------------
//
task automatic
run_q;
 
if(q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Aready active |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
run_q_fork : fork
forever
if(q.try_get(tr_h) != 0)
transaction(tr_h);
else
idle();
join_none
 
#0;
 
endtask: run_q
 
 
// --------------------------------------------------------------------
//
function void
init;
 
fork
run_q();
join_none
 
$display("^^^ %16.t | %m | initialization", $time);
 
endfunction: init
 
endclass: tb_nonblocking_transaction_q_class
 
 
// --------------------------------------------------------------------
//
class tb_blocking_transaction_q_class #(parameter type T = logic);
 
T tr_h;
mailbox #(T) q;
semaphore q_semaphore;
 
//--------------------------------------------------------------------
function new;
 
this.q = new();
this.q_semaphore = new(1);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
event start;
event done;
 
virtual task automatic
transaction
(
ref T tr_h
);
 
->start;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
->done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
task
put
(
ref T tr_h
);
 
q.put(tr_h);
 
endtask: put
 
 
// --------------------------------------------------------------------
//
task automatic
run_q;
 
if(q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Aready active |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.q = new();
 
run_q_fork : fork
forever
begin
q.get(tr_h);
transaction(tr_h);
end
join_none
 
#0;
 
endtask: run_q
 
 
// --------------------------------------------------------------------
//
function void
init;
 
fork
run_q();
join_none
 
$display("^^^ %16.t | %m | initialization", $time);
 
endfunction: init
 
endclass: tb_blocking_transaction_q_class
 
 
endpackage: tb_bfm_pkg
 
/qaz_libs/trunk/BFM/src/tb/tb_clk.sv
0,0 → 1,55
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
import tb_clk_pkg::*;
 
module
tb_clk
#(
parameter PERIOD = 0
)
(
output clock
);
 
tb_clk_class tb_clk_c;
tb_clk_if tb_clk_driver();
assign clock = tb_clk_driver.clk;
 
initial
begin
 
tb_clk_c = new( tb_clk_driver );
 
if( PERIOD != 0 )
tb_clk_c.init_basic_clock( PERIOD );
 
end
 
endmodule
 
 
/qaz_libs/trunk/BFM/src/tb/tb_clk_class.sv
0,0 → 1,110
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
// --------------------------------------------------------------------
//
interface tb_clk_if;
logic clk = 0;
logic enable = 0;
time period;
event clk_rise;
event clk_fall;
modport tb_m
(
output clk
);
endinterface: tb_clk_if
 
 
// --------------------------------------------------------------------
//
class
tb_clk_class;
virtual tb_clk_if tb;
 
// --------------------------------------------------------------------
//
function
new
(
virtual tb_clk_if tb
);
this.tb = tb;
endfunction: new
 
// --------------------------------------------------------------------
//
task
init_basic_clock
(
time period
);
tb.period = period;
tb.enable = 1;
$display( "^^^ %16.t | %m | Starting clock with period %t.", $time, period );
fork
forever
if( tb.enable )
begin
#(period/2) tb.clk = 1;
-> tb.clk_rise;
#(period/2) tb.clk = 0;
-> tb.clk_fall;
end
join_none
endtask: init_basic_clock
// --------------------------------------------------------------------
//
task
enable_clock
(
logic enable
);
tb.enable = enable;
$display( "^^^ %16.t | %m | Clock Enable = %h.", $time, enable );
endtask: enable_clock
endclass: tb_clk_class
 
 
/qaz_libs/trunk/BFM/src/tb/tb_clk_pkg.sv
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
// --------------------------------------------------------------------
//
interface tb_clk_if;
logic clk = 0;
logic enable = 0;
time period;
event clk_rise;
event clk_fall;
modport tb_m
(
output clk
);
endinterface: tb_clk_if
 
 
// --------------------------------------------------------------------
//
package tb_clk_pkg;
 
// --------------------------------------------------------------------
//
class
tb_clk_class;
virtual tb_clk_if tb;
 
// --------------------------------------------------------------------
//
function
new
(
virtual tb_clk_if tb
);
this.tb = tb;
endfunction: new
 
// --------------------------------------------------------------------
//
task
init_basic_clock
(
time period
);
tb.period = period;
tb.enable = 1;
$display( "^^^ %16.t | %m | Starting clock with period %t.", $time, period );
fork
forever
if( tb.enable )
begin
#(period/2) tb.clk = 1;
-> tb.clk_rise;
#(period/2) tb.clk = 0;
-> tb.clk_fall;
end
join_none
endtask: init_basic_clock
// --------------------------------------------------------------------
//
task
enable_clock
(
logic enable
);
tb.enable = enable;
$display( "^^^ %16.t | %m | Clock Enable = %h.", $time, enable );
endtask: enable_clock
// --------------------------------------------------------------------
//
endclass: tb_clk_class
//--------------------------------------------------------------------
//
endpackage: tb_clk_pkg
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_downsizer.sv
0,0 → 1,99
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_downsizer
#(
N, // PCIe IP data in width in bytes
S // data out size divisor
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_out
);
 
// --------------------------------------------------------------------
//
riffa_chnl_xx_downsizer #(.N(N), .S(S))
riffa_chnl_xx_downsizer_i
(
.xx_in(chnl_in.rx),
.ack_in(chnl_in.rx_ack),
.last_in(chnl_in.rx_last),
.len_in(chnl_in.rx_len),
.off_in(chnl_in.rx_off),
.data_in(chnl_in.rx_data),
.data_valid_in(chnl_in.rx_data_valid),
.data_ren_in(chnl_in.rx_data_ren),
 
.last_out(chnl_out.rx_last),
.len_out(chnl_out.rx_len),
.off_out(chnl_out.rx_off),
.data_out(chnl_out.rx_data),
.data_valid_out(chnl_out.rx_data_valid),
.data_ren_out(chnl_out.rx_data_ren),
.reset(chnl_in.rx_reset),
.clk(chnl_in.rx_clk)
);
// --------------------------------------------------------------------
//
riffa_chnl_xx_upsizer #(.N(N/S), .S(S))
riffa_chnl_xx_upsizer_i
(
.xx_in(chnl_in.tx),
.ack_in(chnl_in.tx_ack),
.last_in(chnl_out.tx_last),
.len_in(chnl_out.tx_len),
.off_in(chnl_out.tx_off),
.data_in(chnl_out.tx_data),
.data_valid_in(chnl_out.tx_data_valid),
.data_ren_in(chnl_out.tx_data_ren),
 
.last_out(chnl_in.tx_last),
.len_out(chnl_in.tx_len),
.off_out(chnl_in.tx_off),
.data_out(chnl_in.tx_data),
.data_valid_out(chnl_in.tx_data_valid),
.data_ren_out(chnl_in.tx_data_ren),
.reset(chnl_in.tx_reset),
.clk(chnl_in.tx_clk)
);
 
 
// --------------------------------------------------------------------
//
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer.sv
0,0 → 1,137
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_downsizer
#(
N, // PCIe IP data in width in bytes
S // data out size divisor
)
(
input xx_in,
output ack_in,
input last_in,
input [31:0] len_in,
input [30:0] off_in,
input [(8*N)-1:0] data_in,
input data_valid_in,
output data_ren_in,
 
output last_out,
output reg [31:0] len_out,
output reg [30:0] off_out,
output [(8*N/S)-1:0] data_out,
output data_valid_out,
input data_ren_out,
 
input reset,
input clk
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_divisor: assert(S > 1) else $fatal;
a_data_mod: assert(N % S == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
wire [(8*N)-1:0] wr_data = data_in;
wire wr_full;
wire wr_en = data_ren_in & data_valid_in;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
 
tiny_sync_fifo #(.W((8*N)))
tiny_sync_fifo_i(.*);
 
 
// --------------------------------------------------------------------
//
localparam M_A = $clog2(S);
localparam M_D = 2 ** M_A;
localparam M_NW = (N*8)/ S;
 
wire [M_A-1:0] select;
 
riffa_chnl_xx_downsizer_fsm #(.N(N), .S(S), .M_A(M_A))
riffa_chnl_xx_downsizer_fsm_i(.*);
 
 
// --------------------------------------------------------------------
//
wire [M_NW-1:0] mux_in [M_D-1:0];
 
recursive_mux #(.A(M_A), .W(M_NW))
tdata_mux_i(.data_in(mux_in), .data_out(data_out), .*);
 
 
// --------------------------------------------------------------------
//
generate
begin: rd_data_gen
for(genvar j = 0; j < M_D; j++)
assign mux_in[j] = rd_data[j*M_NW +: M_NW];
end
endgenerate
 
 
// --------------------------------------------------------------------
//
reg last_in_r;
 
always_ff @(posedge clk)
if(xx_in & ack_in)
begin
last_in_r <= last_in;
len_out <= len_in;
off_out <= off_in;
end
 
 
// --------------------------------------------------------------------
//
riffa_chnl_fsm
riffa_chnl_fsm_i(.*);
// --------------------------------------------------------------------
//
assign last_out = (select == S - 1) ? last_in_r : 0; // need to fix
assign data_ren_in = ~wr_full;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer_fsm.sv
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_downsizer_fsm
#(
N, // PCIe IP data in width in bytes
S, // data out size divisor
M_A
)
(
input rd_empty,
input data_ren_out,
 
output rd_en,
output data_valid_out,
output reg [M_A-1:0] select,
 
input reset,
input clk
);
 
// --------------------------------------------------------------------
//
wire almost_last_word;
 
 
//---------------------------------------------------
// state machine binary definitions
enum reg [2:0]
{
GET_WORD_IN = 3'b001,
MUX_WORD_OUT = 3'b010,
LAST_WORD_OUT = 3'b100
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge clk)
if(reset)
state <= GET_WORD_IN;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
GET_WORD_IN: if(~rd_empty)
next_state <= MUX_WORD_OUT;
else
next_state <= GET_WORD_IN;
 
MUX_WORD_OUT: if(rd_empty)
next_state <= GET_WORD_IN;
else if(almost_last_word & data_ren_out)
next_state <= LAST_WORD_OUT;
else
next_state <= MUX_WORD_OUT;
 
LAST_WORD_OUT: if(~data_ren_out)
next_state <= LAST_WORD_OUT;
else
next_state <= MUX_WORD_OUT;
 
default: next_state <= GET_WORD_IN;
 
endcase
 
 
// --------------------------------------------------------------------
//
assign almost_last_word = (select == S - 2);
 
always_ff @(posedge clk)
if(reset | (state == GET_WORD_IN))
select <= 0;
else if(data_valid_out & data_ren_out)
select <= select + 1;
 
 
// --------------------------------------------------------------------
//
wire changing_state = (state != next_state);
assign rd_en = (state == LAST_WORD_OUT) & changing_state;
assign data_valid_out = (state != GET_WORD_IN) & ~rd_empty;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_chnl_xx_upsizer.sv
0,0 → 1,73
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
riffa_chnl_xx_upsizer
#(
N, // PCIe IP data in width in bytes
S // data out size multiplier
)
(
input xx_in,
output ack_in,
input last_in,
input [31:0] len_in,
input [30:0] off_in,
input [(8*N)-1:0] data_in,
input data_valid_in,
output data_ren_in,
 
output last_out,
output [31:0] len_out,
output [30:0] off_out,
output [(8*N*S)-1:0] data_out,
output data_valid_out,
input data_ren_out,
input reset,
input clk
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_multiplier: assert((S > 1) & (S % 2 == 0))else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_files.f File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/files.f File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_top_pkg.sv File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/vs_debug.svh File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/sim.f File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_top.sv File deleted
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.sv
0,0 → 1,146
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
// --------------------------------------------------------------------
//
tb_riffa_register_file_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
always_ff @(posedge chnl_bus.rx_clk)
if(chnl_bus.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv
0,0 → 1,92
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(5us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*B, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*B, 0, 1);
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.tr_h = new(RW, 0, 1);
tb_top.a_h.tr_h.constant(RW, 0, 1, 1);
tb_top.a_h.queue_tx(tb_top.a_h.tr_h);
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.tx_q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
0,0 → 1,70
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_register_file_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam N = 16; // width of the bus in bytes
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
 
// --------------------------------------------------------------------
//
class tb_riffa_register_file_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_register_file_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_register_file_pkg
 
 
 
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/init_test.do
7,6 → 7,7
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
18,8 → 19,18
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
vlog -f ./tb_files.f
vlog -f ./files.f
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/sim.do
3,8 → 3,9
 
quit -sim
 
# vsim -suppress 12110 -novopt work.tb_top
vsim -f ./sim.f work.tb_top
vsim -novopt work.tb_top
 
# log all signals
log /* -r
log -r *
 
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.f
0,0 → 1,14
#
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/wip.do
1,5 → 1,13
#
 
vlog -f ./tb_files.f
vlog -f ./files.f
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_env.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_pkg.sv File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_agent.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_config.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/s_riffa_rp_rx_api.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_rp_rx_driver.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_sequence_item.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/s_riffa_rp_tx_api.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/RIFFA/riffa_rp_tx_driver.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/tb_riffa_debug/vs_top_base.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/tb_riffa_debug/t_debug.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/tb_riffa_debug/tb_env.svh File deleted
/qaz_libs/trunk/PCIe/sim/src/tb_riffa_debug/t_top_base.svh File deleted
/qaz_libs/trunk/axi4_stream_lib/sim/src/axis_bfm_pkg.sv
0,0 → 1,220
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axis_bfm_pkg;
 
 
// --------------------------------------------------------------------
//
import q_pkg::*;
import bfm_pkg::*;
 
 
// --------------------------------------------------------------------
//
class axis_tr_class #(N, I, D, U)
extends transaction_class #(axis_tr_class #(N, I, D, U));
 
rand logic [(8*N)-1:0] tdata;
rand logic [N-1:0] tstrb;
rand logic [N-1:0] tkeep;
rand logic tlast;
rand logic [I-1:0] tid;
rand logic [D-1:0] tdest;
rand logic [U-1:0] tuser;
 
// --------------------------------------------------------------------
//
function void copy(TR_T from);
// delay_class delay_h;
this.tdata = from.tdata;
this.tstrb = from.tstrb;
this.tkeep = from.tkeep;
this.tlast = from.tlast;
this.tid = from.tid;
this.tdest = from.tdest;
this.tuser = from.tuser;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
endclass: axis_tr_class
 
 
// --------------------------------------------------------------------
//
class axis_tx_bfm_class #(N, I, D, U)
extends blocking_transmission_q_class #(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)));
 
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out;
 
 
//--------------------------------------------------------------------
//
function void set_default;
axis_out.cb_m.tvalid <= 0;
axis_out.cb_m.tdata <= 'bx;
axis_out.cb_m.tstrb <= 'bx;
axis_out.cb_m.tkeep <= 'bx;
axis_out.cb_m.tlast <= 'bx;
axis_out.cb_m.tid <= 'bx;
axis_out.cb_m.tdest <= 'bx;
axis_out.cb_m.tuser <= 'bx;
endfunction: set_default
 
 
//--------------------------------------------------------------------
//
task tx_transaction(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)) tr_h);
axis_out.zero_cycle_delay();
repeat(tr_h.delay_h.delay) @(axis_out.cb_m);
 
axis_out.cb_m.tvalid <= 1;
axis_out.cb_m.tdata <= tr_h.tdata;
axis_out.cb_m.tstrb <= 0;
axis_out.cb_m.tkeep <= 0;
axis_out.cb_m.tlast <= tr_h.tlast;
axis_out.cb_m.tid <= 0;
axis_out.cb_m.tdest <= 0;
axis_out.cb_m.tuser <= tr_h.tuser;
 
@(axis_out.cb_m);
wait(axis_out.cb_m.tready);
// @(axis_out.cb_m iff axis_out.cb_m.tready);
 
set_default();
endtask: tx_transaction
 
 
// --------------------------------------------------------------------
//
event tx_done;
 
task automatic transmit(ref Q_T tr_h);
tx_transaction(tr_h);
->tx_done;
endtask: transmit
 
 
//--------------------------------------------------------------------
//
task init;
set_default();
endtask: init
 
 
//--------------------------------------------------------------------
//
function new(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out);
this.axis_out = axis_out;
tr_h = new();
fork
init();
join_none
$display("^^^ %16.t | %m", $time);
endfunction: new
 
// --------------------------------------------------------------------
//
endclass: axis_tx_bfm_class
 
 
// --------------------------------------------------------------------
//
class axis_rx_bfm_class #(N, I, D, U)
extends blocking_receiver_q_class #(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)));
 
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in;
 
 
//--------------------------------------------------------------------
//
function void set_tready(bit value);
axis_in.cb_s.tready <= value;
endfunction: set_tready
 
 
//--------------------------------------------------------------------
//
task rx_transaction(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)) tr_h);
repeat(tr_h.delay_h.delay) @(axis_in.cb_s);
axis_in.cb_s.tready <= 1;
 
@(axis_in.cb_s);
wait(axis_in.cb_s.tvalid);
// @(axis_in.cb_s iff axis_in.cb_s.tvalid);
 
tr_h.tdata <= axis_in.cb_s.tdata;
tr_h.tstrb <= axis_in.cb_s.tstrb;
tr_h.tkeep <= axis_in.cb_s.tkeep;
tr_h.tlast <= axis_in.cb_s.tlast;
tr_h.tid <= axis_in.cb_s.tid;
tr_h.tdest <= axis_in.cb_s.tdest;
tr_h.tuser <= axis_in.cb_s.tuser;
 
axis_in.cb_s.tready <= 0;
endtask: rx_transaction
 
 
// --------------------------------------------------------------------
//
event rx_frame_done;
 
virtual task receive(ref Q_T tr_h);
tr_h = new();
void'(tr_h.delay_h.next());
rx_transaction(tr_h);
->rx_frame_done;
endtask: receive
 
 
//--------------------------------------------------------------------
//
task init;
set_tready(0);
endtask: init
 
 
//--------------------------------------------------------------------
//
function new (virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in);
this.axis_in = axis_in;
fork
init();
join_none
$display("^^^ %16.t | %m", $time);
endfunction: new
 
endclass: axis_rx_bfm_class
 
 
// --------------------------------------------------------------------
//
endpackage: axis_bfm_pkg
 
/qaz_libs/trunk/axi4_stream_lib/sim/src/tb_axis_to_axi4_agent_class_pkg.sv
0,0 → 1,158
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_axis_to_axi4_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import axi4_memory_pkg::*;
import axis_bfm_pkg::*;
 
 
// --------------------------------------------------------------------
//
class tb_axis_to_axi4_agent_class #(N, A, I, D, U);
 
axi4_memory_class #(A, N, I) m_h;
axis_tx_bfm_class #(N, I, D, U) s_h;
memory_tr_class #(A, N, I) m_tr_h;
axis_tr_class #(N, I, D, U) s_tr_h;
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in;
 
mailbox #(memory_tr_class #(A, N, I)) q;
 
 
// --------------------------------------------------------------------
//
task wait_for_sof;
@(posedge axis_in.cb_s.tuser);
$display("^^^ %16.t | %m", $time);
endtask: wait_for_sof
 
 
// --------------------------------------------------------------------
//
task wait_for_dma_done(int bvalid_count);
repeat(bvalid_count)
@(axi4_m.cb_s iff axi4_m.cb_m.bvalid & axi4_m.cb_s.bready);
$display("^^^ %16.t | %m", $time);
endtask: wait_for_dma_done
 
 
// --------------------------------------------------------------------
//
task random_transaction(int addr, int size, int stride);
m_h.clear_all();
m_tr_h = new();
m_tr_h.random(addr, size);
q.put(m_tr_h);
 
$display("^^^ %16.t | %m | m_tr_h.data.size = %x", $time, m_tr_h.data.size);
for(int i = 0; i < m_tr_h.data.size; i += N)
begin
s_tr_h = new();
for(int k = 0; k < N; k++)
begin
s_tr_h.tdata[k*8 +: 8] = m_tr_h.data[i + k];
end
 
if(i == 0)
s_tr_h.tuser = 'b1;
else
s_tr_h.tuser = 'b0;
 
if(i + N < m_tr_h.data.size)
s_tr_h.tlast = 1'b0;
else
s_tr_h.tlast = 1'b1;
 
s_h.q.put(s_tr_h);
end
 
wait_for_dma_done(size / stride);
endtask: random_transaction
 
 
// --------------------------------------------------------------------
//
task automatic compare(int offset);
byte data[];
 
$display("^^^ %16.t | %m", $time);
$display("^^^ %16.t | q.num = %d", $time, q.num);
$display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num);
$display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size);
 
if(q.try_get(m_tr_h) == 0)
begin
$display("!!! %16.t | ERROR!!! try_get(m_tr_h) == 0", $time);
$stop;
end
 
data = new[m_tr_h.data.size];
m_h.dump_words(offset, data);
 
foreach(m_tr_h.data[i])
if(data[i] != m_tr_h.data[i])
begin
$display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time);
$display("!!! %16.t | %x ", $time, i);
$display("!!! %16.t | %x | %x |", $time, data[i], m_tr_h.data[i]);
$stop;
end
 
$display("^^^ %16.t | %m | done!", $time);
 
endtask: compare
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m,
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in
);
 
this.axi4_m = axi4_m;
this.axis_in = axis_in;
m_h = new(axi4_m);
s_h = new(axis_in);
q = new();
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_axis_to_axi4_agent_class
 
// --------------------------------------------------------------------
//
endpackage: tb_axis_to_axi4_agent_class_pkg
/qaz_libs/trunk/axi4_stream_lib/sim/src/tb_axis_upsizer.sv
0,0 → 1,144
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset
sync_reset_i(aclk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_axis_upsizer_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(AVF_N), .U(AVF_U)) axis_in(.*);
axis_if #(.N(AVF_N * S), .U(AVF_U * S)) axis_out(.*);
 
 
// --------------------------------------------------------------------
//
axis_upsizer
#(
.N(AVF_N), // data bus width in bytes
.I(1), // TID width
.D(1), // TDEST width
.U(AVF_U), // TUSER width
.S(S), // tdata size multiplier
.USE_TSTRB(0), // set to 1 to enable, 0 to disable
.USE_TKEEP(0), // set to 1 to enable, 0 to disable
.BYTES_PER_TUSER(0) // bytes per tuser bit. Set to 0 for transfer based.
)
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
axis_checker #(.N(AVF_N * S), .I(1), .D(1), .U(AVF_U))
axis_checker_i(.*);
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if(.*);
 
assign axis_out.tready = avf_axis_in_if.tready;
assign avf_axis_in_if.tvalid = axis_out.tvalid;
assign avf_axis_in_if.tdata = axis_out.tdata;
assign avf_axis_in_if.tuser = {axis_out.tuser[(AVF_U*S)-1], axis_out.tuser[1:0]};
assign avf_axis_in_if.tlast = axis_out.tlast;
 
 
// --------------------------------------------------------------------
//
tb_axis_upsizer_class a_h;
 
initial
a_h = new(.avf_axis_in_if(avf_axis_in_if), .avf_axis_out_if(axis_in));
 
 
// --------------------------------------------------------------------
//
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_agent_class_pkg.sv
0,0 → 1,129
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_axis_upsizer_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import video_frame_pkg::*;
import axis_video_frame_bfm_pkg::*;
 
 
// --------------------------------------------------------------------
//
class tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S);
 
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if;
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if;
 
avf_config_class c_h;
 
avf_tx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) tx_h;
avf_rx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE * S, AVF_U) rx_h;
 
video_frame_class clone_h;
video_frame_class sent_f_h;
video_frame_class rx_f_h;
 
mailbox #(video_frame_class) q;
 
 
// --------------------------------------------------------------------
//
virtual task
queue_frame
(
string pattern = "",
int pixel = 0
);
 
if(pattern != "")
tx_h.make_frame(pattern, pixel);
 
clone_h = tx_h.tx_bfm_h[0].f_h.clone();
tx_h.tx_bfm_h[0].put(clone_h);
q.put(clone_h);
 
$display("^^^ %16.t | %m | using %s pattern", $time, pattern);
 
endtask: queue_frame
 
 
// --------------------------------------------------------------------
//
virtual task automatic
compare_frame;
 
int mismatch_count;
 
$display("^^^ %16.t | %m", $time);
 
q.get(sent_f_h);
rx_h.rx_bfm_h[0].get(rx_f_h);
mismatch_count = sent_f_h.compare(8, rx_f_h);
 
endtask: compare_frame
 
 
//--------------------------------------------------------------------
//
function void init(avf_config_class in_c_h, avf_config_class out_c_h);
 
rx_h = new(in_c_h, '{avf_axis_in_if});
tx_h = new(out_c_h, '{avf_axis_out_if});
 
this.q = new();
 
endfunction: init
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if
);
 
this.avf_axis_in_if = avf_axis_in_if;
this.avf_axis_out_if = avf_axis_out_if;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_axis_upsizer_agent_class
 
// --------------------------------------------------------------------
//
endpackage: tb_axis_upsizer_agent_class_pkg
 
 
 
 
 
/qaz_libs/trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_class_pkg.sv
0,0 → 1,114
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_axis_upsizer_class_pkg;
 
// --------------------------------------------------------------------
//
import axis_video_frame_bfm_pkg::*;
import tb_axis_upsizer_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam WIDTH = 32; // tile width
localparam HEIGHT = 16; // tile height
localparam OUTPUTS_PER_TILE = 1; // outputs per tile
localparam BYTES_PER_PIXEL = 2;
localparam BITS_PER_PIXEL = 16;
localparam VERTICAL_BLANKING = 20;
 
localparam S = 4; // tdata size multiplier
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes
localparam AVF_U = 3; // TUSER width
 
 
// --------------------------------------------------------------------
//
class tb_axis_upsizer_class
extends tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S);
 
avf_config_class in_c_h;
avf_config_class out_c_h;
avf_tile_config_t tile_config[];
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if,
virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if
);
 
super.new(avf_axis_in_if, avf_axis_out_if);
 
this.tile_config = new[1];
this.tile_config[0].direction = RIGHT_DOWN;
 
this.in_c_h = new
(
.width(WIDTH),
.height(HEIGHT),
.bytes_per_pixel(BYTES_PER_PIXEL),
.bits_per_pixel(BITS_PER_PIXEL),
.pixels_per_clk(OUTPUTS_PER_TILE * S),
.name("IN_"),
.vertical_blanking(VERTICAL_BLANKING),
.tile(tile_config)
);
 
this.out_c_h = new
(
.width(WIDTH),
.height(HEIGHT),
.bytes_per_pixel(BYTES_PER_PIXEL),
.bits_per_pixel(BITS_PER_PIXEL),
.pixels_per_clk(OUTPUTS_PER_TILE),
.name("OUT_"),
.vertical_blanking(VERTICAL_BLANKING),
.tile(tile_config)
);
 
super.init(in_c_h, out_c_h);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_axis_upsizer_class
 
// --------------------------------------------------------------------
//
endpackage: tb_axis_upsizer_class_pkg
 
 
 
 
 
/qaz_libs/trunk/axi4_stream_lib/sim/src/tb_axis_register_slice.sv
0,0 → 1,159
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #( .PERIOD(5_000) ) tb( clk_200mhz, tb_rst );
 
 
// --------------------------------------------------------------------
//
localparam TILES = 1;
localparam WIDTH = 32; // tile width
localparam HEIGHT = 16; // tile height
localparam OUTPUTS_PER_TILE = 1; // outputs per tile
localparam BYTES_PER_PIXEL = 2;
localparam BITS_PER_PIXEL = 16;
localparam VERTICAL_BLANKING = 20;
 
 
// --------------------------------------------------------------------
//
localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes
localparam AVF_U = 1; // TUSER width
 
axis_if #(.N(AVF_N), .U(AVF_U)) axis_in[TILES](.*);
axis_if #(.N(AVF_N), .U(AVF_U)) axis_out[TILES](.*);
 
 
// --------------------------------------------------------------------
//
axis_register_slice #(.N(AVF_N), .U(AVF_U))
dut
(
.axis_en(1'b1),
.axis_in(axis_in.slave[0]),
.axis_out(axis_out.master[0]),
.*
);
// --------------------------------------------------------------------
//
import axis_video_frame_bfm_pkg::*;
import avf_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
avf_agent_config_class avf_agent_config_h;
avf_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_agent_h;
 
initial
begin
 
avf_agent_config_h = new
(
.width(WIDTH),
.height(HEIGHT),
.bytes_per_pixel(BYTES_PER_PIXEL),
.bits_per_pixel(BITS_PER_PIXEL),
.tiles(TILES),
.outputs_per_tile(OUTPUTS_PER_TILE),
.name("AVF_"),
.vertical_blanking(VERTICAL_BLANKING)
);
 
avf_agent_config_h.tile[0].direction = RIGHT_DOWN;
 
avf_agent_h = new
(
.avf_agent_config(avf_agent_config_h),
.avf_axis_in_if(axis_out),
.avf_axis_out_if(axis_in)
);
 
avf_agent_h.init();
 
end
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
for(genvar j = 0; j < TILES; j++)
axis_video_debug #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_debug(axis_out[j]);
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
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qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do (nonexistent) @@ -1,37 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -sim_compile_all tb_packages -sim_compile_all bfm_packages -sim_compile_all axi4_lib -sim_compile_all qaz_libs -sim_compile_all sim -vlog -f ./tb_axis_upsizer.f - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_axis_upsizer.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv (nonexistent) @@ -1,98 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int mismatch_count = 0; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(50us); - - - // -------------------------------------------------------------------- - wait(tb_top.aresetn); - #1us; - - // -------------------------------------------------------------------- - repeat(3) tb_top.a_h.queue_frame("counting"); - repeat(3) tb_top.a_h.compare_frame(); - - // -------------------------------------------------------------------- - tb_top.a_h.tx_h.make_frame("constant", 16'habba); - tb_top.a_h.queue_frame(); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("random"); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("constant", 16'hbeef); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("random"); - tb_top.a_h.rx_h.wait_for_rx_frames(1); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("counting"); - tb_top.a_h.compare_frame(); - - repeat(3) tb_top.a_h.queue_frame("random"); - repeat(3) tb_top.a_h.compare_frame(); - - // -------------------------------------------------------------------- - #1us; - // #6us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do (nonexistent) @@ -1,16 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# log all signals -log -r * - -# run -all - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${PROJECT_DIR}/sim/src/tb_axis_upsizer_agent_class_pkg.sv -${PROJECT_DIR}/sim/src/tb_axis_upsizer_class_pkg.sv - -${PROJECT_DIR}/src/axis_upsizer.sv Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# log all signals -log -r * - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${PROJECT_DIR}/src/axis_switch.sv -${PROJECT_DIR}/src/recursive_axis_switch.sv - -${PROJECT_DIR}/src/axis_switch_allocator.sv Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (nonexistent) @@ -1,118 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_axis_switch_allocator_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); - - - // -------------------------------------------------------------------- - // - axis_switch_allocator #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP), .SA(SA)) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - - // -------------------------------------------------------------------- - // - tb_axis_switch_allocator_class a_h; - - initial - a_h = new(axis_in, axis_out); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (nonexistent) @@ -1,143 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axis_switch_allocator_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam AW = 32; // active width - localparam AH = 16; // active height - localparam B = 2; // bytes per pixel - localparam T = 1; // pixels per clock - localparam VERTICAL_BLANKING = AW * 4; - localparam N = B * T; // data bus width in bytes - localparam I = 1; // TID width - localparam D = 1; // TDEST width - localparam U = 3; // TUSER width - localparam U_IS_EOP = 2; - localparam SA = 3; - localparam SD = 2 ** SA; - - - // -------------------------------------------------------------------- - // - class tb_axis_switch_allocator_class; - - avf_config_class c_h; - avf_tile_config_t tile_config[]; - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; - - avf_tx_class #(B, T, U) tx_h; - avf_rx_class #(B, T, U) rx_h; - - // video_frame_class clone_h; - // video_frame_class sent_f_h; - // video_frame_class rx_f_h; - - // mailbox #(video_frame_class) q[]; - - - // -------------------------------------------------------------------- - // - task automatic - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - video_frame_class clone_h; - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - foreach(tx_h.tx_bfm_h[i]) - begin - clone_h = tx_h.tx_bfm_h[i].f_h.clone(); - tx_h.tx_bfm_h[i].put(clone_h); - // q[i].put(clone_h); - end - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(N), .U(U)) axis_in, - virtual axis_if #(.N(N), .U(U)) axis_out[] - ); - - this.axis_out = axis_out; - this.axis_in = axis_in; - - this.tile_config = new[T]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.c_h = new - ( - .width(AW), - .height(AH), - .bytes_per_pixel(B), - .bits_per_pixel(B * 8), - .pixels_per_clk(T), - .name("AVR_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - rx_h = new(c_h, axis_out); - tx_h = new(c_h, '{axis_in}); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_switch_allocator_class - - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_switch_allocator_pkg - - - - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_axis_switch_allocator - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv (nonexistent) @@ -1,88 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module the_test(input tb_clk, input tb_rst); - - // -------------------------------------------------------------------- - // - import tb_axis_switch_allocator_pkg::*; - - // -------------------------------------------------------------------- - // - int i = 0; - - task automatic run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(2ms); - wait(~tb_rst); - - // -------------------------------------------------------------------- - #1us; - - // // -------------------------------------------------------------------- - // repeat(1)tb_top.a_h.queue_frame("counting"); - - // // -------------------------------------------------------------------- - // repeat(1) tb_top.a_h.queue_frame("random"); - // repeat(1)tb_top.a_h.queue_frame("counting"); - // repeat(3) tb_top.a_h.queue_frame("random"); - // tb_top.a_h.queue_frame("constant", 16'habba); - - // // -------------------------------------------------------------------- - // for(i = 0; i < SD; i++) - // begin - // #1us; - // tb_top.a_h.queue_frame("counting"); - // #8us; - // end - - // -------------------------------------------------------------------- - repeat(SD * 2) tb_top.a_h.queue_frame("counting"); - - // -------------------------------------------------------------------- - #100us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do (nonexistent) @@ -1,12 +0,0 @@ -# - - -vlog -f ../../libs/axi4_stream_lib_verilog/axi4_stream_lib.f - -# simulation $root -vlog ../../src/tb_axis_register_slice.sv - -# compile test last -vlog ./the_test.sv - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -# sim_compile_all FPGA -sim_compile_all sim -sim_compile_all sync_fifo -sim_compile_all axi4_stream_lib - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_axis_register_slice.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv (nonexistent) @@ -1,79 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int mismatch_count = 0; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - // -------------------------------------------------------------------- - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(4us); - wait(~tb_rst); - - - // -------------------------------------------------------------------- - repeat(100) @(posedge tb_clk); - tb_top.avf_agent_h.make_frame("counting"); - tb_top.avf_agent_h.get_frame(); - tb_top.avf_agent_h.put_frame(); - - wait(~tb_top.avf_agent_h.put_frame_active); - wait(~tb_top.avf_agent_h.get_frame_active); - - mismatch_count = tb_top.avf_agent_h.compare_frame(); - - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do (nonexistent) @@ -1,21 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top - -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top -# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - - -# # log all signals -# log -r * - -# run -all - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv (nonexistent) @@ -1,328 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package axis_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import bfm_pkg::*; - - // -------------------------------------------------------------------- - // - typedef struct - { - int unsigned N; // data bus width in bytes - int unsigned I; // TID width - int unsigned D; // TDEST width - int unsigned U; // TUSER width - bit USE_TSTRB; // set to 1 to enable, 0 to disable - bit USE_TKEEP; // set to 1 to enable, 0 to disable - bit USE_ROUTING; // set to 1 to enable, 0 to disable - } axis_config_t; - - // -------------------------------------------------------------------- - // - class axis_sequence_item #(axis_config_t cfg) - extends uvm_sequence_item; - `uvm_object_param_utils(axis_sequence_item #(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - delay_class delay_h; - rand logic [(8*N)-1:0] tdata; - rand logic [N-1:0] tstrb; - rand logic [N-1:0] tkeep; - rand logic tlast; - rand logic [I-1:0] tid; - rand logic [D-1:0] tdest; - rand logic [U-1:0] tuser; - - // -------------------------------------------------------------------- - // - function new(string name = ""); - super.new(name); - delay_h = new; - endfunction : new - - // -------------------------------------------------------------------- - // - function bit do_compare(uvm_object rhs, uvm_comparer comparer); - axis_sequence_item #(cfg) tested; - bit same; - - if (rhs==null) - `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer"); - - if (!$cast(tested,rhs)) - same = 0; - else - same = super.do_compare(rhs, comparer) - & (tested.tdata == tdata) - & (USE_TSTRB ? (tested.tstrb == tstrb) : 1) - & (USE_TKEEP ? (tested.tkeep == tkeep) : 1) - & (tested.tlast == tlast) - & (USE_ROUTING ? (tested.tid == tid) : 1) - & (USE_ROUTING ? (tested.tdest == tdest) : 1) - & (tested.tuser == tuser); - return same; - endfunction : do_compare - - // -------------------------------------------------------------------- - // - function void do_copy(uvm_object rhs); - axis_sequence_item #(cfg) item; - assert(rhs != null) else - `uvm_fatal(get_type_name(), "| %m | copy null transaction"); - super.do_copy(rhs); - assert($cast(item,rhs)) else - `uvm_fatal(get_type_name(), "| %m | failed cast"); - tdata = item.tdata; - tstrb = item.tstrb; - tkeep = item.tkeep; - tlast = item.tlast; - tid = item.tid; - tdest = item.tdest; - tuser = item.tuser; - endfunction : do_copy - - // -------------------------------------------------------------------- - // - function string convert2string(); - string s0, s1; - s0 = $sformatf("| tdata: %h\n" ,tdata); - s1 = $sformatf("| tlast: %1h | tuser: %h" , tlast, tuser); - return {s1, s0}; - endfunction : convert2string - - // -------------------------------------------------------------------- - // - endclass : axis_sequence_item - - // -------------------------------------------------------------------- - // - class axis_driver #(parameter axis_config_t cfg) - extends uvm_driver #(axis_sequence_item #(cfg)); - `uvm_component_param_utils(axis_driver#(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; - - //-------------------------------------------------------------------- - // - function void set_default; - axis_bus.cb_m.tvalid <= 0; - axis_bus.cb_m.tdata <= 'bx; - axis_bus.cb_m.tstrb <= 'bx; - axis_bus.cb_m.tkeep <= 'bx; - axis_bus.cb_m.tlast <= 'bx; - axis_bus.cb_m.tid <= 'bx; - axis_bus.cb_m.tdest <= 'bx; - axis_bus.cb_m.tuser <= 'bx; - endfunction: set_default - - //-------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - axis_sequence_item #(cfg) item; - super.run_phase(phase); - - set_default(); - wait(~axis_bus.aresetn); - @(axis_bus.cb_m); - - forever - begin - // seq_item_port.try_next_item(item); - seq_item_port.get_next_item(item); - - axis_bus.cb_m.tvalid <= 1; - axis_bus.cb_m.tdata <= item.tdata; - axis_bus.cb_m.tstrb <= 0; - axis_bus.cb_m.tkeep <= 0; - axis_bus.cb_m.tlast <= item.tlast; - axis_bus.cb_m.tid <= 0; - axis_bus.cb_m.tdest <= 0; - axis_bus.cb_m.tuser <= item.tuser; - - @(axis_bus.cb_m); - wait(axis_bus.cb_m.tready); - // @(axis_bus.cb_m iff axis_bus.cb_m.tready); - - set_default(); - repeat(item.delay_h.next()) @(axis_bus.cb_m); - - seq_item_port.item_done(); - end - endtask : run_phase - - //-------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_driver - - // -------------------------------------------------------------------- - // - class axis_sequencer #(axis_config_t cfg) - extends uvm_sequencer #(axis_sequence_item #(cfg)); - `uvm_component_param_utils(axis_sequencer #(cfg)) - - // -------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_sequencer - - // -------------------------------------------------------------------- - // - class axis_counting_sequence #(axis_config_t cfg) - extends uvm_sequence #(axis_sequence_item #(cfg)); - `uvm_object_param_utils(axis_counting_sequence #(cfg)) - - rand int length = 16; - - // -------------------------------------------------------------------- - // - virtual task body(); - axis_sequence_item #(cfg) item; - - for(int i = 0; i < length; i++) - begin - item = axis_sequence_item #(cfg)::type_id::create("axis_sequence_item"); - - item.tdata = i; - item.tlast = (i == length - 1); - - start_item (item); - finish_item(item); - end - endtask - - // -------------------------------------------------------------------- - // - function new(string name = "axis_counting_sequence"); - super.new(name); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_counting_sequence - - // -------------------------------------------------------------------- - // - class axis_agent #(axis_config_t cfg) - extends uvm_agent; - `uvm_component_param_utils(axis_agent #(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; - - axis_driver #(cfg) driver; - // my_monitor #(cfg) monitor; - axis_sequencer #(cfg) sequencer; - - // -------------------------------------------------------------------- - // - virtual function void build_phase(uvm_phase phase); - super.build_phase(phase); - - if(!uvm_config_db #(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)))::get(this, "", "axis_bus", axis_bus)) - `uvm_fatal(get_name(), "Couldn't get virtual interface!") - - driver = axis_driver #(cfg)::type_id::create("driver", this); - // monitor = my_monitor #(cfg)::type_id::create("monitor" , this); - sequencer = axis_sequencer #(cfg)::type_id::create("sequencer", this); - endfunction - - // -------------------------------------------------------------------- - // - virtual function void connect_phase(uvm_phase phase); - super.connect_phase(phase); - - driver.axis_bus = axis_bus; - // monitor.vif = vif; - - driver.seq_item_port.connect(sequencer.seq_item_export); - endfunction - - // -------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_agent - -// -------------------------------------------------------------------- -// -endpackage: axis_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do (nonexistent) @@ -1,11 +0,0 @@ -# - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -vlog ./$env(SIM_TB)_pkg.sv -vlog ./tests_pkg.sv - -# simulation $root -vlog ./$env(SIM_TB).sv - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do (nonexistent) @@ -1,42 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_axis_gear_box - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# AXI4 streaming package -vlog ./axis_pkg.sv - -vlog ./$env(SIM_TB)_pkg.sv -vlog ./tests_base_pkg.sv -vlog ./tests_pkg.sv -vlog ./tb_dut_if.sv - -# simulation $root -vlog ./$env(SIM_TB).sv - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# # compile test last -# vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f (nonexistent) @@ -1,6 +0,0 @@ -# - -./axis_pkg.sv - -${PROJECT_DIR}/src/axis_gear_box.sv - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv (nonexistent) @@ -1,85 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package tests_base_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import tb_axis_gear_box_pkg::*; - - // -------------------------------------------------------------------- - // - virtual class test_base extends uvm_test; - `uvm_component_utils(test_base); - tb_env env_h; - - // -------------------------------------------------------------------- - // - function void build_phase(uvm_phase phase); - env_h = tb_env::type_id::create("env_h",this); - endfunction : build_phase - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - endclass : test_base - - // -------------------------------------------------------------------- - // - class test_debug_base extends test_base; - `uvm_component_utils(test_debug_base) - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - function void final_phase(uvm_phase phase); - super.final_phase(phase); - $display("^^^ %16.t | %m | Test Done!!!", $time); - $stop; - endfunction : final_phase - - // -------------------------------------------------------------------- - // - endclass : test_debug_base - -// -------------------------------------------------------------------- -// -endpackage: tests_base_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv (nonexistent) @@ -1,63 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -import tb_axis_gear_box_pkg::*; - -interface - tb_dut_if #(dut_config_t dut_cfg) - ( - input aclk, - input aresetn - ); - - // -------------------------------------------------------------------- - // - axis_if - #( - .N(dut_cfg.axis_cfg_in.N), - .I(dut_cfg.axis_cfg_in.I), - .D(dut_cfg.axis_cfg_in.D), - .U(dut_cfg.axis_cfg_in.U) - ) - axis_in(.*); - - // -------------------------------------------------------------------- - // - axis_if - #( - .N(dut_cfg.axis_cfg_out.N), - .I(dut_cfg.axis_cfg_out.I), - .D(dut_cfg.axis_cfg_out.D), - .U(dut_cfg.axis_cfg_out.U) - ) - axis_out(.*); - -// -------------------------------------------------------------------- -// -endinterface: tb_dut_if - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv (nonexistent) @@ -1,90 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - -import tb_axis_gear_box_pkg::*; -import tests_pkg::*; -import uvm_pkg::*; -`include "uvm_macros.svh" - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - // -------------------------------------------------------------------- - // - import tb_axis_gear_box_pkg::*; - - // -------------------------------------------------------------------- - // - tb_dut_if #(dut_cfg) dut_bus(.*); - - // -------------------------------------------------------------------- - // - axis_gear_box - dut - ( - .axis_in(dut_bus.axis_in), - .axis_out(dut_bus.axis_out), - .aclk(dut_bus.aclk), - .aresetn(dut_bus.aresetn) - ); - - // -------------------------------------------------------------------- - // - assign dut_bus.axis_out.tready = 1; - - // -------------------------------------------------------------------- - // - tb_dut_config #(dut_cfg) cfg_h; - - initial - begin - cfg_h = new(dut_bus); - uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h); - run_test("t_debug"); - end - -// -------------------------------------------------------------------- -// -endmodule Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (nonexistent) @@ -1,139 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -package tb_axis_gear_box_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import axis_pkg::*; - - // -------------------------------------------------------------------- - // - typedef struct - { - axis_config_t axis_cfg_in; - axis_config_t axis_cfg_out; - } dut_config_t; - - localparam dut_config_t dut_cfg = - '{ - '{ N : 2 // data bus width in bytes. - , I : 1 // TID width - , D : 1 // TDEST width - , U : 1 // TUSER width - , USE_TSTRB : 0 - , USE_TKEEP : 0 - , USE_ROUTING : 0 - }, - '{ N : 2 // data bus width in bytes. - , I : 1 // TID width - , D : 1 // TDEST width - , U : 1 // TUSER width - , USE_TSTRB : 0 - , USE_TKEEP : 0 - , USE_ROUTING : 0 - } - }; - - // -------------------------------------------------------------------- - // - class tb_dut_config #(dut_config_t dut_cfg); - - virtual tb_dut_if #(dut_cfg) dut_bus; - - // -------------------------------------------------------------------- - // - function new(virtual tb_dut_if #(dut_cfg) dut_bus); - this.dut_bus = dut_bus; - endfunction : new - - // -------------------------------------------------------------------- - // - endclass : tb_dut_config - - // -------------------------------------------------------------------- - // - class tb_env extends uvm_env; - `uvm_component_utils(tb_env); - - // -------------------------------------------------------------------- - // - // coverage coverage_h; - // scoreboard scoreboard_h; - axis_agent #(dut_cfg.axis_cfg_in) agent_h; - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - function void build_phase(uvm_phase phase); - tb_dut_config #(dut_cfg) cfg_h; - if (!uvm_config_db#(tb_dut_config #(dut_cfg))::get(this, "", "tb_dut_config", cfg_h)) - `uvm_fatal(get_name(), "Couldn't get config object!") - - uvm_config_db - #( - virtual axis_if - #( .N(dut_cfg.axis_cfg_in.N) - , .I(dut_cfg.axis_cfg_in.I) - , .D(dut_cfg.axis_cfg_in.D) - , .U(dut_cfg.axis_cfg_in.U) - ) - )::set(this, "*agent_h", "axis_bus", cfg_h.dut_bus.axis_in); - - // // analysis - // coverage_h = coverage::type_id::create ("coverage_h",this); - // scoreboard_h = scoreboard::type_id::create("scoreboard",this); - - agent_h = axis_agent #(dut_cfg.axis_cfg_in)::type_id::create("agent_h", this); - - endfunction : build_phase - - // // -------------------------------------------------------------------- - // // - // function void connect_phase(uvm_phase phase); - - // endfunction : connect_phase - -// -------------------------------------------------------------------- -// -endclass : tb_env - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_gear_box_pkg - - - - - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# # log all signals -# log -r * - Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv (nonexistent) @@ -1,196 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package tests_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import axis_pkg::*; - import tb_axis_gear_box_pkg::*; - import tests_base_pkg::*; - - // -------------------------------------------------------------------- - // - class t_counting extends test_base; - `uvm_component_utils(t_counting) - - // -------------------------------------------------------------------- - // - function new(string name = "my_test", uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - virtual function void end_of_elaboration_phase(uvm_phase phase); - uvm_phase run_phase = uvm_run_phase::get(); - run_phase.phase_done.set_drain_time(this, 300ns); - endfunction - - // -------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - axis_counting_sequence #(dut_cfg.axis_cfg_in) seq_h; - super.run_phase(phase); - phase.raise_objection(this); - fork - repeat(3) - begin - seq_h = axis_counting_sequence #(dut_cfg.axis_cfg_in)::type_id::create("seq_h"); - seq_h.start(env_h.agent_h.sequencer); - end - join - phase.drop_objection(this); - endtask : run_phase - - // -------------------------------------------------------------------- - // - endclass : t_counting - // -------------------------------------------------------------------- - // - - // -------------------------------------------------------------------- - // - class gear_box_sequence #(dut_config_t dut_cfg) - extends uvm_sequence #(axis_sequence_item #(dut_cfg.axis_cfg_in)); - `uvm_object_param_utils(gear_box_sequence #(dut_cfg)) - - rand int length = 7 * 3; - - // -------------------------------------------------------------------- - // - typedef logic [15:0] packed_data_t[7]; - - function packed_data_t next_data(int init); - static logic [15:0] previous_value; - logic [13:0] unpacked_data[8]; - logic [15:0] packed_data[7]; - - if(init == 0) - previous_value = 0; - - foreach(unpacked_data[i]) - begin - unpacked_data[i] = previous_value; - // $display("^^^ %16.t | unpacked_data[%0.d] = %h", $time, i, unpacked_data[i]); - previous_value++; - end - - packed_data = {<<16{{<<14{unpacked_data}}}}; - - // $display("^^^ %16.t | %p", $time, packed_data); - - // foreach(packed_data[i]) - // $display("^^^ %16.t | packed_data[%0.d] = %h", $time, i, packed_data[i]); - - next_data = packed_data; - endfunction - - - // -------------------------------------------------------------------- - // - virtual task body(); - localparam CHUNKS = 3; - axis_sequence_item #(dut_cfg.axis_cfg_in) item; - logic [15:0] data[7]; - - item = axis_sequence_item #(dut_cfg.axis_cfg_in)::type_id::create("axis_sequence_item"); - - for(int i = 0; i < CHUNKS; i++) - begin - data = next_data(i); - - foreach(data[k]) - begin - start_item(item); - item.tdata = data[k]; - item.tlast = (i == CHUNKS - 1) & (k == 0); - item.tuser = 0; - finish_item(item); - // $display("^^^ %16.t | %d | %x", $time, (i * 7) + k, item.tdata); - end - end - - endtask - - // -------------------------------------------------------------------- - // - function new(string name = "gear_box_sequence"); - super.new(name); - endfunction - - // -------------------------------------------------------------------- - // - endclass : gear_box_sequence - - // -------------------------------------------------------------------- - // - class t_debug extends test_debug_base; - `uvm_component_utils(t_debug) - - // -------------------------------------------------------------------- - // - function new(string name = "t_debug", uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - function void end_of_elaboration_phase(uvm_phase phase); - uvm_phase run_phase = uvm_run_phase::get(); - run_phase.phase_done.set_drain_time(this, 300ns); - endfunction - - // -------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - gear_box_sequence #(dut_cfg) seq_h; - super.run_phase(phase); - phase.raise_objection(this); - - fork - repeat(3) - begin - seq_h = gear_box_sequence #(dut_cfg)::type_id::create("seq_h"); - seq_h.start(env_h.agent_h.sequencer); - end - join - - phase.drop_objection(this); - endtask : run_phase - - // -------------------------------------------------------------------- - // - endclass : t_debug - -// -------------------------------------------------------------------- -// -endpackage: tests_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv (revision 49) @@ -0,0 +1,328 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package axis_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import bfm_pkg::*; + + // -------------------------------------------------------------------- + // + typedef struct + { + int unsigned N; // data bus width in bytes + int unsigned I; // TID width + int unsigned D; // TDEST width + int unsigned U; // TUSER width + bit USE_TSTRB; // set to 1 to enable, 0 to disable + bit USE_TKEEP; // set to 1 to enable, 0 to disable + bit USE_ROUTING; // set to 1 to enable, 0 to disable + } axis_config_t; + + // -------------------------------------------------------------------- + // + class axis_sequence_item #(axis_config_t cfg) + extends uvm_sequence_item; + `uvm_object_param_utils(axis_sequence_item #(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + delay_class delay_h; + rand logic [(8*N)-1:0] tdata; + rand logic [N-1:0] tstrb; + rand logic [N-1:0] tkeep; + rand logic tlast; + rand logic [I-1:0] tid; + rand logic [D-1:0] tdest; + rand logic [U-1:0] tuser; + + // -------------------------------------------------------------------- + // + function new(string name = ""); + super.new(name); + delay_h = new; + endfunction : new + + // -------------------------------------------------------------------- + // + function bit do_compare(uvm_object rhs, uvm_comparer comparer); + axis_sequence_item #(cfg) tested; + bit same; + + if (rhs==null) + `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer"); + + if (!$cast(tested,rhs)) + same = 0; + else + same = super.do_compare(rhs, comparer) + & (tested.tdata == tdata) + & (USE_TSTRB ? (tested.tstrb == tstrb) : 1) + & (USE_TKEEP ? (tested.tkeep == tkeep) : 1) + & (tested.tlast == tlast) + & (USE_ROUTING ? (tested.tid == tid) : 1) + & (USE_ROUTING ? (tested.tdest == tdest) : 1) + & (tested.tuser == tuser); + return same; + endfunction : do_compare + + // -------------------------------------------------------------------- + // + function void do_copy(uvm_object rhs); + axis_sequence_item #(cfg) item; + assert(rhs != null) else + `uvm_fatal(get_type_name(), "| %m | copy null transaction"); + super.do_copy(rhs); + assert($cast(item,rhs)) else + `uvm_fatal(get_type_name(), "| %m | failed cast"); + tdata = item.tdata; + tstrb = item.tstrb; + tkeep = item.tkeep; + tlast = item.tlast; + tid = item.tid; + tdest = item.tdest; + tuser = item.tuser; + endfunction : do_copy + + // -------------------------------------------------------------------- + // + function string convert2string(); + string s0, s1; + s0 = $sformatf("| tdata: %h\n" ,tdata); + s1 = $sformatf("| tlast: %1h | tuser: %h" , tlast, tuser); + return {s1, s0}; + endfunction : convert2string + + // -------------------------------------------------------------------- + // + endclass : axis_sequence_item + + // -------------------------------------------------------------------- + // + class axis_driver #(parameter axis_config_t cfg) + extends uvm_driver #(axis_sequence_item #(cfg)); + `uvm_component_param_utils(axis_driver#(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; + + //-------------------------------------------------------------------- + // + function void set_default; + axis_bus.cb_m.tvalid <= 0; + axis_bus.cb_m.tdata <= 'bx; + axis_bus.cb_m.tstrb <= 'bx; + axis_bus.cb_m.tkeep <= 'bx; + axis_bus.cb_m.tlast <= 'bx; + axis_bus.cb_m.tid <= 'bx; + axis_bus.cb_m.tdest <= 'bx; + axis_bus.cb_m.tuser <= 'bx; + endfunction: set_default + + //-------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + axis_sequence_item #(cfg) item; + super.run_phase(phase); + + set_default(); + wait(~axis_bus.aresetn); + @(axis_bus.cb_m); + + forever + begin + // seq_item_port.try_next_item(item); + seq_item_port.get_next_item(item); + + axis_bus.cb_m.tvalid <= 1; + axis_bus.cb_m.tdata <= item.tdata; + axis_bus.cb_m.tstrb <= 0; + axis_bus.cb_m.tkeep <= 0; + axis_bus.cb_m.tlast <= item.tlast; + axis_bus.cb_m.tid <= 0; + axis_bus.cb_m.tdest <= 0; + axis_bus.cb_m.tuser <= item.tuser; + + @(axis_bus.cb_m); + wait(axis_bus.cb_m.tready); + // @(axis_bus.cb_m iff axis_bus.cb_m.tready); + + set_default(); + repeat(item.delay_h.next()) @(axis_bus.cb_m); + + seq_item_port.item_done(); + end + endtask : run_phase + + //-------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_driver + + // -------------------------------------------------------------------- + // + class axis_sequencer #(axis_config_t cfg) + extends uvm_sequencer #(axis_sequence_item #(cfg)); + `uvm_component_param_utils(axis_sequencer #(cfg)) + + // -------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_sequencer + + // -------------------------------------------------------------------- + // + class axis_counting_sequence #(axis_config_t cfg) + extends uvm_sequence #(axis_sequence_item #(cfg)); + `uvm_object_param_utils(axis_counting_sequence #(cfg)) + + rand int length = 16; + + // -------------------------------------------------------------------- + // + virtual task body(); + axis_sequence_item #(cfg) item; + + for(int i = 0; i < length; i++) + begin + item = axis_sequence_item #(cfg)::type_id::create("axis_sequence_item"); + + item.tdata = i; + item.tlast = (i == length - 1); + + start_item (item); + finish_item(item); + end + endtask + + // -------------------------------------------------------------------- + // + function new(string name = "axis_counting_sequence"); + super.new(name); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_counting_sequence + + // -------------------------------------------------------------------- + // + class axis_agent #(axis_config_t cfg) + extends uvm_agent; + `uvm_component_param_utils(axis_agent #(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; + + axis_driver #(cfg) driver; + // my_monitor #(cfg) monitor; + axis_sequencer #(cfg) sequencer; + + // -------------------------------------------------------------------- + // + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if(!uvm_config_db #(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)))::get(this, "", "axis_bus", axis_bus)) + `uvm_fatal(get_name(), "Couldn't get virtual interface!") + + driver = axis_driver #(cfg)::type_id::create("driver", this); + // monitor = my_monitor #(cfg)::type_id::create("monitor" , this); + sequencer = axis_sequencer #(cfg)::type_id::create("sequencer", this); + endfunction + + // -------------------------------------------------------------------- + // + virtual function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + driver.axis_bus = axis_bus; + // monitor.vif = vif; + + driver.seq_item_port.connect(sequencer.seq_item_export); + endfunction + + // -------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_agent + +// -------------------------------------------------------------------- +// +endpackage: axis_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do (revision 49) @@ -0,0 +1,42 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_gear_box + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# AXI4 streaming package +vlog ./axis_pkg.sv + +vlog ./$env(SIM_TB)_pkg.sv +vlog ./tests_base_pkg.sv +vlog ./tests_pkg.sv +vlog ./tb_dut_if.sv + +# simulation $root +vlog ./$env(SIM_TB).sv + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# # compile test last +# vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f (revision 49) @@ -0,0 +1,6 @@ +# + +./axis_pkg.sv + +${PROJECT_DIR}/src/axis_gear_box.sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv (revision 49) @@ -0,0 +1,90 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + +import tb_axis_gear_box_pkg::*; +import tests_pkg::*; +import uvm_pkg::*; +`include "uvm_macros.svh" + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + // -------------------------------------------------------------------- + // + import tb_axis_gear_box_pkg::*; + + // -------------------------------------------------------------------- + // + tb_dut_if #(dut_cfg) dut_bus(.*); + + // -------------------------------------------------------------------- + // + axis_gear_box + dut + ( + .axis_in(dut_bus.axis_in), + .axis_out(dut_bus.axis_out), + .aclk(dut_bus.aclk), + .aresetn(dut_bus.aresetn) + ); + + // -------------------------------------------------------------------- + // + assign dut_bus.axis_out.tready = 1; + + // -------------------------------------------------------------------- + // + tb_dut_config #(dut_cfg) cfg_h; + + initial + begin + cfg_h = new(dut_bus); + uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h); + run_test("t_debug"); + end + +// -------------------------------------------------------------------- +// +endmodule Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (revision 49) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +package tb_axis_gear_box_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import axis_pkg::*; + + // -------------------------------------------------------------------- + // + typedef struct + { + axis_config_t axis_cfg_in; + axis_config_t axis_cfg_out; + } dut_config_t; + + localparam dut_config_t dut_cfg = + '{ + '{ N : 2 // data bus width in bytes. + , I : 1 // TID width + , D : 1 // TDEST width + , U : 1 // TUSER width + , USE_TSTRB : 0 + , USE_TKEEP : 0 + , USE_ROUTING : 0 + }, + '{ N : 2 // data bus width in bytes. + , I : 1 // TID width + , D : 1 // TDEST width + , U : 1 // TUSER width + , USE_TSTRB : 0 + , USE_TKEEP : 0 + , USE_ROUTING : 0 + } + }; + + // -------------------------------------------------------------------- + // + class tb_dut_config #(dut_config_t dut_cfg); + + virtual tb_dut_if #(dut_cfg) dut_bus; + + // -------------------------------------------------------------------- + // + function new(virtual tb_dut_if #(dut_cfg) dut_bus); + this.dut_bus = dut_bus; + endfunction : new + + // -------------------------------------------------------------------- + // + endclass : tb_dut_config + + // -------------------------------------------------------------------- + // + class tb_env extends uvm_env; + `uvm_component_utils(tb_env); + + // -------------------------------------------------------------------- + // + // coverage coverage_h; + // scoreboard scoreboard_h; + axis_agent #(dut_cfg.axis_cfg_in) agent_h; + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + function void build_phase(uvm_phase phase); + tb_dut_config #(dut_cfg) cfg_h; + if (!uvm_config_db#(tb_dut_config #(dut_cfg))::get(this, "", "tb_dut_config", cfg_h)) + `uvm_fatal(get_name(), "Couldn't get config object!") + + uvm_config_db + #( + virtual axis_if + #( .N(dut_cfg.axis_cfg_in.N) + , .I(dut_cfg.axis_cfg_in.I) + , .D(dut_cfg.axis_cfg_in.D) + , .U(dut_cfg.axis_cfg_in.U) + ) + )::set(this, "*agent_h", "axis_bus", cfg_h.dut_bus.axis_in); + + // // analysis + // coverage_h = coverage::type_id::create ("coverage_h",this); + // scoreboard_h = scoreboard::type_id::create("scoreboard",this); + + agent_h = axis_agent #(dut_cfg.axis_cfg_in)::type_id::create("agent_h", this); + + endfunction : build_phase + + // // -------------------------------------------------------------------- + // // + // function void connect_phase(uvm_phase phase); + + // endfunction : connect_phase + +// -------------------------------------------------------------------- +// +endclass : tb_env + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_gear_box_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv (revision 49) @@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +import tb_axis_gear_box_pkg::*; + +interface + tb_dut_if #(dut_config_t dut_cfg) + ( + input aclk, + input aresetn + ); + + // -------------------------------------------------------------------- + // + axis_if + #( + .N(dut_cfg.axis_cfg_in.N), + .I(dut_cfg.axis_cfg_in.I), + .D(dut_cfg.axis_cfg_in.D), + .U(dut_cfg.axis_cfg_in.U) + ) + axis_in(.*); + + // -------------------------------------------------------------------- + // + axis_if + #( + .N(dut_cfg.axis_cfg_out.N), + .I(dut_cfg.axis_cfg_out.I), + .D(dut_cfg.axis_cfg_out.D), + .U(dut_cfg.axis_cfg_out.U) + ) + axis_out(.*); + +// -------------------------------------------------------------------- +// +endinterface: tb_dut_if + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv (revision 49) @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package tests_base_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import tb_axis_gear_box_pkg::*; + + // -------------------------------------------------------------------- + // + virtual class test_base extends uvm_test; + `uvm_component_utils(test_base); + tb_env env_h; + + // -------------------------------------------------------------------- + // + function void build_phase(uvm_phase phase); + env_h = tb_env::type_id::create("env_h",this); + endfunction : build_phase + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + endclass : test_base + + // -------------------------------------------------------------------- + // + class test_debug_base extends test_base; + `uvm_component_utils(test_debug_base) + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + function void final_phase(uvm_phase phase); + super.final_phase(phase); + $display("^^^ %16.t | %m | Test Done!!!", $time); + $stop; + endfunction : final_phase + + // -------------------------------------------------------------------- + // + endclass : test_debug_base + +// -------------------------------------------------------------------- +// +endpackage: tests_base_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv (revision 49) @@ -0,0 +1,196 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package tests_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import axis_pkg::*; + import tb_axis_gear_box_pkg::*; + import tests_base_pkg::*; + + // -------------------------------------------------------------------- + // + class t_counting extends test_base; + `uvm_component_utils(t_counting) + + // -------------------------------------------------------------------- + // + function new(string name = "my_test", uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + virtual function void end_of_elaboration_phase(uvm_phase phase); + uvm_phase run_phase = uvm_run_phase::get(); + run_phase.phase_done.set_drain_time(this, 300ns); + endfunction + + // -------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + axis_counting_sequence #(dut_cfg.axis_cfg_in) seq_h; + super.run_phase(phase); + phase.raise_objection(this); + fork + repeat(3) + begin + seq_h = axis_counting_sequence #(dut_cfg.axis_cfg_in)::type_id::create("seq_h"); + seq_h.start(env_h.agent_h.sequencer); + end + join + phase.drop_objection(this); + endtask : run_phase + + // -------------------------------------------------------------------- + // + endclass : t_counting + // -------------------------------------------------------------------- + // + + // -------------------------------------------------------------------- + // + class gear_box_sequence #(dut_config_t dut_cfg) + extends uvm_sequence #(axis_sequence_item #(dut_cfg.axis_cfg_in)); + `uvm_object_param_utils(gear_box_sequence #(dut_cfg)) + + rand int length = 7 * 3; + + // -------------------------------------------------------------------- + // + typedef logic [15:0] packed_data_t[7]; + + function packed_data_t next_data(int init); + static logic [15:0] previous_value; + logic [13:0] unpacked_data[8]; + logic [15:0] packed_data[7]; + + if(init == 0) + previous_value = 0; + + foreach(unpacked_data[i]) + begin + unpacked_data[i] = previous_value; + // $display("^^^ %16.t | unpacked_data[%0.d] = %h", $time, i, unpacked_data[i]); + previous_value++; + end + + packed_data = {<<16{{<<14{unpacked_data}}}}; + + // $display("^^^ %16.t | %p", $time, packed_data); + + // foreach(packed_data[i]) + // $display("^^^ %16.t | packed_data[%0.d] = %h", $time, i, packed_data[i]); + + next_data = packed_data; + endfunction + + + // -------------------------------------------------------------------- + // + virtual task body(); + localparam CHUNKS = 3; + axis_sequence_item #(dut_cfg.axis_cfg_in) item; + logic [15:0] data[7]; + + item = axis_sequence_item #(dut_cfg.axis_cfg_in)::type_id::create("axis_sequence_item"); + + for(int i = 0; i < CHUNKS; i++) + begin + data = next_data(i); + + foreach(data[k]) + begin + start_item(item); + item.tdata = data[k]; + item.tlast = (i == CHUNKS - 1) & (k == 0); + item.tuser = 0; + finish_item(item); + // $display("^^^ %16.t | %d | %x", $time, (i * 7) + k, item.tdata); + end + end + + endtask + + // -------------------------------------------------------------------- + // + function new(string name = "gear_box_sequence"); + super.new(name); + endfunction + + // -------------------------------------------------------------------- + // + endclass : gear_box_sequence + + // -------------------------------------------------------------------- + // + class t_debug extends test_debug_base; + `uvm_component_utils(t_debug) + + // -------------------------------------------------------------------- + // + function new(string name = "t_debug", uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + function void end_of_elaboration_phase(uvm_phase phase); + uvm_phase run_phase = uvm_run_phase::get(); + run_phase.phase_done.set_drain_time(this, 300ns); + endfunction + + // -------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + gear_box_sequence #(dut_cfg) seq_h; + super.run_phase(phase); + phase.raise_objection(this); + + fork + repeat(3) + begin + seq_h = gear_box_sequence #(dut_cfg)::type_id::create("seq_h"); + seq_h.start(env_h.agent_h.sequencer); + end + join + + phase.drop_objection(this); + endtask : run_phase + + // -------------------------------------------------------------------- + // + endclass : t_debug + +// -------------------------------------------------------------------- +// +endpackage: tests_pkg Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do (revision 49) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# # log all signals +# log -r * + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do (revision 49) @@ -0,0 +1,11 @@ +# + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +vlog ./$env(SIM_TB)_pkg.sv +vlog ./tests_pkg.sv + +# simulation $root +vlog ./$env(SIM_TB).sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip (revision 49)
qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (revision 49) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_switch_allocator + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (revision 49) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (revision 49) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/src/axis_switch.sv +${PROJECT_DIR}/src/recursive_axis_switch.sv + +${PROJECT_DIR}/src/axis_switch_allocator.sv Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (revision 49) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_axis_switch_allocator_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); + + + // -------------------------------------------------------------------- + // + axis_switch_allocator #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP), .SA(SA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + tb_axis_switch_allocator_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (revision 49) @@ -0,0 +1,143 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_axis_switch_allocator_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam U_IS_EOP = 2; + localparam SA = 3; + localparam SD = 2 ** SA; + + + // -------------------------------------------------------------------- + // + class tb_axis_switch_allocator_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in, + virtual axis_if #(.N(N), .U(U)) axis_out[] + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, axis_out); + tx_h = new(c_h, '{axis_in}); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_axis_switch_allocator_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_switch_allocator_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (revision 49) @@ -0,0 +1,88 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_axis_switch_allocator_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // // -------------------------------------------------------------------- + // repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // // -------------------------------------------------------------------- + // for(i = 0; i < SD; i++) + // begin + // #1us; + // tb_top.a_h.queue_frame("counting"); + // #8us; + // end + + // -------------------------------------------------------------------- + repeat(SD * 2) tb_top.a_h.queue_frame("counting"); + + // -------------------------------------------------------------------- + #100us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (revision 49) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_catenate + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (revision 49) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (revision 49) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/src/recursive_axis_mux.sv +${PROJECT_DIR}/src/axis_catenate.sv +${PROJECT_DIR}/src/recursive_axis_catenate.sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (revision 49) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_catenate_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); + + + // -------------------------------------------------------------------- + // + recursive_axis_catenate + #( + .N(N), + .I(I), + .D(D), + .U(U), + .U_IS_EOP(U_IS_EOP), + .MA(MA) + ) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_catenate_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (revision 49) @@ -0,0 +1,144 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_catenate_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + // localparam U_IS_EOP = 2; + localparam U_IS_EOP = -1; + localparam MA = 2; + localparam MD = 2 ** MA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_catenate_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in[], + virtual axis_if #(.N(N), .U(U)) axis_out + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, '{axis_out}); + tx_h = new(c_h, axis_in); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_catenate_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_catenate_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (revision 49) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_catenate_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // -------------------------------------------------------------------- + repeat(10)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // // -------------------------------------------------------------------- + // for(i = 0; i < MD; i++) + // begin + // force tb_top.select = i; + // #20us; + // end + + // -------------------------------------------------------------------- + #100us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (revision 49) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_mux + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (revision 49) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (revision 49) @@ -0,0 +1,4 @@ +# + +${PROJECT_DIR}/src/recursive_axis_mux.sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (revision 49) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_mux_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); + + + // -------------------------------------------------------------------- + // + wire [MA-1:0] select = 0; + + recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + initial + axis_out.cb_s.tready <= 1; + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_mux_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (revision 49) @@ -0,0 +1,142 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_mux_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam MA = 5; + localparam MD = 2 ** MA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_mux_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in[], + virtual axis_if #(.N(N), .U(U)) axis_out + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, '{axis_out}); + tx_h = new(c_h, axis_in); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_mux_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_mux_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (revision 49) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_mux_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + // tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // -------------------------------------------------------------------- + repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // -------------------------------------------------------------------- + for(i = 0; i < MD; i++) + begin + force tb_top.select = i; + #20us; + end + + // -------------------------------------------------------------------- + #10us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (revision 49) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_switch + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (revision 49) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (revision 49) @@ -0,0 +1,5 @@ +# + +${PROJECT_DIR}/src/axis_switch.sv +${PROJECT_DIR}/src/recursive_axis_switch.sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (revision 49) @@ -0,0 +1,127 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_switch_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); + + + // -------------------------------------------------------------------- + // + wire [SA-1:0] select = 0; + + recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // // -------------------------------------------------------------------- + // // + // initial + // axis_out.cb_s.tready <= 1; + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_switch_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (revision 49) @@ -0,0 +1,142 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_switch_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam SA = 2; + localparam SD = 2 ** SA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_switch_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in, + virtual axis_if #(.N(N), .U(U)) axis_out[] + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, axis_out); + tx_h = new(c_h, '{axis_in}); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_switch_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_switch_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (revision 49) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_switch_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // // -------------------------------------------------------------------- + // repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // -------------------------------------------------------------------- + for(i = 0; i < SD; i++) + begin + force tb_top.select = i; + #1us; + tb_top.a_h.queue_frame("counting"); + #8us; + end + + // -------------------------------------------------------------------- + #5us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do (revision 49) @@ -0,0 +1,34 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_to_axi4_basic_dma + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all tb_packages +sim_compile_all bfm_packages +sim_compile_all axi4_lib +sim_compile_all qaz_lib +sim_compile_all sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do (revision 49) @@ -0,0 +1,13 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top + +# log all signals +log -r * + +# run -all + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (revision 49) @@ -0,0 +1,12 @@ +# + +${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv +${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv + +${PROJECT_DIR}/sim/src/tb_axis_to_axi4_agent_class_pkg.sv + +${PROJECT_DIR}/src/axis_to_axi4_basic_dma.sv + +./${SIM_TB}_pkg.sv +./${SIM_TB}.sv + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (revision 49) @@ -0,0 +1,115 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_200mhz; + wire tb_clk = clk_200mhz; + wire tb_rst; + + tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + + sync_reset + sync_reset_i(aclk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_basic_dma_pkg::*; + + + // -------------------------------------------------------------------- + // + axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + + + // -------------------------------------------------------------------- + // + logic dma_enable = 0; + + axis_to_axi4_basic_dma + #( + .A(A), + .N(N), + .I(I), + .BASE_ADDRESS(BASE_ADDRESS), + .BUFFER_SIZE(BUFFER_SIZE), + .BURST_LENGTH(BURST_LENGTH), + .MAX_BURSTS(MAX_BURSTS), + .BYTES_PER_TUSER(BYTES_PER_TUSER) + ) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + axi4_checker #(.A(A), .N(N), .MAXWAITS(64)) + axi4_checker_i(.axi4_in(axi4_m)); + + + // -------------------------------------------------------------------- + // + axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64)) + axis_checker_i(.axis_in(axis_in)); + + + // -------------------------------------------------------------------- + // + tb_axis_to_axi4_basic_dma_class a_h; + + initial + a_h = new(axi4_m, axis_in); + + + // -------------------------------------------------------------------- + // + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (revision 49) @@ -0,0 +1,58 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + + +package tb_axis_to_axi4_basic_dma_pkg; + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam BASE_ADDRESS = 32'h0000_0000; // must be on 4K boundry + localparam BUFFER_SIZE = 'h800; + localparam BURST_LENGTH = 8'h08; + localparam MAX_BURSTS = 4; + localparam BYTES_PER_TUSER = 2; // bytes per tuser bit. Set to 0 for transfer based. + + localparam N = 8; // data bus width in bytes + localparam A = 32; // address bus width + localparam I = 1; // ID width + localparam D = 1; // TDEST width + localparam U = N / BYTES_PER_TUSER; // TUSER width + + + // -------------------------------------------------------------------- + // + class tb_axis_to_axi4_basic_dma_class + extends tb_axis_to_axi4_agent_class #(N, A, I, D, U); + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in + ); + + super.new(.axi4_m(axi4_m), .axis_in(axis_in)); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_axis_to_axi4_basic_dma_class + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_to_axi4_basic_dma_pkg + + + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv (revision 49) @@ -0,0 +1,60 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_basic_dma_pkg::*; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(50us); + + // -------------------------------------------------------------------- + wait(tb_top.aresetn); + #200ns; + + // -------------------------------------------------------------------- + force tb_top.dma_enable = 1; + #100ns; + + // -------------------------------------------------------------------- + repeat(8) + begin + tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE, N * BURST_LENGTH); + tb_top.a_h.compare(BASE_ADDRESS); + end + + // -------------------------------------------------------------------- + #200ns; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + +// -------------------------------------------------------------------- +// +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do (revision 49) @@ -0,0 +1,11 @@ +# + +vlog -f ./tb_axis_to_axi4_basic_dma.f + +# simulation $root +vlog ./tb_axis_to_axi4_basic_dma.sv + +# compile test last +vlog ./the_test.sv + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do (revision 49) @@ -0,0 +1,37 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all tb_packages +sim_compile_all bfm_packages +sim_compile_all axi4_lib +sim_compile_all qaz_libs +sim_compile_all sim +vlog -f ./tb_axis_upsizer.f + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_axis_upsizer.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do (revision 49) @@ -0,0 +1,16 @@ +# +# + + +quit -sim + +# vsim opt_tb_top +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# log all signals +log -r * + +# run -all + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f (revision 49) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/sim/src/tb_axis_upsizer_agent_class_pkg.sv +${PROJECT_DIR}/sim/src/tb_axis_upsizer_class_pkg.sv + +${PROJECT_DIR}/src/axis_upsizer.sv Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv (revision 49) @@ -0,0 +1,98 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int mismatch_count = 0; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(50us); + + + // -------------------------------------------------------------------- + wait(tb_top.aresetn); + #1us; + + // -------------------------------------------------------------------- + repeat(3) tb_top.a_h.queue_frame("counting"); + repeat(3) tb_top.a_h.compare_frame(); + + // -------------------------------------------------------------------- + tb_top.a_h.tx_h.make_frame("constant", 16'habba); + tb_top.a_h.queue_frame(); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("random"); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("constant", 16'hbeef); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("random"); + tb_top.a_h.rx_h.wait_for_rx_frames(1); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("counting"); + tb_top.a_h.compare_frame(); + + repeat(3) tb_top.a_h.queue_frame("random"); + repeat(3) tb_top.a_h.compare_frame(); + + // -------------------------------------------------------------------- + #1us; + // #6us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do (revision 49) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +# sim_compile_all FPGA +sim_compile_all sim +sim_compile_all sync_fifo +sim_compile_all axi4_stream_lib + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_axis_register_slice.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do (revision 49) @@ -0,0 +1,21 @@ +# +# + + +quit -sim + +# vsim opt_tb_top + +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top +# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + + +# # log all signals +# log -r * + +# run -all + + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv (revision 49) @@ -0,0 +1,79 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int mismatch_count = 0; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + // -------------------------------------------------------------------- + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(4us); + wait(~tb_rst); + + + // -------------------------------------------------------------------- + repeat(100) @(posedge tb_clk); + tb_top.avf_agent_h.make_frame("counting"); + tb_top.avf_agent_h.get_frame(); + tb_top.avf_agent_h.put_frame(); + + wait(~tb_top.avf_agent_h.put_frame_active); + wait(~tb_top.avf_agent_h.get_frame_active); + + mismatch_count = tb_top.avf_agent_h.compare_frame(); + + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do =================================================================== --- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do (revision 49) @@ -0,0 +1,12 @@ +# + + +vlog -f ../../libs/axi4_stream_lib_verilog/axi4_stream_lib.f + +# simulation $root +vlog ../../src/tb_axis_register_slice.sv + +# compile test last +vlog ./the_test.sv + + Index: qaz_libs/trunk/axi4_stream_lib/src/axis_to_memory.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/src/axis_to_memory.sv (revision 50) +++ qaz_libs/trunk/axi4_stream_lib/src/axis_to_memory.sv (nonexistent) @@ -1,129 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2019 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -module - axis_to_memory - #( - W, // data width in bits - A, // address width in bits - P = 1 // pipeline delay - ) - ( - axis_if axis_ar, - axis_if axis_r, - output wr, - output [A-1:0] addr, - output [W-1:0] din, - input [W-1:0] dout, - input aclk, - input aresetn - ); - - // -------------------------------------------------------------------- - localparam CW = ($clog2(P) == 0) ? 1 : $clog2(P); - localparam D = 2 ** CW; - localparam UB = $clog2(D); - - // -------------------------------------------------------------------- - reg [P-1:0] pipeline; - wire ar = axis_ar.tready & axis_ar.tvalid; - wire rd_ready = pipeline[0]; - wire bypass; - - generate - if(P > 1) begin: pipeline_gen - always_ff @(posedge aclk) - if(~aresetn) - pipeline <= 0; - else - pipeline <= {ar, pipeline[P-1:1]}; - end - else begin: min_pipeline_gen // P == 1 - always_ff @(posedge aclk) - if(~aresetn) - pipeline <= 0; - else - pipeline <= ar; - end - endgenerate - - // -------------------------------------------------------------------- - wire wr_full; - wire [W-1:0] wr_data = dout; - wire wr_en = bypass ? 0 : rd_ready; - wire rd_empty; - wire [W-1:0] rd_data; - wire rd_en = axis_r.tready & axis_r.tvalid & ~bypass; - wire [UB:0] count; - - sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*); - - // -------------------------------------------------------------------- - // assign bypass = rd_empty & (count != 0) & rd_ready; - assign bypass = 0; - - // // -------------------------------------------------------------------- - // logic [$clog2($bits(pipeline)+1)-1:0] in_pipeline; - - // always_comb begin - // in_pipeline = '0; - - // foreach(pipeline[idx]) begin - // in_pipeline += pipeline[idx]; - // end - // end - - // -------------------------------------------------------------------- - reg [$clog2($bits(pipeline)+1)-1:0] pipeline_count; - reg [$clog2($bits(pipeline)+1)-1:0] next_pipeline_count; - - always_comb - case({rd_ready, ar}) - 2'b0_0: next_pipeline_count = pipeline_count; - 2'b0_1: next_pipeline_count = pipeline_count + 1; - 2'b1_0: next_pipeline_count = pipeline_count - 1; - 2'b1_1: next_pipeline_count = pipeline_count; - endcase - - always_ff @(posedge aclk) - if(~aresetn) - pipeline_count <= 0; - else - pipeline_count <= next_pipeline_count; - - // -------------------------------------------------------------------- - assign axis_ar.tready = (pipeline_count + count < D) | rd_en; - assign axis_r.tdata = bypass ? dout : rd_data; - assign axis_r.tlast = 1; - assign axis_r.tvalid = ~rd_empty | bypass; - - // -------------------------------------------------------------------- - assign wr = 0; - // assign addr = axis_ar.tdata; - -// -------------------------------------------------------------------- -endmodule Index: qaz_libs/trunk/axi4_stream_lib/src/data_to_axis_fsm.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/src/data_to_axis_fsm.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/src/data_to_axis_fsm.sv (revision 49) @@ -0,0 +1,106 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module + data_to_axis_fsm + ( + input axis_en, + output axis_tvalid, + input axis_tready, + + input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also + input fifo_empty, + output fifo_rd_en, + + output data_to_axis_fsm_error, + + input aclk, + input aresetn + ); + + //--------------------------------------------------- + // state machine binary definitions + enum reg [3:0] { + IDLE_STATE = 4'b0001, + TVALID = 4'b0010, + TREADY = 4'b0100, + ERROR_STATE = 4'b1000 + } state, next_state; + + + //--------------------------------------------------- + // state machine flop + always_ff @(posedge aclk) + if(~aresetn) + state <= IDLE_STATE; + else + state <= next_state; + + + //--------------------------------------------------- + // state machine + always_comb + case(state) + IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) + if(axis_tready) + next_state <= TREADY; + else + next_state <= TVALID; + else + next_state <= IDLE_STATE; + + TVALID: if(axis_tready) // wait for slave to be ready + next_state <= TREADY; + else + next_state <= TVALID; + + TREADY: if(fifo_empty) // slave can accept data + next_state <= IDLE_STATE; + else if(axis_tready) + next_state <= TREADY; + else + next_state <= TVALID; + + ERROR_STATE: next_state <= IDLE_STATE; + + default: next_state <= ERROR_STATE; + + endcase + + + //--------------------------------------------------- + // outputs + assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); + assign fifo_rd_en = axis_tvalid & axis_tready; + assign data_to_axis_fsm_error = (state == ERROR_STATE); + + +endmodule + + + Index: qaz_libs/trunk/axi4_stream_lib/src/axis_flow_control.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/src/axis_flow_control.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/src/axis_flow_control.sv (revision 49) @@ -0,0 +1,127 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module + axis_flow_control + #( + N = 8, // data bus width in bytes + I = 0, // TID width + D = 0, // TDEST width + U = 1, // TUSER width + USE_TSTRB = 0, // set to 1 to enable, 0 to disable + USE_TKEEP = 0 // set to 1 to enable, 0 to disable + ) + ( + input axis_en, + input flow_enable, // enable / disable incoming tready & tvalid + input [1:0] tready_to_master_select, // 00:force 0, 01:force 1, 1X:from_slave + input [1:0] tvalid_to_master_select, // 00:force 0, 01:force 1, 1X:from_slave + output tready_from_slave, // from input of mux + output tvalid_from_slave, // from input of mux + axis_if.slave axis_in, + axis_if.master axis_out, + input aclk, + input aresetn + ); + + // -------------------------------------------------------------------- + // + localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1; + + fifo_write_if #(.W(W)) fifo_sink(aclk, ~aresetn); + fifo_read_if #(.W(W)) fifo_source(aclk, ~aresetn); + + tiny_sync_fifo #(.W(W)) + tiny_sync_fifo_i(.source(fifo_sink.fifo), .sink(fifo_source.fifo)); + + + // -------------------------------------------------------------------- + // + wire data_to_axis_fsm_error; + + data_to_axis_fsm + data_to_axis_fsm_i + ( + .axis_tvalid(tvalid_from_slave), // axis_out.tvalid + .axis_tready(flow_enable & axis_out.tready), + .fifo_empty(fifo_source.empty), + .fifo_rd_en(fifo_source.rd_en), + .fifo_watermark(1'b1), + .* + ); + + + // -------------------------------------------------------------------- + // + reg axis_in_tready_r; + assign axis_in.tready = axis_in_tready_r; + + always_comb + case(tready_to_master_select) + 2'b00: axis_in_tready_r = 0; + 2'b01: axis_in_tready_r = 1; + 2'b10: axis_in_tready_r = tready_from_slave; + 2'b11: axis_in_tready_r = tready_from_slave; + endcase + + + // -------------------------------------------------------------------- + // + reg axis_out_tvalid_r; + assign axis_out.tvalid = axis_out_tvalid_r; + + always_comb + case(tvalid_to_master_select) + 2'b00: axis_out_tvalid_r = 0; + 2'b01: axis_out_tvalid_r = 1; + 2'b10: axis_out_tvalid_r = tvalid_from_slave; + 2'b11: axis_out_tvalid_r = tvalid_from_slave; + endcase + + + // -------------------------------------------------------------------- + // + assign tready_from_slave = ~fifo_sink.full; // axis_in.tready + + assign fifo_sink.wr_en = flow_enable & axis_in.tvalid & ~fifo_sink.full; + assign fifo_sink.wr_data = + { + axis_in.tdata, + axis_in.tlast, + axis_in.tuser + }; + + assign + { + axis_out.tdata, + axis_out.tlast, + axis_out.tuser + } = fifo_source.rd_data; + + +endmodule + Index: qaz_libs/trunk/axi4_stream_lib/syn/src/axis_if.sv =================================================================== --- qaz_libs/trunk/axi4_stream_lib/syn/src/axis_if.sv (nonexistent) +++ qaz_libs/trunk/axi4_stream_lib/syn/src/axis_if.sv (revision 49) @@ -0,0 +1,128 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +interface + axis_if + #( + N = 8, // data bus width in bytes + I = 1, // TID width + D = 1, // TDEST width + U = 1 // TUSER width + ) + ( + input aclk, + input aresetn + ); + wire tvalid; + wire tready; + wire [(8*N)-1:0] tdata; + wire [N-1:0] tstrb; + wire [N-1:0] tkeep; + wire tlast; + wire [I-1:0] tid; + wire [D-1:0] tdest; + wire [U-1:0] tuser; + + +// -------------------------------------------------------------------- +// synthesis translate_off + default clocking cb_m @(posedge aclk iff aresetn); + output tvalid; + input tready; + output tdata; + output tstrb; + output tkeep; + output tlast; + output tid; + output tdest; + output tuser; + endclocking + + + // -------------------------------------------------------------------- + // + clocking cb_s @(posedge aclk iff aresetn); + input tvalid; + output tready; + input tdata; + input tstrb; + input tkeep; + input tlast; + input tid; + input tdest; + input tuser; + endclocking + + + // -------------------------------------------------------------------- + // + modport + master + ( + input aresetn, + input aclk, + output tvalid, + input tready, + output tdata, + output tstrb, + output tkeep, + output tlast, + output tid, + output tdest, + output tuser, + clocking cb_m + ); + + + // -------------------------------------------------------------------- + // + modport + slave + ( + input aresetn, + input aclk, + input tvalid, + output tready, + input tdata, + input tstrb, + input tkeep, + input tlast, + input tid, + input tdest, + input tuser, + clocking cb_s + ); + + +// synthesis translate_on +// -------------------------------------------------------------------- + + +endinterface: axis_if + + Index: qaz_libs/trunk/basal/src/FIFOs/sync_fifo.sv =================================================================== --- qaz_libs/trunk/basal/src/FIFOs/sync_fifo.sv (revision 50) +++ qaz_libs/trunk/basal/src/FIFOs/sync_fifo.sv (revision 49) @@ -25,6 +25,7 @@ //// //// ////////////////////////////////////////////////////////////////////// + module sync_fifo #( @@ -36,9 +37,11 @@ output wr_full, input [W-1:0] wr_data, input wr_en, + output rd_empty, output [W-1:0] rd_data, input rd_en, + output [UB:0] count, input clk, input reset @@ -45,21 +48,12 @@ ); // -------------------------------------------------------------------- + // generate begin: fifo_gen if(D == 2) begin - reg [UB:0] count_r; - assign count = count_r; - - always_comb - case({wr_full, rd_empty}) - 2'b0_0: count_r = 1; - 2'b0_1: count_r = 0; - 2'b1_0: count_r = 2; - 2'b1_1: count_r = 'x; // should never happen - endcase - + assign count = 0; tiny_sync_fifo #(.W(W)) tiny_sync_fifo_i(.*); end @@ -79,6 +73,7 @@ end endgenerate + // -------------------------------------------------------------------- // synthesis translate_off always_ff @(posedge clk) @@ -90,5 +85,9 @@ // synthesis translate_on // -------------------------------------------------------------------- + // -------------------------------------------------------------------- +// endmodule + +
/qaz_libs/trunk/basal/src/FIFOs/tiny_async_fifo.sv
0,0 → 1,189
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
tiny_async_fifo
#(
parameter W = 8
)
(
output wr_full,
input [W-1:0] wr_data,
input wr_en,
input wr_clk,
input wr_reset,
 
output rd_empty,
output [W-1:0] rd_data,
input rd_en,
input rd_clk,
input rd_reset
);
 
// --------------------------------------------------------------------
//
wire writing = wr_en && ~wr_full;
wire reading = rd_en && ~rd_empty;
 
 
// --------------------------------------------------------------------
//
function logic [1:0]
grey_counter_2_bit
(
input logic [1:0] count
);
 
case(count)
2'b00: grey_counter_2_bit = 2'b00;
2'b01: grey_counter_2_bit = 2'b01;
2'b10: grey_counter_2_bit = 2'b11;
2'b11: grey_counter_2_bit = 2'b10;
endcase
 
endfunction
 
 
// --------------------------------------------------------------------
// sync grey_wr_ptr to rd clk domain
reg [1:0] grey_wr_ptr;
reg [1:0] grey_wr_ptr_r;
reg [1:0] grey_wr_ptr_s;
 
always_ff @(posedge rd_clk)
if(rd_reset)
{grey_wr_ptr_s, grey_wr_ptr_r} <= 0;
else
{grey_wr_ptr_s, grey_wr_ptr_r} <= {grey_wr_ptr_r, grey_wr_ptr};
 
 
// --------------------------------------------------------------------
// sync grey_rd_ptr to wr clk domain
reg [1:0] grey_rd_ptr;
reg [1:0] grey_rd_ptr_r;
reg [1:0] grey_rd_ptr_s;
 
always_ff @(posedge wr_clk)
if(rd_reset)
{grey_rd_ptr_s, grey_rd_ptr_r} <= 0;
else
{grey_rd_ptr_s, grey_rd_ptr_r} <= {grey_rd_ptr_r, grey_rd_ptr};
 
 
// --------------------------------------------------------------------
//
reg [1:0] bin_rd_ptr;
wire [1:0] bin_rd_ptr_next = bin_rd_ptr + reading;
 
always_ff @(posedge rd_clk)
if(rd_reset)
bin_rd_ptr <= 0;
else
bin_rd_ptr <= bin_rd_ptr_next;
 
 
// --------------------------------------------------------------------
//
wire [1:0] grey_rd_ptr_next = grey_counter_2_bit(bin_rd_ptr_next);
 
always_ff @(posedge rd_clk)
if(rd_reset)
grey_rd_ptr <= 0;
else
grey_rd_ptr <= grey_rd_ptr_next;
 
 
// --------------------------------------------------------------------
//
reg asf_empty_r;
 
always_ff @(posedge rd_clk)
if(rd_reset)
asf_empty_r <= 1;
else
asf_empty_r <= (grey_rd_ptr_next == grey_wr_ptr_s);
 
 
// --------------------------------------------------------------------
//
reg [1:0] bin_wr_ptr;
wire [1:0] bin_wr_ptr_next = bin_wr_ptr + writing;
 
always_ff @(posedge wr_clk)
if(wr_reset)
bin_wr_ptr <= 0;
else
bin_wr_ptr <= bin_wr_ptr_next;
 
 
// --------------------------------------------------------------------
//
wire [1:0] grey_wr_ptr_next = grey_counter_2_bit(bin_wr_ptr_next);
 
always_ff @(posedge wr_clk)
if(wr_reset)
grey_wr_ptr <= 0;
else
grey_wr_ptr <= grey_wr_ptr_next;
 
 
// --------------------------------------------------------------------
//
reg asf_full_r;
 
always_ff @(posedge wr_clk)
if(wr_reset)
asf_full_r <= 1;
else
asf_full_r <= (grey_wr_ptr_next == ~grey_rd_ptr_s);
 
 
// --------------------------------------------------------------------
//
reg [W-1:0] data_0_r;
reg [W-1:0] data_1_r;
wire [W-1:0] rd_data_mux = bin_rd_ptr[0] ? data_1_r : data_0_r;
assign rd_data = rd_data_mux;
 
always_ff @(posedge wr_clk)
if (writing)
if(bin_wr_ptr[0])
data_1_r <= wr_data;
else
data_0_r <= wr_data;
 
 
// --------------------------------------------------------------------
//
assign rd_empty = asf_empty_r;
assign wr_full = asf_full_r;
 
 
endmodule
 
 
/qaz_libs/trunk/basal/src/misc/barrel_shifter.v File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/sim.do File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/wip.do File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/init_test.do File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/the_test.sv File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/the_test.sv File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/sim.do File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/wip.do File deleted
/qaz_libs/trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/init_test.do File deleted
/qaz_libs/trunk/basal/sim/tests/tb_tiny_async_fifo/init_test.do
0,0 → 1,33
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all async_fifo
sim_compile_all sim
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_async_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_async_fifo/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_async_fifo/tb_tiny_async_fifo.sv
0,0 → 1,122
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
 
// wire clk_100mhz;
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);
 
 
// --------------------------------------------------------------------
//
localparam W = 8;
 
fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst);
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
tiny_async_fifo
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
// import fifo_bfm_pkg::*;
 
// fifo_bfm_class bfm = new(source, sink);
 
// initial
// bfm.init("", BOTH);
 
 
// --------------------------------------------------------------------
//
import fifo_agent_pkg::*;
 
fifo_agent_class bfm = new(source, sink);
 
initial
begin
bfm.init();
bfm.start_q();
end
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_async_fifo/the_test.sv
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
int data;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(1000ms);
 
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
 
repeat(20) @(posedge tb_clk);
 
repeat(100) tb_top.bfm.queue_random();
repeat(500) @(posedge tb_clk);
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_async_fifo/wip.do
0,0 → 1,13
#
 
 
vlog -f ../../libs/async_fifo_verilog/tiny_async_fifo.f
# vlog -f ../../libs/sim_verilog/fifo_bfm.f
 
# simulation $root
vlog ../../src/tb_tiny_async_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_sync_fifo/init_test.do
0,0 → 1,33
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all sync_fifo
sim_compile_all sim
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_sync_fifo/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv
0,0 → 1,122
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
 
// wire clk_100mhz;
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);
 
 
// --------------------------------------------------------------------
//
localparam W = 8;
 
fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst);
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
tiny_sync_fifo
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
// import fifo_bfm_pkg::*;
 
// fifo_bfm_class bfm = new(source, sink);
 
// initial
// bfm.init("", BOTH);
 
 
// --------------------------------------------------------------------
//
import fifo_agent_pkg::*;
 
fifo_agent_class bfm = new(source, sink);
 
initial
begin
bfm.init();
bfm.start_q();
end
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_sync_fifo/the_test.sv
0,0 → 1,88
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
int data;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(1000ms);
 
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
 
repeat(10) @(posedge tb_clk);
 
repeat(100) tb_top.bfm.queue_random();
 
 
// tb_top.bfm.write(8'h22, 0);
// tb_top.bfm.write(8'haa, 0);
// tb_top.bfm.read(10);
// tb_top.bfm.write(8'hff, 5);
// tb_top.bfm.read(0);
// tb_top.bfm.read(0);
// tb_top.bfm.write(8'h11, 1);
 
 
repeat(1000) @(posedge tb_clk);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/qaz_libs/trunk/basal/sim/tests/tb_tiny_sync_fifo/wip.do
0,0 → 1,13
#
 
 
vlog -f ../../libs/FPGA_verilog/tiny_fifo.f
vlog -f ../../libs/sim_verilog/fifo_bfm.f
 
# simulation $root
vlog ../../src/tb_tiny_sync_fifo.sv
 
# compile test last
vlog ./the_test.sv
 
/qaz_libs/trunk/basal/sim/src/legacy/fifo_bfm_pkg.sv File deleted
/qaz_libs/trunk/basal/sim/src/legacy/fifo_agent_pkg.sv File deleted
/qaz_libs/trunk/basal/sim/src/fifo_agent_pkg.sv
0,0 → 1,102
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package fifo_agent_pkg;
 
// --------------------------------------------------------------------
//
import fifo_bfm_pkg::*;
 
class fifo_agent_class #(W = 8);
 
fifo_bfm_class source_fifo;
fifo_bfm_class sink_fifo;
fifo_transaction_class tr_h;
fifo_transaction_class clone_h;
 
//--------------------------------------------------------------------
function
new
(
virtual fifo_write_if #(.W(W)) source,
virtual fifo_read_if #(.W(W)) sink
);
 
this.source_fifo = new(.source(source));
this.sink_fifo = new(.sink(sink));
this.tr_h = new();
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void init;
 
source_fifo.init("source", SOURCE);
sink_fifo.init("sink", SINK);
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task automatic
start_q;
 
source_fifo.fifo_write_q();
sink_fifo.fifo_read_q();
 
endtask: start_q
 
 
// --------------------------------------------------------------------
//
task automatic
queue_random;
 
if (!tr_h.randomize())
begin
$display("^^^ %16.t | %m | ERROR! randomize error", $time);
$stop;
end
 
clone_h = tr_h.clone();
source_fifo.fifo_tr_q.put(clone_h);
sink_fifo.fifo_tr_q.put(clone_h);
 
endtask: queue_random
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_agent_class
 
endpackage: fifo_agent_pkg
 
/qaz_libs/trunk/basal/sim/src/fifo_bfm_pkg.sv
0,0 → 1,380
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package fifo_bfm_pkg;
 
typedef enum
{
SOURCE,
SINK,
BOTH
} fifo_type_t;
 
// --------------------------------------------------------------------
//
class fifo_transaction_class;
 
rand int data;
rand int write_delay = 0;
rand int read_delay = 0;
 
constraint default_write_delay
{
write_delay >= 0 && write_delay <= 4;
write_delay dist {0 := 60, [1:4] :=40 };
}
 
constraint default_read_delay
{
read_delay >= 0 && read_delay <= 4;
read_delay dist {0 := 60, [1:4] :=40 };
}
 
 
// --------------------------------------------------------------------
//
function void copy
(
ref fifo_transaction_class from
);
 
// $display("^^^ %16.t | %m", $time);
 
this.data = from.data;
this.write_delay = from.write_delay;
this.read_delay = from.read_delay;
 
endfunction: copy
 
 
// --------------------------------------------------------------------
//
extern virtual function fifo_transaction_class clone();
// virtual function fifo_transaction_class clone();
 
// $display("^^^ %16.t | %m", $time);
 
// clone = new();
// clone.copy(this);
// return(clone);
 
// endfunction: clone
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_transaction_class
 
 
// --------------------------------------------------------------------
//
function fifo_transaction_class fifo_transaction_class::clone();
 
// $display("^^^ %16.t | %m", $time);
 
clone = new();
clone.copy(this);
 
endfunction: clone
 
 
// --------------------------------------------------------------------
//
class fifo_bfm_class #(W = 8);
 
string fifo_name;
fifo_type_t fifo_type;
 
virtual fifo_write_if #(.W(W)) source = null;
virtual fifo_read_if #(.W(W)) sink = null;
fifo_transaction_class fifo_tr = new();
 
 
//--------------------------------------------------------------------
function new
(
virtual fifo_write_if #(.W(W)) source = null,
virtual fifo_read_if #(.W(W)) sink = null
);
 
if(source != null)
this.source = source;
 
if(sink != null)
this.sink = sink;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
init
(
input string fifo_name,
input fifo_type_t fifo_type
);
 
this.fifo_name = fifo_name;
this.fifo_type = fifo_type;
 
if(fifo_type == SOURCE)
source.cb_s.wr_en <= 0;
else if(fifo_type == SINK)
sink.cb_s.rd_en <= 0;
else if(fifo_type == BOTH)
if((this.source == null) | (this.sink == null))
begin
$display("^^^ %16.t | %m | ERROR! %s fifo_type == BOTH with null class", $time, fifo_type.name);
$stop;
end
else
begin
source.cb_s.wr_en <= 0;
sink.cb_s.rd_en <= 0;
end
else
begin
$display("^^^ %16.t | %m | ERROR! fifo_type %s is invalid", $time, fifo_type.name);
$stop;
end
 
$display("^^^ %16.t | %m | initialization of %s for %s", $time, fifo_name, fifo_type.name);
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
write
(
input [W-1:0] wr_data,
input int write_delay = 0
);
 
source.cb_s.wr_data <= wr_data;
source.cb_s.wr_en <= 0;
 
source.zero_cycle_delay();
 
if(write_delay != 0)
repeat(write_delay) @(source.cb_s);
 
@(source.cb_s iff (source.cb_s.full == 0));
// @(source.cb_s iff (~source.cb_s.full));
source.cb_s.wr_en <= 1;
 
@(posedge source.clk);
source.cb_s.wr_en <= 0;
 
endtask: write
 
 
// --------------------------------------------------------------------
//
task
fork_write
(
input [W-1:0] wr_data,
input int write_delay = 0
);
 
fork
write(wr_data, write_delay);
join_none
 
#0;
 
endtask: fork_write
 
 
// --------------------------------------------------------------------
//
mailbox #(int) rd_data_q = new();
 
task
read
(
input int read_delay = 0
);
 
sink.cb_s.rd_en <= 0;
 
sink.zero_cycle_delay();
 
if(read_delay != 0)
repeat(read_delay) @(sink.cb_s);
 
@(sink.cb_s iff (sink.cb_s.empty == 0));
// @(sink.cb_s iff (~sink.cb_s.empty));
sink.cb_s.rd_en <= 1;
 
@(posedge sink.clk);
 
sink.cb_s.rd_en <= 0;
 
rd_data_q.put(sink.cb_s.rd_data);
 
endtask: read
 
 
// --------------------------------------------------------------------
//
task automatic
fork_read
(
input int read_delay = 0
);
 
fork
read(read_delay);
join_none
 
#0;
 
endtask: fork_read
 
 
// --------------------------------------------------------------------
//
mailbox #(fifo_transaction_class) fifo_tr_q;
semaphore fifo_tr_q_semaphore = new(1);
 
 
// --------------------------------------------------------------------
//
event fifo_write_done;
 
task automatic
fifo_write_q;
 
if((fifo_type != SOURCE) & (fifo_type == BOTH))
begin
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time);
return;
end
 
if(fifo_tr_q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.fifo_tr_q = new();
 
fifo_write_fork : fork
forever
begin
 
fifo_tr_q.get(fifo_tr);
fork_write(fifo_tr.data, fifo_tr.write_delay);
 
wait fork;
 
->fifo_write_done;
end
join_none
 
#0;
 
endtask: fifo_write_q
 
 
// --------------------------------------------------------------------
//
fifo_transaction_class fifo_tr_clone;
event fifo_read_done;
logic [W - 1:0] rd_data;
logic [W - 1:0] rd_result;
int compare_result;
int compare_errors = 0;
 
task automatic
fifo_read_q;
 
if((fifo_type != SINK) & (fifo_type == BOTH))
begin
$display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time);
return;
end
 
 
if(fifo_tr_q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.fifo_tr_q = new();
fifo_tr_clone = fifo_tr.clone();
 
fifo_read_q_fork : fork
forever
begin
 
fifo_tr_q.get(fifo_tr);
fork_read(fifo_tr.read_delay);
 
wait fork;
 
->fifo_read_done;
 
rd_data_q.get(rd_result);
rd_data = fifo_tr.data;
 
if(rd_result != rd_data)
begin
$display("^^^ %16.t | %m | ERROR! rd_result != fifo_tr.data |", $time);
$display("^^^ %16.t | %m | rd_result = %h |", $time, rd_result);
$display("^^^ %16.t | %m | fifo_tr.data = %h |", $time, fifo_tr.data);
end
 
// compare_result = avf_in_frame.compare(8, f_h);
// compare_errors += compare_result;
 
end
join_none
 
#0;
 
endtask: fifo_read_q
 
 
// --------------------------------------------------------------------
//
 
endclass: fifo_bfm_class
 
endpackage: fifo_bfm_pkg
 
/qaz_libs/trunk/sim/libs/bfm_packages_verilog/BFM.f
1,3 → 1,4
#
 
${LIB_BASE_DIR}/BFM/src/tb/tb_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_bfm_pkg.sv
/qaz_libs/trunk/sim/libs/bfm_packages_verilog/axi4_models.f
0,0 → 1,6
#
 
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv
 
/qaz_libs/trunk/sim/libs/bfm_packages_verilog/axis_bfm.f
0,0 → 1,9
#
 
${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv
 
 
 
 
 
 
/qaz_libs/trunk/sim/libs/sim_verilog/BFM.f
1,5 → 1,5
#
 
${LIB_BASE_DIR}/BFM/src/tb/tb_base.sv
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv
/qaz_libs/trunk/sim/libs/sim_verilog/axi4_models.f
0,0 → 1,4
#
 
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/tb_axi4_multi_port_memory.sv
 
/qaz_libs/trunk/sim/libs/qaz_lib_verilog/basal.f
1,15 → 1,38
#
 
${LIB_BASE_DIR}/basal/src/8b10b/decode_8b10b.v
${LIB_BASE_DIR}/basal/src/8b10b/encode_8b10b.v
 
${LIB_BASE_DIR}/basal/src/FIFOs/bc_sync_fifo.v
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/async_fifo.sv
 
${LIB_BASE_DIR}/basal/src/misc/bit_connect_big_to_little.v
${LIB_BASE_DIR}/basal/src/misc/bit_connect_little_to_big.v
${LIB_BASE_DIR}/basal/src/misc/bit_swap_big_to_little.v
${LIB_BASE_DIR}/basal/src/misc/bit_swap_little_to_big.v
${LIB_BASE_DIR}/basal/src/misc/one_hot_encoder.sv
${LIB_BASE_DIR}/basal/src/misc/pulse_stretcher.v
${LIB_BASE_DIR}/basal/src/misc/recursive_mux.sv
${LIB_BASE_DIR}/basal/src/misc/sr_latch.v
 
${LIB_BASE_DIR}/basal/src/PRBS/cf_pnmon.v
${LIB_BASE_DIR}/basal/src/PRBS/pcie_scrambler.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_16.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_64.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_8.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_14.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_8.v
 
${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_read_wider.v
${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_write_wider.v
${LIB_BASE_DIR}/basal/src/RAM/bram_tdp.v
${LIB_BASE_DIR}/basal/src/RAM/byte_enabled_simple_dual_port_ram.sv
${LIB_BASE_DIR}/basal/src/RAM/read_mixed_width_ram.sv
${LIB_BASE_DIR}/basal/src/RAM/write_mixed_width_ram.sv
 
${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v
${LIB_BASE_DIR}/basal/src/synchronize/pulse_synchronizer.v
 
/qaz_libs/trunk/sim/libs/tb_packages_verilog/BFM.f
1,5 → 1,8
#
 
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/q_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/bfm_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/logger_pkg.sv
 
${LIB_BASE_DIR}/BFM/src/video_frame/video_frame_pkg.sv
/qaz_libs/trunk/axi4_lib/sim/src/legacy/tb_bfm.sv File deleted
/qaz_libs/trunk/axi4_lib/sim/src/legacy/tb_axi4_memory.sv File deleted
/qaz_libs/trunk/axi4_lib/sim/src/legacy/tb_axi4_to_axis_agent_class_pkg.sv File deleted
/qaz_libs/trunk/axi4_lib/sim/src/legacy/tb_register_slice.sv File deleted
/qaz_libs/trunk/axi4_lib/sim/src/axi4_bfm_pkg.sv
0,0 → 1,563
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package axi4_bfm_pkg;
 
// --------------------------------------------------------------------
//
import tb_bfm_pkg::*;
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class ar_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
super.new();
this.axi4_m = axi4_m;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
ar_default;
 
axi4_m.cb_m.araddr <= 'bx;
axi4_m.cb_m.arburst <= 'bx;
axi4_m.cb_m.arcache <= 'bx;
axi4_m.cb_m.arid <= 'bx;
axi4_m.cb_m.arlen <= 'bx;
axi4_m.cb_m.arlock <= 'bx;
axi4_m.cb_m.arprot <= 'bx;
axi4_m.cb_m.arqos <= 'bx;
axi4_m.cb_m.arregion <= 'bx;
axi4_m.cb_m.arsize <= 'bx;
axi4_m.cb_m.arvalid <= 0;
 
endfunction: ar_default
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
repeat(tr_h.delay_h.next()) @(axi4_m.cb_m);
 
axi4_m.cb_m.araddr <= tr_h.addr;
axi4_m.cb_m.arid <= tr_h.id;
axi4_m.cb_m.arlen <= tr_h.len;
axi4_m.cb_m.arsize <= tr_h.size;
 
axi4_m.cb_m.arburst <= tr_h.burst;
axi4_m.cb_m.arcache <= tr_h.cache;
axi4_m.cb_m.arlock <= tr_h.lock;
axi4_m.cb_m.arprot <= tr_h.prot;
axi4_m.cb_m.arqos <= tr_h.qos;
axi4_m.cb_m.arregion <= tr_h.region;
axi4_m.cb_m.arvalid <= 1;
 
$display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);
 
repeat(1) @(axi4_m.cb_m);
wait(axi4_m.cb_m.arready);
 
axi4_m.zero_cycle_delay();
ar_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: ar_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class r_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
super.new();
this.axi4_m = axi4_m;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
r_default;
 
axi4_m.cb_m.rready <= 0;
 
endfunction: r_default
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
tr_h.data_h = new(tr_h.len);
 
foreach(tr_h.payload_h.w[i])
begin
repeat(tr_h.delay_h.next()) @(axi4_m.cb_m);
axi4_m.cb_m.rready <= 1;
repeat(1) @(axi4_m.cb_m);
 
wait(axi4_m.cb_m.rvalid);
axi4_m.zero_cycle_delay();
 
tr_h.data_h.w[i] = axi4_m.cb_m.rdata;
 
$display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
r_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: r_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class aw_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
super.new();
this.axi4_m = axi4_m;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
aw_default;
 
axi4_m.cb_m.awaddr <= 'bx;
axi4_m.cb_m.awburst <= 'bx;
axi4_m.cb_m.awcache <= 'bx;
axi4_m.cb_m.awid <= 'bx;
axi4_m.cb_m.awlen <= 'bx;
axi4_m.cb_m.awlock <= 'bx;
axi4_m.cb_m.awprot <= 'bx;
axi4_m.cb_m.awqos <= 'bx;
axi4_m.cb_m.awregion <= 'bx;
axi4_m.cb_m.awsize <= 'bx;
axi4_m.cb_m.awvalid <= 0;
 
endfunction: aw_default
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
repeat(tr_h.delay_h.next()) @(axi4_m.cb_m);
 
axi4_m.cb_m.awaddr <= tr_h.addr;
axi4_m.cb_m.awid <= tr_h.id;
axi4_m.cb_m.awlen <= tr_h.len;
axi4_m.cb_m.awsize <= tr_h.size;
 
axi4_m.cb_m.awburst <= tr_h.burst;
axi4_m.cb_m.awcache <= tr_h.cache;
axi4_m.cb_m.awlock <= tr_h.lock;
axi4_m.cb_m.awprot <= tr_h.prot;
axi4_m.cb_m.awqos <= tr_h.qos;
axi4_m.cb_m.awregion <= tr_h.region;
axi4_m.cb_m.awvalid <= 1;
 
$display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);
 
repeat(1) @(axi4_m.cb_m);
wait(axi4_m.cb_m.awready);
 
axi4_m.zero_cycle_delay();
aw_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: aw_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class w_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
super.new();
this.axi4_m = axi4_m;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
w_default;
 
axi4_m.cb_m.wdata <= 'bx;
axi4_m.cb_m.wlast <= 'bx;
axi4_m.cb_m.wstrb <= {N{1'b1}};
axi4_m.cb_m.wvalid <= 0;
 
endfunction: w_default
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
foreach(tr_h.payload_h.w[i])
begin
repeat(tr_h.delay_h.next()) @(axi4_m.cb_m);
 
axi4_m.cb_m.wdata <= tr_h.payload_h.w[i];
// axi4_m.cb_m.wstrb <= tr_h.strb; // need to fix
 
if(i < tr_h.payload_h.w.size - 1)
axi4_m.cb_m.wlast <= 0;
else
axi4_m.cb_m.wlast <= 1;
 
axi4_m.cb_m.wvalid <= 1;
 
repeat(1) @(axi4_m.cb_m);
wait(axi4_m.cb_m.wready);
 
axi4_m.zero_cycle_delay();
$display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
w_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: w_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class b_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
super.new();
this.axi4_m = axi4_m;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
b_default;
 
axi4_m.cb_m.bready <= 0;
 
endfunction: b_default
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
repeat(tr_h.delay_h.next()) @(axi4_m.cb_m);
axi4_m.cb_m.bready <= 1;
repeat(1) @(axi4_m.cb_m);
 
wait(axi4_m.cb_m.bvalid);
axi4_m.zero_cycle_delay();
 
$display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, axi4_m.cb_m.bresp);
b_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: b_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class axi4_master_bfm_class #(A = 32, N = 8, I = 1);
 
ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h;
aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h;
b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h;
 
axi4_transaction_class tr_h;
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
 
this.axi4_m = axi4_m;
 
ar_h = new(axi4_m);
r_h = new(axi4_m);
aw_h = new(axi4_m);
w_h = new(axi4_m);
b_h = new(axi4_m);
ar_h.init();
ar_h.ar_default();
 
r_h.init();
r_h.r_default();
 
aw_h.init();
aw_h.aw_default();
 
w_h.init();
w_h.w_default();
 
b_h.init();
b_h.b_default();
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
init;
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
basic_read
(
input logic [(A-1):0] araddr,
input logic [7:0] arlen,
output logic [(8*N)-1:0] data[],
output logic [1:0] rresp
);
 
this.tr_h = new;
this.tr_h.basic_read(araddr, arlen);
 
ar_h.put(tr_h);
r_h.put(tr_h);
 
@(r_h.done);
data = tr_h.data_h.w;
rresp = tr_h.resp;
 
endtask: basic_read
 
// --------------------------------------------------------------------
//
task
basic_random_read_burst
(
output logic [(8*N)-1:0] data[],
output logic [1:0] rresp
);
 
this.tr_h = new;
this.tr_h.basic_random_burst;
 
ar_h.put(tr_h);
r_h.put(tr_h);
 
@(r_h.done);
data = tr_h.data_h.w;
rresp = tr_h.resp;
 
endtask: basic_random_read_burst
 
 
// --------------------------------------------------------------------
//
task
basic_write
(
input logic [(A-1):0] awaddr,
input logic [7:0] awlen,
input logic [(8*N)-1:0] data[],
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_write(awaddr, awlen);
 
foreach(this.tr_h.payload_h.w[i])
this.tr_h.payload_h.w[i] = data[i];
 
aw_h.put(tr_h);
w_h.put(tr_h);
b_h.put(tr_h);
 
@(b_h.done);
bresp = tr_h.resp;
 
endtask: basic_write
 
// --------------------------------------------------------------------
//
task
basic_random_write_burst
(
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_random_burst;
 
aw_h.put(tr_h);
w_h.put(tr_h);
b_h.put(tr_h);
 
@(b_h.done);
bresp = tr_h.resp;
 
endtask: basic_random_write_burst
 
 
// --------------------------------------------------------------------
//
endclass: axi4_master_bfm_class
// --------------------------------------------------------------------
//
endpackage: axi4_bfm_pkg
 
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv
0,0 → 1,474
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_arbiter_pkg;
 
// --------------------------------------------------------------------
//
import axi4_models_pkg::*;
import bfm_pkg::*;
import logger_pkg::*;
 
 
// --------------------------------------------------------------------
//
virtual class base_request_class #(A, N, I);
 
string kind;
int id = -1;
 
//--------------------------------------------------------------------
//
pure virtual function void write_ax_if(axi4_channel_if_class #(A, N, I) channel);
pure virtual function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel);
 
 
// --------------------------------------------------------------------
//
endclass: base_request_class
 
 
// --------------------------------------------------------------------
//
class write_request_class #(A, N, I)
extends base_request_class #(A, N, I);
 
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic [2:0] awsize;
logic [3:0] awcache;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic [3:0] awregion;
 
 
// --------------------------------------------------------------------
//
function void write_ax_if(axi4_channel_if_class #(A, N, I) channel);
axi4_aw_if_class #(A, N, I) aw_if_h;
$cast(aw_if_h, channel);
aw_if_h.awaddr = awaddr;
aw_if_h.awburst = awburst;
aw_if_h.awid = awid;
aw_if_h.awlen = awlen;
aw_if_h.awsize = awsize;
aw_if_h.awcache = awcache;
aw_if_h.awlock = awlock;
aw_if_h.awprot = awprot;
aw_if_h.awqos = awqos;
aw_if_h.awregion = awregion;
endfunction: write_ax_if
 
 
// --------------------------------------------------------------------
//
function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel);
axi4_aw_if_class #(A, N, I) aw_if_h;
$cast(aw_if_h, channel);
awaddr = aw_if_h.awaddr;
awburst = aw_if_h.awburst;
awid = aw_if_h.awid;
awlen = aw_if_h.awlen;
awsize = aw_if_h.awsize;
awcache = aw_if_h.awcache;
awlock = aw_if_h.awlock;
awprot = aw_if_h.awprot;
awqos = aw_if_h.awqos;
awregion = aw_if_h.awregion;
endfunction: copy_ax_if
 
 
//--------------------------------------------------------------------
function new(int id);
super.new;
this.kind = "WRITE";
this.id = id;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: write_request_class
 
 
// --------------------------------------------------------------------
//
class read_request_class #(A, N, I)
extends base_request_class #(A, N, I);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic [2:0] arsize;
logic [3:0] arcache;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic [3:0] arregion;
 
// --------------------------------------------------------------------
//
function void write_ax_if(axi4_channel_if_class #(A, N, I) channel);
axi4_ar_if_class #(A, N, I) ar_if_h;
$cast(ar_if_h, channel);
ar_if_h.araddr = araddr;
ar_if_h.arburst = arburst;
ar_if_h.arid = arid;
ar_if_h.arlen = arlen;
ar_if_h.arsize = arsize;
ar_if_h.arcache = arcache;
ar_if_h.arlock = arlock;
ar_if_h.arprot = arprot;
ar_if_h.arqos = arqos;
ar_if_h.arregion = arregion;
endfunction: write_ax_if
 
 
// --------------------------------------------------------------------
//
function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel);
axi4_ar_if_class #(A, N, I) ar_if_h;
$cast(ar_if_h, channel);
araddr = ar_if_h.araddr;
arburst = ar_if_h.arburst;
arid = ar_if_h.arid;
arlen = ar_if_h.arlen;
arsize = ar_if_h.arsize;
arcache = ar_if_h.arcache;
arlock = ar_if_h.arlock;
arprot = ar_if_h.arprot;
arqos = ar_if_h.arqos;
arregion = ar_if_h.arregion;
endfunction: copy_ax_if
 
 
//--------------------------------------------------------------------
function new(int id);
super.new;
this.kind = "READ";
this.id = id;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: read_request_class
 
 
// --------------------------------------------------------------------
//
class requester_class #(A, N, I)
extends axi4_slave_model_class #(A, N, I);
 
mailbox #(base_request_class #(A, N, I)) q;
semaphore read_done;
semaphore write_done;
int id = -1;
logger_class log;
 
 
// --------------------------------------------------------------------
//
task automatic run_read_interface;
read_request_class #(A, N, I) r_req_h;
read_done = new;
forever
@(axi4_s.cb_s)
begin
ar_q_h.q.get(ar_if_h);
log.debug($sformatf("%m | start"));
log.debug($sformatf("%m | araddr = 0x%h", ar_if_h.araddr));
log.debug($sformatf("%m | arlen = 0x%h", ar_if_h.arlen));
r_req_h = new(id);
r_req_h.copy_ax_if(ar_if_h);
q.put(r_req_h);
read_done.get();
log.debug($sformatf("%m | done"));
end
endtask: run_read_interface
 
 
// --------------------------------------------------------------------
//
task run_write_interface;
write_request_class #(A, N, I) w_req_h;
write_done = new;
forever
@(axi4_s.cb_s)
begin
aw_q_h.q.get(aw_if_h);
log.debug($sformatf("%m | start"));
log.debug($sformatf("%m | awaddr = 0x%h", aw_if_h.awaddr));
log.debug($sformatf("%m | awlen = 0x%h", aw_if_h.awlen));
w_req_h = new(id);
w_req_h.copy_ax_if(aw_if_h);
q.put(w_req_h);
write_done.get();
log.debug($sformatf("%m | done"));
end
endtask: run_write_interface
 
 
// --------------------------------------------------------------------
//
task run_model;
wait(axi4_s.cb_s.aresetn);
axi4_s.zero_cycle_delay();
 
aw_q_h.run_q();
w_q_h.run_q();
b_q_h.run_q();
ar_q_h.run_q();
r_q_h.run_q();
 
fork
run_read_interface();
join_none
 
fork
run_write_interface();
join_none
 
endtask: run_model
 
 
//--------------------------------------------------------------------
function new(int id, virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_s);
super.new(axi4_s);
this.aw_q_h = new(axi4_s, 2);
this.w_q_h = new(axi4_s, 16);
this.b_q_h = new(axi4_s, 2);
this.ar_q_h = new(axi4_s, 2);
this.r_q_h = new(axi4_s, 16);
this.id = id;
this.q = new(1);
this.log = new();
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: requester_class
 
 
// --------------------------------------------------------------------
//
class axi4_granter_class #(A, N, I)
extends axi4_master_model_class #(A, N, I);
 
logger_class log;
 
 
// --------------------------------------------------------------------
//
task run_model;
wait(axi4_m.cb_s.aresetn);
axi4_m.zero_cycle_delay();
 
aw_q_h.run_q();
w_q_h.run_q();
b_q_h.run_q();
ar_q_h.run_q();
r_q_h.run_q();
endtask: run_model
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m);
super.new(axi4_m);
this.aw_q_h = new(axi4_m, 2);
this.w_q_h = new(axi4_m, 16);
this.b_q_h = new(axi4_m, 2);
this.ar_q_h = new(axi4_m, 2);
this.r_q_h = new(axi4_m, 16);
this.log = new();
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_granter_class
 
 
// --------------------------------------------------------------------
//
class axi4_arbiter_class #(A, N, I);
 
axi4_granter_class #(A, N, I) g_h;
requester_class #(A, N, I) r_h[];
mailbox #(int) grant;
int count = -1;
int current = 0, previous;
logger_class log;
 
 
// --------------------------------------------------------------------
//
task automatic do_read(requester_class #(A, N, I) r_h);
int id;
read_request_class #(A, N, I) r_req_h;
base_request_class #(A, N, I) request;
log.debug($sformatf("%m | read grant for %d", r_h.id));
r_h.q.get(request);
$cast(r_req_h, request);
 
g_h.ar_if_h = new(g_h.axi4_m);
r_req_h.write_ax_if(g_h.ar_if_h);
g_h.ar_q_h.q.put(g_h.ar_if_h);
 
for(int i = 0; i < r_h.ar_if_h.arlen + 1; i++)
begin
g_h.r_if_h = new(g_h.axi4_m);
r_h.r_if_h = new(r_h.axi4_s);
g_h.r_q_h.q.get(g_h.r_if_h);
r_h.r_if_h.copy(g_h.r_if_h);
r_h.r_q_h.q.put(r_h.r_if_h);
@(r_h.axi4_s.cb_s);
end
 
r_h.read_done.put();
grant.get(id);
log.debug($sformatf("%m | read grant for %d done", id));
endtask: do_read
 
 
// --------------------------------------------------------------------
//
task automatic do_write(requester_class #(A, N, I) r_h);
int id;
write_request_class #(A, N, I) w_req_h;
base_request_class #(A, N, I) request;
log.debug($sformatf("%m | write grant for %d", r_h.id));
r_h.q.get(request);
$cast(w_req_h, request);
 
g_h.aw_if_h = new(g_h.axi4_m);
w_req_h.write_ax_if(g_h.aw_if_h);
g_h.aw_q_h.q.put(g_h.aw_if_h);
 
for(int i = 0; i < r_h.aw_if_h.awlen + 1; i++)
begin
r_h.w_if_h = new(r_h.axi4_s);
g_h.w_if_h = new(g_h.axi4_m);
r_h.w_q_h.q.get(r_h.w_if_h);
g_h.w_if_h.copy(r_h.w_if_h);
g_h.w_q_h.q.put(g_h.w_if_h);
@(r_h.axi4_s.cb_s);
end
 
g_h.b_q_h.q.get(g_h.b_if_h);
r_h.b_if_h = new(r_h.axi4_s);
r_h.b_if_h.copy(g_h.b_if_h);
r_h.b_q_h.q.put(r_h.b_if_h);
r_h.write_done.put();
grant.get(id);
log.debug($sformatf("%m | write grant for %d done", id));
endtask: do_write
 
 
// --------------------------------------------------------------------
//
task automatic give_grant(requester_class #(A, N, I) r_h);
base_request_class #(A, N, I) request;
grant.put(r_h.id);
r_h.q.peek(request);
log.debug($sformatf("%m | %d got grant for %s", r_h.id, request.kind));
 
if(request.kind.toupper == "WRITE")
do_write(r_h);
else if(request.kind.toupper == "READ")
do_read(r_h);
else
$stop;
 
current = (current + count + 1) % count;
log.debug($sformatf("%m | new current = %d", current));
endtask: give_grant
 
 
// --------------------------------------------------------------------
//
task automatic do_arbitration;
wait(g_h.axi4_m.cb_m.aresetn);
g_h.axi4_m.zero_cycle_delay();
forever
@(g_h.axi4_m.cb_m)
begin
for(int i = current; i < current + count; i++)
if(r_h[i % count].q.num > 0)
begin
give_grant(r_h[i % count]);
break;
end
end
endtask: do_arbitration
 
 
//--------------------------------------------------------------------
function void debug_enable;
log.debug_enable();
g_h.log.debug_enable();
foreach(r_h[i])
r_h[i].log.debug_enable();
endfunction: debug_enable
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_if #(A, N, I) axi4_s[],
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m
);
this.grant = new(1);
this.g_h = new(axi4_m);
this.count = axi4_s.size;
this.r_h = new[axi4_s.size];
this.log = new;
 
foreach(axi4_s[i])
r_h[i] = new(i, axi4_s[i]);
 
fork
do_arbitration();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_arbiter_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_arbiter_pkg
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv
0,0 → 1,369
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_memory_pkg;
 
// --------------------------------------------------------------------
//
import axi4_models_pkg::*;
import bfm_pkg::*;
import logger_pkg::*;
 
 
// --------------------------------------------------------------------
//
class memory_tr_class #(A, N, I, type WORD_T = byte)
extends transaction_class #(memory_tr_class #(A, N, I));
 
rand int addr;
rand int size;
rand byte data[];
 
constraint default_addr
{
addr[$clog2(N*8)-1:0] == 0;
}
 
constraint default_size
{
size dist {N := 40, [N*2:N*15] := 40, [N*16:N*255] := 20};
}
 
 
//--------------------------------------------------------------------
//
function void init(int addr, int size);
this.data = new[size];
this.addr = addr;
this.size = size;
endfunction: init
 
 
//--------------------------------------------------------------------
//
function void random(int addr, int size);
this.data = new[size];
assert(this.randomize() with
{
this.addr == addr; // why not working?
this.size == size;
});
this.addr = addr;
this.size = size;
endfunction: random
 
 
// --------------------------------------------------------------------
//
task constant(int addr, int size, byte value[]);
init(addr, size);
this.data = new[size];
for(int i = 0; i < size; i += value.size)
foreach(value[k])
data[i + k] = value[k];
endtask: constant
 
 
// --------------------------------------------------------------------
//
task automatic counting(int addr, int count);
byte word[];
int word_size = $bits(WORD_T) / 8; // word size in bytes
init(addr, count * word_size);
for(WORD_T i = 0; i < count; i++)
begin
word = {<< byte{i}};
foreach(word[k])
data[addr + (i * word_size) + k] = word[k];
end
endtask: counting
 
 
// --------------------------------------------------------------------
//
function void copy(TR_T from);
init(from.addr, from.size);
this.data = new[from.size];
foreach(from.data[i])
this.data[i] = from.data[i];
endfunction: copy
 
 
//--------------------------------------------------------------------
function new;
a_word_t_mod_n: assert($bits(WORD_T) % 8 == 0) else $fatal;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: memory_tr_class
 
 
// --------------------------------------------------------------------
//
class axi4_memory_class #(A, N, I, type WORD_T = byte)
extends axi4_slave_model_class #(.A(A), .N(N), .I(I));
 
logger_class log;
byte memory [*];
 
 
// --------------------------------------------------------------------
//
function void clear_all;
memory.delete;
endfunction: clear_all
 
 
// --------------------------------------------------------------------
//
function void compare(memory_tr_class #(A, N, I, WORD_T) tr_h);
foreach(tr_h.data[i])
if(memory.exists(tr_h.addr + i))
begin
if(memory[tr_h.addr + i] != tr_h.data[i])
log.error($sformatf("%m | 1 memory[0x%8.h] = 0x%2.h | 0x%2.h", tr_h.addr + i, memory[tr_h.addr + i], tr_h.data[i]));
end
else
log.error($sformatf("%m | 2 memory[0x%8.h] = 0x%2.h | 0x%2.h", tr_h.addr + i, 'bx, tr_h.data[i]));
endfunction: compare
 
 
// --------------------------------------------------------------------
//
task display_memory(int offset, int count);
for(int i = 0; i < count; i++)
if(memory.exists(offset + i))
$display("^^^ %16.t | %m | memory[0x%8.x] = 0x%2.x", $time, offset + i, memory[offset + i]);
else
$display("^^^ %16.t | %m | memory[0x%8.x] = 0x%2.x", $time, offset + i, 8'hxx);
endtask: display_memory
 
 
// --------------------------------------------------------------------
//
task constant_fill(int offset, int count, int value);
for(int i = 0; i < count; i++)
memory[offset + i] = value;
endtask: constant_fill
 
 
// --------------------------------------------------------------------
//
task counting_fill(int offset, int count);
for(int i = 0; i < count; i++)
memory[offset + i] = i;
endtask: counting_fill
 
 
// --------------------------------------------------------------------
//
task dump_words(int offset, ref byte data[]);
foreach(data[i])
if(memory.exists(offset + i))
data[i] = memory[offset + i];
else
data[i] = 'bx;
endtask: dump_words
 
 
// --------------------------------------------------------------------
//
function reg [7:0] dump(int offset);
if(memory.exists(offset))
return(memory[offset]);
else
return('bx);
endfunction: dump
 
 
// --------------------------------------------------------------------
//
task load_words(int offset, byte data[]);
foreach(data[i])
memory[offset + i] = data[i];
endtask: load_words
 
 
// --------------------------------------------------------------------
//
task load(int offset, reg [7:0] data);
memory[offset] = data;
endtask: load
 
 
// --------------------------------------------------------------------
//
task run_read_interface;
int result;
logic [9:0] delay = 0;
int memory_addr;
 
forever
@(axi4_s.cb_s)
begin
result = ar_q_h.q.try_peek(ar_if_h);
if(result != 0)
begin
log.debug($sformatf("araddr = 0x%h", ar_if_h.araddr));
log.debug($sformatf("arlen = 0x%h", ar_if_h.arlen));
delay = $urandom_range(9, 0);
if(delay > 6)
repeat($urandom_range(50, 1))
@(axi4_s.cb_s);
 
for(int i = 0; i < ar_if_h.arlen + 1; i++)
begin
memory_addr = ar_if_h.araddr + (i * (2 ** ar_if_h.arsize));
for(int i = 0; i < ar_if_h.N; i++)
begin
if(memory.exists(memory_addr))
r_if_h.rdata[i*8 +: 8] = memory[memory_addr];
else
r_if_h.rdata[i*8 +: 8] = 8'hxx;
 
memory_addr++;
end
log.debug($sformatf("rdata = 0x%h", r_if_h.rdata));
 
if(i == ar_if_h.arlen)
begin
ar_q_h.q.get(ar_if_h);
r_if_h.rlast = 1;
end
else
r_if_h.rlast = 0;
 
r_if_h.rid = 0;
r_if_h.rresp = 0;
 
r_q_h.q.put(r_if_h);
r_if_h = new(axi4_s);
 
@(axi4_s.cb_s);
end
r_if_h.rlast = 0;
end
end
endtask: run_read_interface
 
 
// --------------------------------------------------------------------
//
task run_write_interface;
 
int result;
logic [9:0] delay = 0;
int memory_addr;
 
forever
@(axi4_s.cb_s)
begin
result = aw_q_h.q.try_peek(aw_if_h);
if(result != 0)
begin
memory_addr = aw_if_h.awaddr;
log.debug($sformatf("awaddr = 0x%h", aw_if_h.awaddr));
 
delay = $urandom_range(9, 0);
if(delay > 6)
repeat($urandom_range(8, 1))
@(axi4_s.cb_s);
 
for(int i = 0; i < aw_if_h.awlen + 1; i++)
begin
w_q_h.q.get(w_if_h);
log.debug($sformatf("wdata = 0x%h", w_if_h.wdata));
for(int k = 0; k < aw_if_h.N; k++)
begin
memory[memory_addr] = w_if_h.wdata[k*8 +: 8];
memory_addr++;
end
 
if(i == aw_if_h.awlen)
begin
b_if_h.bresp = 0;
b_if_h.bid = aw_if_h.awid;
b_q_h.q.put(b_if_h);
b_if_h = new(axi4_s);
aw_q_h.q.get(aw_if_h);
end
 
@(axi4_s.cb_s);
end
end
end
 
endtask: run_write_interface
 
 
// --------------------------------------------------------------------
//
task run_model;
wait(axi4_s.cb_s.aresetn);
axi4_s.zero_cycle_delay();
 
aw_q_h.run_q();
w_q_h.run_q();
b_q_h.run_q();
ar_q_h.run_q();
r_q_h.run_q();
 
fork
run_write_interface();
join_none
 
fork
run_read_interface();
join_none
endtask: run_model
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_s);
super.new(axi4_s);
a_word_t_mod_n: assert($bits(WORD_T) % 8 == 0) else $fatal;
this.aw_q_h = new(axi4_s, 2);
this.w_q_h = new(axi4_s, 16);
this.b_q_h = new(axi4_s, 2);
this.ar_q_h = new(axi4_s, 2);
this.r_q_h = new(axi4_s, 16);
this.log = new();
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_memory_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_memory_pkg
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv
0,0 → 1,822
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package axi4_models_pkg;
 
// --------------------------------------------------------------------
//
virtual class axi4_channel_if_class #(A, N, I);
 
virtual axi4_if #(A, N, I) axi4_bus;
event valid;
 
 
// --------------------------------------------------------------------
//
pure virtual function void set_master_default;
pure virtual function void set_slave_default;
pure virtual function void copy(axi4_channel_if_class #(A, N, I) from);
pure virtual function void copy_if;
pure virtual function void drive_if;
pure virtual function void set_ready(bit value);
pure virtual function bit is_valid;
pure virtual function void set_valid(bit value);
pure virtual function bit is_ready;
pure virtual function bit is_transfer;
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
this.axi4_bus = axi4_bus;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_channel_if_class
 
 
// --------------------------------------------------------------------
//
class axi4_channel_sink_q_class #(A, N, I, type T = logic);
 
virtual axi4_if #(A, N, I) axi4_bus;
T c_if_h;
int q_size;
mailbox #(T) q;
 
 
// --------------------------------------------------------------------
//
function automatic void run_q;
int result;
c_if_h.set_ready(1'b1);
 
fork
forever
@(axi4_bus.cb_s)
begin
if(c_if_h.is_transfer)
begin
result = q.try_put(c_if_h);
if(result == 0)
$error;
 
c_if_h.copy_if();
c_if_h = new(axi4_bus);
end
 
if(q.num >= q_size)
c_if_h.set_ready(1'b0);
else
c_if_h.set_ready(1'b1);
end
join_none
endfunction: run_q
 
 
//--------------------------------------------------------------------
function new( virtual axi4_if #(A, N, I) axi4_bus, int q_size);
this.axi4_bus = axi4_bus;
this.q_size = q_size;
this.q = new(q_size);
this.c_if_h = new(axi4_bus);
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_channel_sink_q_class
 
 
// --------------------------------------------------------------------
//
class axi4_channel_source_q_class #(A, N, I, type T = logic);
 
virtual axi4_if #(A, N, I) axi4_bus;
T c_if_h;
int q_size;
mailbox #(T) q;
 
 
// --------------------------------------------------------------------
//
function automatic void run_q;
int result;
c_if_h.set_valid(1'b0);
 
fork
forever
@(axi4_bus.cb_s)
begin
if(c_if_h.is_transfer)
begin
result = q.try_get(c_if_h);
if(result == 0)
$stop;
end
 
result = q.try_peek(c_if_h);
if(result == 0)
c_if_h.set_valid(1'b0);
else
begin
c_if_h.set_valid(1'b1);
c_if_h.drive_if();
end
end
join_none
endfunction: run_q
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus, int q_size);
this.axi4_bus = axi4_bus;
this.q_size = q_size;
this.q = new(q_size);
this.c_if_h = new(axi4_bus);
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_channel_source_q_class
 
 
// --------------------------------------------------------------------
//
class axi4_aw_if_class #(A, N, I)
extends axi4_channel_if_class #(A, N, I);
 
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic [2:0] awsize;
logic [3:0] awcache;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic [3:0] awregion;
 
 
// --------------------------------------------------------------------
//
function void set_master_default;
axi4_bus.cb_m.awvalid <= 0;
endfunction: set_master_default
 
 
// --------------------------------------------------------------------
//
function void set_slave_default;
axi4_bus.cb_s.awready <= 0;
endfunction: set_slave_default
 
 
// --------------------------------------------------------------------
//
function void copy(axi4_channel_if_class #(A, N, I) from);
axi4_aw_if_class #(A, N, I) child;
$cast(child, from);
awaddr = child.awaddr;
awburst = child.awburst;
awid = child.awid;
awlen = child.awlen;
awsize = child.awsize;
awcache = child.awcache;
awlock = child.awlock;
awprot = child.awprot;
awqos = child.awqos;
awregion = child.awregion;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
function void copy_if;
awaddr = axi4_bus.cb_s.awaddr;
awburst = axi4_bus.cb_s.awburst;
awid = axi4_bus.cb_s.awid;
awlen = axi4_bus.cb_s.awlen;
awsize = axi4_bus.cb_s.awsize;
awcache = axi4_bus.cb_s.awcache;
awlock = axi4_bus.cb_s.awlock;
awprot = axi4_bus.cb_s.awprot;
awqos = axi4_bus.cb_s.awqos;
awregion = axi4_bus.cb_s.awregion;
endfunction: copy_if
 
 
// --------------------------------------------------------------------
//
function void drive_if;
axi4_bus.cb_m.awaddr <= awaddr;
axi4_bus.cb_m.awburst <= awburst;
axi4_bus.cb_m.awid <= awid;
axi4_bus.cb_m.awlen <= awlen;
axi4_bus.cb_m.awsize <= awsize;
axi4_bus.cb_m.awcache <= awcache;
axi4_bus.cb_m.awlock <= awlock;
axi4_bus.cb_m.awprot <= awprot;
axi4_bus.cb_m.awqos <= awqos;
axi4_bus.cb_m.awregion <= awregion;
endfunction: drive_if
 
 
// --------------------------------------------------------------------
//
function void set_ready(bit value);
axi4_bus.cb_s.awready <= value;
endfunction: set_ready
 
 
// --------------------------------------------------------------------
//
function bit is_valid;
return(axi4_bus.cb_s.awvalid);
endfunction: is_valid
 
 
// --------------------------------------------------------------------
//
function void set_valid(bit value);
axi4_bus.cb_m.awvalid <= value;
endfunction: set_valid
 
 
// --------------------------------------------------------------------
//
function bit is_ready;
return(axi4_bus.cb_m.awready);
endfunction: is_ready
 
 
// --------------------------------------------------------------------
//
function bit is_transfer;
return(axi4_bus.cb_m.awready & axi4_bus.cb_s.awvalid);
endfunction: is_transfer
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
super.new(axi4_bus);
endfunction: new
 
// --------------------------------------------------------------------
//
endclass: axi4_aw_if_class
 
 
// --------------------------------------------------------------------
//
class axi4_ar_if_class #(A, N, I)
extends axi4_channel_if_class #(A, N, I);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic [2:0] arsize;
logic [3:0] arcache;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic [3:0] arregion;
 
 
// --------------------------------------------------------------------
//
virtual function void set_master_default;
axi4_bus.cb_m.arvalid <= 0;
endfunction: set_master_default
 
 
// --------------------------------------------------------------------
//
virtual function void set_slave_default;
axi4_bus.cb_s.arready <= 0;
endfunction: set_slave_default
 
 
// --------------------------------------------------------------------
//
virtual function void copy(axi4_channel_if_class #(A, N, I) from);
axi4_ar_if_class #(A, N, I) child;
$cast(child, from);
araddr = child.araddr;
arburst = child.arburst;
arid = child.arid;
arlen = child.arlen;
arsize = child.arsize;
arcache = child.arcache;
arlock = child.arlock;
arprot = child.arprot;
arqos = child.arqos;
arregion = child.arregion;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
virtual function void copy_if;
araddr = axi4_bus.cb_s.araddr;
arburst = axi4_bus.cb_s.arburst;
arid = axi4_bus.cb_s.arid;
arlen = axi4_bus.cb_s.arlen;
arsize = axi4_bus.cb_s.arsize;
arcache = axi4_bus.cb_s.arcache;
arlock = axi4_bus.cb_s.arlock;
arprot = axi4_bus.cb_s.arprot;
arqos = axi4_bus.cb_s.arqos;
arregion = axi4_bus.cb_s.arregion;
endfunction: copy_if
 
 
// --------------------------------------------------------------------
//
virtual function void drive_if;
axi4_bus.cb_m.araddr <= araddr;
axi4_bus.cb_m.arburst <= arburst;
axi4_bus.cb_m.arid <= arid;
axi4_bus.cb_m.arlen <= arlen;
axi4_bus.cb_m.arsize <= arsize;
axi4_bus.cb_m.arcache <= arcache;
axi4_bus.cb_m.arlock <= arlock;
axi4_bus.cb_m.arprot <= arprot;
axi4_bus.cb_m.arqos <= arqos;
axi4_bus.cb_m.arregion <= arregion;
endfunction: drive_if
 
 
// --------------------------------------------------------------------
//
virtual function void set_ready(bit value);
axi4_bus.cb_s.arready <= value;
endfunction: set_ready
 
 
// --------------------------------------------------------------------
//
virtual function bit is_valid;
return(axi4_bus.cb_s.arvalid);
endfunction: is_valid
 
 
// --------------------------------------------------------------------
//
function void set_valid(bit value);
axi4_bus.cb_m.arvalid <= value;
endfunction: set_valid
 
 
// --------------------------------------------------------------------
//
function bit is_ready;
return(axi4_bus.cb_m.arready);
endfunction: is_ready
 
 
// --------------------------------------------------------------------
//
function bit is_transfer;
return(axi4_bus.cb_m.arready & axi4_bus.cb_s.arvalid);
endfunction: is_transfer
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
super.new(axi4_bus);
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_ar_if_class
 
 
// --------------------------------------------------------------------
//
class axi4_w_if_class #(A, N, I)
extends axi4_channel_if_class #(A, N, I);
 
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic [N-1:0] wstrb;
 
 
// --------------------------------------------------------------------
//
function void set_master_default;
axi4_bus.cb_m.wvalid <= 0;
endfunction: set_master_default
 
 
// --------------------------------------------------------------------
//
function void set_slave_default;
axi4_bus.cb_s.wready <= 0;
endfunction: set_slave_default
 
 
// --------------------------------------------------------------------
//
function void copy(axi4_channel_if_class #(A, N, I) from);
axi4_w_if_class #(A, N, I) child;
$cast(child, from);
wdata = child.wdata;
wid = child.wid;
wlast = child.wlast;
wstrb = child.wstrb;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
function void copy_if;
wdata = axi4_bus.cb_s.wdata;
wid = axi4_bus.cb_s.wid;
wlast = axi4_bus.cb_s.wlast;
wstrb = axi4_bus.cb_s.wstrb;
endfunction: copy_if
 
 
// --------------------------------------------------------------------
//
function void drive_if;
axi4_bus.cb_m.wdata <= wdata;
axi4_bus.cb_m.wid <= wid;
axi4_bus.cb_m.wlast <= wlast;
axi4_bus.cb_m.wstrb <= wstrb;
endfunction: drive_if
 
 
// --------------------------------------------------------------------
//
function void set_ready(bit value);
axi4_bus.cb_s.wready <= value;
endfunction: set_ready
 
 
// --------------------------------------------------------------------
//
function bit is_valid;
return(axi4_bus.cb_s.wvalid);
endfunction: is_valid
 
 
// --------------------------------------------------------------------
//
function void set_valid(bit value);
axi4_bus.cb_m.wvalid <= value;
endfunction: set_valid
 
 
// --------------------------------------------------------------------
//
function bit is_ready;
return(axi4_bus.cb_m.wready);
endfunction: is_ready
 
 
// --------------------------------------------------------------------
//
function bit is_transfer;
return(axi4_bus.cb_m.wready & axi4_bus.cb_s.wvalid);
endfunction: is_transfer
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
super.new(axi4_bus);
endfunction: new
 
// --------------------------------------------------------------------
//
endclass: axi4_w_if_class
 
 
// --------------------------------------------------------------------
//
class axi4_b_if_class #(A, N, I)
extends axi4_channel_if_class #(A, N, I);
 
logic [(I-1):0] bid;
logic [1:0] bresp;
 
 
// --------------------------------------------------------------------
//
function void set_master_default;
axi4_bus.cb_m.bready <= 0;
endfunction: set_master_default
 
 
// --------------------------------------------------------------------
//
function void set_slave_default;
axi4_bus.cb_s.bvalid <= 0;
endfunction: set_slave_default
 
 
// --------------------------------------------------------------------
//
function void copy(axi4_channel_if_class #(A, N, I) from);
axi4_b_if_class #(A, N, I) child;
$cast(child, from);
bid = child.bid;
bresp = child.bresp;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
function void copy_if;
bid = axi4_bus.cb_m.bid;
bresp = axi4_bus.cb_m.bresp;
endfunction: copy_if
 
 
// --------------------------------------------------------------------
//
function void drive_if;
axi4_bus.cb_s.bid <= bid;
axi4_bus.cb_s.bresp <= bresp;
endfunction: drive_if
 
 
// --------------------------------------------------------------------
//
function void set_ready(bit value);
axi4_bus.cb_m.bready <= value;
endfunction: set_ready
 
 
// --------------------------------------------------------------------
//
function bit is_valid;
return(axi4_bus.cb_m.bvalid);
endfunction: is_valid
 
 
// --------------------------------------------------------------------
//
function void set_valid(bit value);
axi4_bus.cb_s.bvalid <= value;
endfunction: set_valid
 
 
// --------------------------------------------------------------------
//
function bit is_ready;
return(axi4_bus.cb_s.bready);
endfunction: is_ready
 
 
// --------------------------------------------------------------------
//
function bit is_transfer;
return(axi4_bus.cb_s.bready & axi4_bus.cb_m.bvalid);
endfunction: is_transfer
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
super.new(axi4_bus);
endfunction: new
 
// --------------------------------------------------------------------
//
endclass: axi4_b_if_class
 
// --------------------------------------------------------------------
//
class axi4_r_if_class #(A, N, I)
extends axi4_channel_if_class #(A, N, I);
 
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic [1:0] rresp;
 
 
// --------------------------------------------------------------------
//
function void set_master_default;
axi4_bus.cb_m.rready <= 0;
endfunction: set_master_default
 
 
// --------------------------------------------------------------------
//
function void set_slave_default;
axi4_bus.cb_s.rvalid <= 0;
endfunction: set_slave_default
 
 
// --------------------------------------------------------------------
//
function void copy(axi4_channel_if_class #(A, N, I) from);
axi4_r_if_class #(A, N, I) child;
$cast(child, from);
rdata = child.rdata;
rid = child.rid;
rlast = child.rlast;
rresp = child.rresp;
endfunction: copy
 
 
// --------------------------------------------------------------------
//
function void copy_if;
rdata = axi4_bus.cb_m.rdata;
rid = axi4_bus.cb_m.rid;
rlast = axi4_bus.cb_m.rlast;
rresp = axi4_bus.cb_m.rresp;
endfunction: copy_if
 
 
// --------------------------------------------------------------------
//
function void drive_if;
axi4_bus.cb_s.rdata <= rdata;
axi4_bus.cb_s.rid <= rid;
axi4_bus.cb_s.rlast <= rlast;
axi4_bus.cb_s.rresp <= rresp;
endfunction: drive_if
 
 
// --------------------------------------------------------------------
//
function void set_ready(bit value);
axi4_bus.cb_m.rready <= value;
endfunction: set_ready
 
 
// --------------------------------------------------------------------
//
function bit is_valid;
return(axi4_bus.cb_m.rvalid);
endfunction: is_valid
 
 
// --------------------------------------------------------------------
//
function void set_valid(bit value);
axi4_bus.cb_s.rvalid <= value;
endfunction: set_valid
 
 
// --------------------------------------------------------------------
//
function bit is_ready;
return(axi4_bus.cb_s.rready);
endfunction: is_ready
 
 
// --------------------------------------------------------------------
//
function bit is_transfer;
return(axi4_bus.cb_s.rready & axi4_bus.cb_m.rvalid);
endfunction: is_transfer
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_bus);
super.new(axi4_bus);
endfunction: new
 
// --------------------------------------------------------------------
//
endclass: axi4_r_if_class
 
 
// --------------------------------------------------------------------
//
virtual class axi4_master_model_class #(A, N, I);
 
virtual axi4_if #(A, N, I) axi4_m;
axi4_aw_if_class #(A, N, I) aw_if_h;
axi4_channel_source_q_class #(A, N, I, axi4_aw_if_class #(A, N, I)) aw_q_h;
axi4_w_if_class #(A, N, I) w_if_h;
axi4_channel_source_q_class #(A, N, I, axi4_w_if_class #(A, N, I)) w_q_h;
axi4_b_if_class #(A, N, I) b_if_h;
axi4_channel_sink_q_class #(A, N, I, axi4_b_if_class #(A, N, I)) b_q_h;
axi4_ar_if_class #(A, N, I) ar_if_h;
axi4_channel_source_q_class #(A, N, I, axi4_ar_if_class #(A, N, I)) ar_q_h;
axi4_r_if_class #(A, N, I) r_if_h;
axi4_channel_sink_q_class #(A, N, I, axi4_r_if_class #(A, N, I)) r_q_h;
 
 
// --------------------------------------------------------------------
//
pure virtual task run_model;
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_m);
this.axi4_m = axi4_m;
this.aw_if_h = new(axi4_m);
aw_if_h.set_master_default();
this.w_if_h = new(axi4_m);
w_if_h.set_master_default();
this.b_if_h = new(axi4_m);
b_if_h.set_master_default();
this.ar_if_h = new(axi4_m);
ar_if_h.set_master_default();
this.r_if_h = new(axi4_m);
r_if_h.set_master_default();
 
fork
run_model();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_master_model_class
 
 
// --------------------------------------------------------------------
//
virtual class axi4_slave_model_class #(A, N, I);
 
virtual axi4_if #(A, N, I) axi4_s;
axi4_aw_if_class #(A, N, I) aw_if_h;
axi4_channel_sink_q_class #(A, N, I, axi4_aw_if_class #(A, N, I)) aw_q_h;
axi4_w_if_class #(A, N, I) w_if_h;
axi4_channel_sink_q_class #(A, N, I, axi4_w_if_class #(A, N, I)) w_q_h;
axi4_b_if_class #(A, N, I) b_if_h;
axi4_channel_source_q_class #(A, N, I, axi4_b_if_class #(A, N, I)) b_q_h;
axi4_ar_if_class #(A, N, I) ar_if_h;
axi4_channel_sink_q_class #(A, N, I, axi4_ar_if_class #(A, N, I)) ar_q_h;
axi4_r_if_class #(A, N, I) r_if_h;
axi4_channel_source_q_class #(A, N, I, axi4_r_if_class #(A, N, I)) r_q_h;
 
 
// --------------------------------------------------------------------
//
pure virtual task run_model;
 
 
//--------------------------------------------------------------------
function new(virtual axi4_if #(A, N, I) axi4_s);
 
this.axi4_s = axi4_s;
this.aw_if_h = new(axi4_s);
aw_if_h.set_slave_default();
this.w_if_h = new(axi4_s);
w_if_h.set_slave_default();
this.b_if_h = new(axi4_s);
b_if_h.set_slave_default();
this.ar_if_h = new(axi4_s);
ar_if_h.set_slave_default();
this.r_if_h = new(axi4_s);
r_if_h.set_slave_default();
 
fork
run_model();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: axi4_slave_model_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_models_pkg
 
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_models/tb_axi4_multi_port_memory.sv
0,0 → 1,89
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
tb_axi4_multi_port_memory
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
PORTS,
MAXWAITS = 256,
type WORD_T = byte
)
(
axi4_if axi4_s[PORTS],
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
import axis_bfm_pkg::*;
import axi4_memory_pkg::*;
import axi4_arbiter_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N), .I(I)) axi4_bus(.*);
 
 
// --------------------------------------------------------------------
//
axi4_arbiter_class #(A, N, I) arb_h;
axi4_memory_class #(A, N, I, WORD_T) m_h;
 
initial
begin
arb_h = new(axi4_s, axi4_bus);
m_h = new(axi4_bus);
end
 
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
axi4_bus_checker(.axi4_in(axi4_bus));
 
 
// --------------------------------------------------------------------
//
generate
begin: axi4_s_cherkers
for(genvar j = 0; j < PORTS; j++)
axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
axi4_checker_i(.axi4_in(axi4_s[j]));
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 
/qaz_libs/trunk/axi4_lib/sim/src/tb_axi4_memory.sv
0,0 → 1,129
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 8;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N))
axi4_s(.*);
 
// --------------------------------------------------------------------
//
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N))
axi4_s_check(.axi4_in(axi4_s));
 
 
// // --------------------------------------------------------------------
// //
// axi4_master_bfm_if #(.A(A), .N(N))
// tb_axi4_m(.axi4_s(axi4_s), .*);
 
 
// --------------------------------------------------------------------
//
import axi4_bfm_pkg::*;
axi4_master_bfm_class bfm;
 
initial
bfm = new(axi4_s);
 
 
// --------------------------------------------------------------------
//
import axi4_memory_pkg::*;
axi4_memory_class axi4_memory;
 
initial
axi4_memory = new(axi4_s);
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/axi4_lib/sim/src/tb_axi4_to_axis_agent_class_pkg.sv
0,0 → 1,130
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_axi4_to_axis_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import axi4_memory_pkg::*;
import axis_bfm_pkg::*;
 
 
// --------------------------------------------------------------------
//
class tb_axi4_to_axis_agent_class #(N, A, I, D, U);
 
axi4_memory_class #(A, N, I) m_h;
axis_rx_bfm_class #(N, I, D, U) s_h;
memory_tr_class #(A, N, I) m_tr_h, m_tr_clone_h;
axis_tr_class #(N, I, D, U) s_tr_h;
 
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m;
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out;
 
mailbox #(memory_tr_class #(A, N, I)) q;
 
 
// --------------------------------------------------------------------
//
task wait_for_sof;
@(posedge axis_out.cb_s.tuser);
$display("^^^ %16.t | %m", $time);
endtask: wait_for_sof
 
 
// --------------------------------------------------------------------
//
task random_transaction(int addr, int size);
m_tr_h = new();
m_tr_h.random(addr, size);
m_tr_clone_h = m_tr_h.clone();
q.put(m_tr_clone_h);
m_h.load_words(addr, m_tr_h.data);
endtask: random_transaction
 
 
// --------------------------------------------------------------------
//
task automatic
compare;
 
$display("^^^ %16.t | %m", $time);
$display("^^^ %16.t | q.num = %d", $time, q.num);
$display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num);
$display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size);
 
q.get(m_tr_h);
 
for(int i = 0; i < m_tr_h.data.size; i += N)
begin
if(s_h.q.try_get(s_tr_h) == 0)
begin
$display("!!! %16.t | ERROR!!! try_get(s_tr_h) == 0", $time);
break;
end
 
for(int k = 0; k < N; k++)
begin
if(s_tr_h.tdata[k*8 +: 8] != m_tr_h.data[i + k])
begin
$display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time);
$display("!!! %16.t | ERROR!!! mismatch | i = %d | k = %d", $time, i, k);
$display("!!! %16.t | %x | %x |", $time, s_tr_h.tdata[k*8 +: 8], m_tr_h.data[i + k]);
$stop;
end
end
end
 
$display("^^^ %16.t | %m | done!", $time);
 
endtask: compare
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m,
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out
);
 
this.axi4_m = axi4_m;
this.axis_out = axis_out;
m_h = new(axi4_m);
s_h = new(axis_out);
q = new();
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_axi4_to_axis_agent_class
 
// --------------------------------------------------------------------
//
endpackage: tb_axi4_to_axis_agent_class_pkg
/qaz_libs/trunk/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv
0,0 → 1,526
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
axi4_master_bfm_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
)
(
axi4_if axi4_s,
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
 
 
// --------------------------------------------------------------------
//
default clocking cb @(posedge aclk);
output arid;
output araddr;
output arburst;
output arcache;
output awid;
output arlen;
output arlock;
output arprot;
output arqos;
input arready;
output arregion;
output arsize;
output arvalid;
output awaddr;
output awburst;
output awcache;
output awlen;
output awlock;
output awprot;
output awqos;
input awready;
output awregion;
output awsize;
output awvalid;
output bready;
input bid;
input bresp;
input bvalid;
input rdata;
input rid;
input rlast;
output rready;
input rresp;
input rvalid;
output wdata;
output wlast;
input wready;
output wstrb;
output wvalid;
input aresetn;
input aclk;
endclocking
 
 
// --------------------------------------------------------------------
//
assign axi4_s.arid = arid;
assign axi4_s.araddr = araddr;
assign axi4_s.arburst = arburst;
assign axi4_s.arcache = arcache;
assign axi4_s.awid = awid;
assign axi4_s.arlen = arlen;
assign axi4_s.arlock = arlock;
assign axi4_s.arprot = arprot;
assign axi4_s.arqos = arqos;
assign arready = axi4_s.arready;
assign axi4_s.arregion = arregion;
assign axi4_s.arsize = arsize;
assign axi4_s.arvalid = arvalid;
assign axi4_s.awaddr = awaddr;
assign axi4_s.awburst = awburst;
assign axi4_s.awcache = awcache;
assign axi4_s.awlen = awlen;
assign axi4_s.awlock = awlock;
assign axi4_s.awprot = awprot;
assign axi4_s.awqos = awqos;
assign awready = axi4_s.awready;
assign axi4_s.awregion = awregion;
assign axi4_s.awsize = awsize;
assign axi4_s.awvalid = awvalid;
assign axi4_s.bready = bready;
assign bid = axi4_s.bid;
assign bresp = axi4_s.bresp;
assign bvalid = axi4_s.bvalid;
assign rdata = axi4_s.rdata;
assign rid = axi4_s.rid;
assign rlast = axi4_s.rlast;
assign axi4_s.rready = rready;
assign rresp = axi4_s.rresp;
assign rvalid = axi4_s.rvalid;
assign axi4_s.wdata = wdata;
assign axi4_s.wlast = wlast;
assign wready = axi4_s.wready;
assign axi4_s.wstrb = wstrb;
assign axi4_s.wvalid = wvalid;
 
 
// --------------------------------------------------------------------
//
function void
ar_default;
 
cb.araddr <= 'bx;
cb.arburst <= 'bx;
cb.arcache <= 'bx;
cb.arid <= 'bx;
cb.arlen <= 'bx;
cb.arlock <= 'bx;
cb.arprot <= 'bx;
cb.arqos <= 'bx;
cb.arregion <= 'bx;
cb.arsize <= 'bx;
cb.arvalid <= 0;
 
endfunction: ar_default
 
 
// --------------------------------------------------------------------
//
function void
aw_default;
 
cb.awaddr <= 'bx;
cb.awburst <= 'bx;
cb.awcache <= 'bx;
cb.awid <= 'bx;
cb.awlen <= 'bx;
cb.awlock <= 'bx;
cb.awprot <= 'bx;
cb.awqos <= 'bx;
cb.awregion <= 'bx;
cb.awsize <= 'bx;
cb.awvalid <= 0;
 
endfunction: aw_default
 
 
// --------------------------------------------------------------------
//
function void
r_default;
 
cb.rready <= 0;
 
endfunction: r_default
 
 
// --------------------------------------------------------------------
//
function void
w_default;
 
cb.wdata <= 'bx;
cb.wlast <= 'bx;
cb.wstrb <= {N{1'b1}};
cb.wvalid <= 0;
 
endfunction: w_default
 
 
// --------------------------------------------------------------------
//
function void
b_default;
 
cb.bready <= 0;
 
endfunction: b_default
 
 
// --------------------------------------------------------------------
//
function void
init;
 
ar_default();
r_default();
aw_default();
w_default();
b_default();
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
import tb_bfm_pkg::*;
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class ar_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.araddr <= tr_h.addr;
cb.arid <= tr_h.id;
cb.arlen <= tr_h.len;
cb.arsize <= tr_h.size;
 
cb.arburst <= tr_h.burst;
cb.arcache <= tr_h.cache;
cb.arlock <= tr_h.lock;
cb.arprot <= tr_h.prot;
cb.arqos <= tr_h.qos;
cb.arregion <= tr_h.region;
cb.arvalid <= 1;
 
$display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);
 
##1;
wait(cb.arready);
 
##0;
ar_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: ar_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class r_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
tr_h.data_h = new(tr_h.len);
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
cb.rready <= 1;
##1;
 
wait(cb.rvalid);
##0;
 
tr_h.data_h.w[i] = cb.rdata;
 
$display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
r_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: r_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class aw_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.awaddr <= tr_h.addr;
cb.awid <= tr_h.id;
cb.awlen <= tr_h.len;
cb.awsize <= tr_h.size;
 
cb.awburst <= tr_h.burst;
cb.awcache <= tr_h.cache;
cb.awlock <= tr_h.lock;
cb.awprot <= tr_h.prot;
cb.awqos <= tr_h.qos;
cb.awregion <= tr_h.region;
cb.awvalid <= 1;
 
$display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);
 
##1;
wait(cb.awready);
 
##0;
aw_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: aw_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class w_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.wdata <= tr_h.payload_h.w[i];
// cb.wstrb <= tr_h.strb; // need to fix
 
if(i < tr_h.payload_h.w.size - 1)
cb.wlast <= 0;
else
cb.wlast <= 1;
 
cb.wvalid <= 1;
 
##1;
wait(cb.wready);
 
##0;
$display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
w_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: w_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class b_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
cb.bready <= 1;
##1;
 
wait(cb.bvalid);
##0;
 
$display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp);
b_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: b_master_transaction_class
 
 
// --------------------------------------------------------------------
//
ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h;
aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h;
b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h;
 
initial
begin
init();
ar_h = new;
ar_h.init();
r_h = new;
r_h.init();
aw_h = new;
aw_h.init();
w_h = new;
w_h.init();
b_h = new;
b_h.init();
end
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv
0,0 → 1,153
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_simple_agent_pkg;
 
// --------------------------------------------------------------------
//
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class axi4_simple_agent_class #(A = 32, N = 8, I = 1);
 
axi4_transaction_class tr_h;
virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m;
virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m,
virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s
);
 
this.axi4_m = axi4_m;
this.axi4_s = axi4_s;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
task
basic_read
(
input logic [(A-1):0] araddr,
input logic [7:0] arlen,
output logic [(8*N)-1:0] data[],
output logic [1:0] rresp
);
 
this.tr_h = new;
this.tr_h.basic_read(araddr, arlen);
 
axi4_m.ar_h.put(tr_h);
axi4_s.ar_h.put(tr_h);
axi4_m.r_h.put(tr_h);
 
@(axi4_m.r_h.done);
data = tr_h.data_h.w;
rresp = tr_h.resp;
 
endtask: basic_read
 
 
// --------------------------------------------------------------------
//
task
basic_write
(
input logic [(A-1):0] awaddr,
input logic [7:0] awlen,
input logic [(8*N)-1:0] data[],
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_write(awaddr, awlen);
 
foreach(this.tr_h.payload_h.w[i])
this.tr_h.payload_h.w[i] = data[i];
 
axi4_m.aw_h.put(tr_h);
axi4_s.aw_h.put(tr_h);
axi4_m.w_h.put(tr_h);
axi4_s.w_h.put(tr_h);
axi4_m.b_h.put(tr_h);
 
@(axi4_s.b_h.done);
bresp = tr_h.resp;
 
endtask: basic_write
 
 
// --------------------------------------------------------------------
//
task
basic_random_write
(
input logic [(A-1):0] awaddr,
input logic [7:0] awlen,
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_write(awaddr, awlen);
 
axi4_m.aw_h.put(tr_h);
axi4_s.aw_h.put(tr_h);
axi4_m.w_h.put(tr_h);
axi4_s.w_h.put(tr_h);
axi4_m.b_h.put(tr_h);
 
@(axi4_s.b_h.done);
bresp = tr_h.resp;
 
endtask: basic_random_write
 
 
// --------------------------------------------------------------------
//
function void
init;
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
endclass: axi4_simple_agent_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_simple_agent_pkg
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv
0,0 → 1,514
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
axi4_slave_bfm_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
)
(
axi4_if axi4_m,
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
 
 
// --------------------------------------------------------------------
//
default clocking cb @(posedge aclk);
input arid;
input araddr;
input arburst;
input arcache;
input awid;
input arlen;
input arlock;
input arprot;
input arqos;
output arready;
input arregion;
input arsize;
input arvalid;
input awaddr;
input awburst;
input awcache;
input awlen;
input awlock;
input awprot;
input awqos;
output awready;
input awregion;
input awsize;
input awvalid;
input bready;
output bid;
output bresp;
output bvalid;
output rdata;
output rid;
output rlast;
input rready;
output rresp;
output rvalid;
input wdata;
input wid;
input wlast;
output wready;
input wstrb;
input wvalid;
input aresetn;
input aclk;
endclocking
 
 
// --------------------------------------------------------------------
//
assign arid = axi4_m.arid;
assign araddr = axi4_m.araddr;
assign arburst = axi4_m.arburst;
assign arcache = axi4_m.arcache;
assign awid = axi4_m.awid;
assign arlen = axi4_m.arlen;
assign arlock = axi4_m.arlock;
assign arprot = axi4_m.arprot;
assign arqos = axi4_m.arqos;
assign axi4_m.arready = arready;
assign arregion = axi4_m.arregion;
assign arsize = axi4_m.arsize;
assign arvalid = axi4_m.arvalid;
assign awaddr = axi4_m.awaddr;
assign awburst = axi4_m.awburst;
assign awcache = axi4_m.awcache;
assign awlen = axi4_m.awlen;
assign awlock = axi4_m.awlock;
assign awprot = axi4_m.awprot;
assign awqos = axi4_m.awqos;
assign axi4_m.awready = awready;
assign awregion = axi4_m.awregion;
assign awsize = axi4_m.awsize;
assign awvalid = axi4_m.awvalid;
assign bready = axi4_m.bready;
assign axi4_m.bid = bid;
assign axi4_m.bresp = bresp;
assign axi4_m.bvalid = bvalid;
assign axi4_m.rdata = rdata;
assign axi4_m.rid = rid;
assign axi4_m.rlast = rlast;
assign rready = axi4_m.rready;
assign axi4_m.rresp = rresp;
assign axi4_m.rvalid = rvalid;
assign wdata = axi4_m.wdata;
assign wlast = axi4_m.wlast;
assign axi4_m.wready = wready;
assign wstrb = axi4_m.wstrb;
assign wvalid = axi4_m.wvalid;
 
 
// --------------------------------------------------------------------
//
function void
ar_default;
 
cb.arready <= 0;
 
endfunction: ar_default
 
 
// --------------------------------------------------------------------
//
function void
aw_default;
 
cb.awready <= 0;
 
endfunction: aw_default
 
 
// --------------------------------------------------------------------
//
function void
r_default;
 
cb.rdata <= 'bx;
cb.rid <= 'bx;
cb.rlast <= 'bx;
cb.rresp <= 0;
cb.rvalid <= 0;
 
endfunction: r_default
 
 
// --------------------------------------------------------------------
//
function void
w_default;
 
cb.wready <= 0;
 
endfunction: w_default
 
 
// --------------------------------------------------------------------
//
function void
b_default;
 
cb.bid <= 0;
cb.bresp <= 0;
cb.bvalid <= 0;
 
endfunction: b_default
 
 
// --------------------------------------------------------------------
//
function void
init;
 
ar_default();
r_default();
aw_default();
w_default();
b_default();
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
import tb_bfm_pkg::*;
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class r_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.rdata <= tr_h.payload_h.w[i];
cb.rresp <= tr_h.resp;
cb.rid <= tr_h.id;
 
if(i < tr_h.payload_h.w.size - 1)
cb.rlast <= 0;
else
cb.rlast <= 1;
 
cb.rvalid <= 1;
##1;
 
wait(cb.rready);
##0;
 
$display("^^^ %16.t | %m | slave R transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
r_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: r_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
r_slave_transaction_class #(.A(A), .N(N), .I(I)) r_h;
 
class ar_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.arready <= 1;
##1;
 
wait(cb.arvalid);
 
##0;
r_h.put(tr_h);
ar_default();
 
$display("^^^ %16.t | %m | slave AR transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: ar_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
class aw_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
semaphore aw_semaphore;
 
 
//--------------------------------------------------------------------
function new;
 
super.new();
this.aw_semaphore = new(0);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.awready <= 1;
##1;
 
wait(cb.awvalid);
 
##0;
this.aw_semaphore.put();
aw_default();
 
$display("^^^ %16.t | %m | slave AW transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
 
->this.done;
 
endtask: transaction
 
// --------------------------------------------------------------------
//
endclass: aw_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
aw_slave_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
 
class b_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
// Error: AXI4_ERRS_BRESP_AW: A slave must not give a write response before the write address.
// Spec: section A3.3.1 and figure A3-7.
aw_h.aw_semaphore.get(); // better way to do this???
 
##(tr_h.delay_h.next());
 
cb.bresp <= tr_h.resp;
cb.bid <= tr_h.id;
 
cb.bvalid <= 1;
##1;
 
wait(cb.bready);
##0;
 
$display("^^^ %16.t | %m | slave B transaction |", $time);
b_default();
 
->this.done;
 
endtask: transaction
 
// --------------------------------------------------------------------
//
endclass: b_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
b_slave_transaction_class #(.A(A), .N(N), .I(I)) b_h;
 
class w_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
tr_h.data_h = new(tr_h.len);
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.wready <= 1;
##1;
 
wait(cb.wvalid);
##0;
 
tr_h.data_h.w[i] <= cb.wdata;
$display("^^^ %16.t | %m | slave W transaction | %d | 0x%016x |", $time, i, cb.wdata);
w_default();
end
 
b_h.put(tr_h);
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: w_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
ar_slave_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
w_slave_transaction_class #(.A(A), .N(N), .I(I)) w_h;
 
initial
begin
init();
ar_h = new;
ar_h.init();
r_h = new;
r_h.init();
aw_h = new;
aw_h.init();
w_h = new;
w_h.init();
b_h = new;
b_h.init();
end
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/qaz_libs/trunk/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv
0,0 → 1,253
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_transaction_pkg;
 
// --------------------------------------------------------------------
//
class axi4_delay_class;
 
rand int unsigned delay;
 
 
// --------------------------------------------------------------------
//
function int unsigned
next;
 
assert(this.randomize() with{delay dist {0 := 40, [1:3] := 40, [4:7] := 20};});
return(delay);
 
endfunction: next
 
 
// --------------------------------------------------------------------
//
endclass: axi4_delay_class
 
 
// --------------------------------------------------------------------
//
class axi4_payload_class #(N = 8);
 
rand logic [(8*N)-1:0] w[];
 
 
// --------------------------------------------------------------------
//
function
new
(
logic [7:0] len = 0
);
 
this.w = new[len + 1];
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
random
(
logic [7:0] len = 0
);
 
this.w = new[len + 1];
assert(this.randomize());
 
endfunction: random
 
 
// --------------------------------------------------------------------
//
endclass: axi4_payload_class
 
 
// --------------------------------------------------------------------
//
class axi4_transaction_class #(A = 32, N = 8, I = 1);
 
axi4_delay_class delay_h;
axi4_payload_class #(.N(N)) payload_h;
axi4_payload_class #(.N(N)) data_h;
rand logic [(A-1):0] addr = 'bz;
rand logic [1:0] burst = 2'b01;
rand logic [7:0] len = 0;
rand logic [2:0] size = $clog2(N);
rand logic [(I-1):0] id = 0;
rand logic [1:0] resp = 0;
 
logic [3:0] cache = 0;
logic lock = 0;
logic [2:0] prot = 0;
logic [3:0] qos = 0;
logic [3:0] region = 0;
 
constraint default_len
{
len dist {0 := 40, [1:15] := 40, [16:255] := 20};
}
 
 
// --------------------------------------------------------------------
//
function
new
(
logic [7:0] len = 0
);
 
this.payload_h = new(len + 1);
this.delay_h = new;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
basic_random;
 
assert(this.randomize() with
{
this.id == 0;
this.resp == 0;
this.burst == 2'b01;
this.len == 0;
this.size == $clog2(N);
});
 
this.payload_h.random(this.len);
 
endfunction: basic_random
 
 
// --------------------------------------------------------------------
//
function void
basic_random_burst;
 
assert(this.randomize() with
{
this.addr[$clog2(N*8)-1:0] == 0;
this.id == 0;
this.resp == 0;
this.burst == 2'b01;
this.size == $clog2(N);
this.len dist {0 := 40, [1:3] := 40, [4:15] := 20};
});
 
this.payload_h.random(this.len);
 
endfunction: basic_random_burst
 
 
// --------------------------------------------------------------------
//
function void
basic_read
(
logic [(A-1):0] addr,
logic [7:0] len = 0
);
 
this.id = 0;
this.resp = 0;
this.burst = 2'b01;
this.size = $clog2(N);
this.addr = addr;
this.len = len;
this.payload_h.random(len);
 
endfunction: basic_read
 
 
// --------------------------------------------------------------------
//
function void
basic_write
(
logic [(A-1):0] addr,
logic [7:0] len = 0
);
 
this.id = 0;
this.resp = 0;
this.burst = 2'b01;
this.size = $clog2(N);
this.addr = addr;
this.len = len;
this.payload_h.random(len);
 
endfunction: basic_write
 
 
// --------------------------------------------------------------------
//
function void copy
(
axi4_transaction_class #(.A(A), .N(N), .I(I)) from
);
 
this.addr = from.addr;
this.burst = from.burst;
this.len = from.len;
this.size = from.size;
this.id = from.id;
this.resp = from.resp;
this.cache = from.cache;
this.lock = from.lock;
this.prot = from.prot;
this.qos = from.qos;
this.region = from.region;
 
endfunction: copy
 
 
// --------------------------------------------------------------------
//
virtual function axi4_transaction_class #(.A(A), .N(N), .I(I)) clone;
 
clone = new();
clone.copy(this);
return(clone);
 
endfunction: clone
 
 
// --------------------------------------------------------------------
//
endclass: axi4_transaction_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_transaction_pkg
 
/qaz_libs/trunk/axi4_lib/sim/src/tb_bfm.sv
0,0 → 1,119
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 8;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N))
axi4_bus(.*);
 
axi4_checker #(.A(A), .N(N))
axi4_in_check(.axi4_in(axi4_bus));
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
import axi4_simple_agent_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_master_bfm_if #(.A(A), .N(N))
axi4_m(.axi4_s(axi4_bus), .*);
 
axi4_slave_bfm_if #(.A(A), .N(N))
axi4_s(.axi4_m(axi4_bus), .*);
 
 
// --------------------------------------------------------------------
//
axi4_simple_agent_class bfm;
 
initial
bfm = new(axi4_m, axi4_s);
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/axi4_lib/sim/src/tb_register_slice.sv
0,0 → 1,133
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 8;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N))
axi4_s(.*);
axi4_if #(.A(A), .N(N))
axi4_m(.*);
 
// --------------------------------------------------------------------
//
axi4_register_slice #(.A(A), .N(N))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N))
axi4_s_check(.axi4_in(axi4_s));
 
axi4_checker #(.A(A), .N(N))
axi4_m_check(.axi4_in(axi4_m));
 
 
// --------------------------------------------------------------------
//
import axi4_simple_agent_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_master_bfm_if #(.A(A), .N(N))
tb_axi4_m(.axi4_s(axi4_s), .*);
 
axi4_slave_bfm_if #(.A(A), .N(N))
tb_axi4_s(.axi4_m(axi4_m), .*);
 
 
// --------------------------------------------------------------------
//
axi4_simple_agent_class bfm;
 
initial
bfm = new(tb_axi4_m, tb_axi4_s);
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf
qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== --- qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf (nonexistent) +++ qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf (revision 49)
qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/avalon_lib/src/ast_ready_cycle_fsm.sv =================================================================== --- qaz_libs/trunk/avalon_lib/src/ast_ready_cycle_fsm.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/src/ast_ready_cycle_fsm.sv (revision 49) @@ -0,0 +1,106 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module + ast_ready_cycle_fsm + ( + input axis_en, + output axis_tvalid, + input axis_tready, + + input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also + input fifo_empty, + output fifo_rd_en, + + output data_to_axis_fsm_error, + + input aclk, + input aresetn + ); + + //--------------------------------------------------- + // state machine binary definitions + enum reg [3:0] { + IDLE_STATE = 4'b0001, + TVALID = 4'b0010, + TREADY = 4'b0100, + ERROR_STATE = 4'b1000 + } state, next_state; + + + //--------------------------------------------------- + // state machine flop + always_ff @(posedge aclk) + if(~aresetn) + state <= IDLE_STATE; + else + state <= next_state; + + + //--------------------------------------------------- + // state machine + always_comb + case(state) + IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) + if(axis_tready) + next_state <= TREADY; + else + next_state <= TVALID; + else + next_state <= IDLE_STATE; + + TVALID: if(axis_tready) // wait for slave to be ready + next_state <= TREADY; + else + next_state <= TVALID; + + TREADY: if(fifo_empty) // slave can accept data + next_state <= IDLE_STATE; + else if(axis_tready) + next_state <= TREADY; + else + next_state <= TVALID; + + ERROR_STATE: next_state <= IDLE_STATE; + + default: next_state <= ERROR_STATE; + + endcase + + + //--------------------------------------------------- + // outputs + assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); + assign fifo_rd_en = axis_tvalid & axis_tready; + assign data_to_axis_fsm_error = (state == ERROR_STATE); + + +//--------------------------------------------------- +// +endmodule + Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv (revision 49) @@ -0,0 +1,292 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_monitor +// =head1 SYNOPSIS +// Bridge with Avalon Bus Protocol Assertion Checker +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module implements Avalon ST protocol assertion checking for simulation. +// The component acts as a simple repeater with Avalon bus signals +// passed through from the sink to source interface. +// The instantiated altera_avalon_st_monitor snoops all passing Avalon +// bus signals and performs assertion checking and measures coverage on +// Avalon Streaming protocol properties. +// Transactions in transit may also be captured in a transaction buffer and +// extracted from the monitor via the API. +// The macro ALTERA_AVALON_SIM_SVA is defined to disable SVA processing +// The macro ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING must be defined to +// enable transaction monitoring +//----------------------------------------------------------------------------- + +`timescale 1ps / 1ps + +module altera_avalon_st_monitor( + clk, + reset, + + sink_data, + sink_channel, + sink_valid, + sink_startofpacket, + sink_endofpacket, + sink_error, + sink_empty, + sink_ready, + + src_data, + src_channel, + src_valid, + src_startofpacket, + src_endofpacket, + src_error, + src_empty, + src_ready + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // number of bits in one symbols + parameter ST_NUMSYMBOLS = 4; // number of symbols in one data + parameter ST_CHANNEL_W = 0; // width of channel signal + parameter ST_ERROR_W = 0; // width of error signal + parameter ST_EMPTY_W = 0; // width of empty signal, ST_EMPTY_W = log2(`ST_NUMSYMBOLS) + + parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles + parameter ST_MAX_CHANNELS = 1; // maximum number of channels + + parameter USE_PACKET = 0; // data transfer in packet format + parameter USE_CHANNEL = 0; // use channel port + parameter USE_ERROR = 0; // use error port + parameter USE_READY = 1; // use ready port + parameter USE_VALID = 1; // use valid port + parameter USE_EMPTY = 0; // use empty port + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + + parameter ST_MAX_PACKET_SIZE = 1; // Max number of packet size covered + parameter VHDL_ID = 0; // VHDL BFM ID number + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; + localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; + localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; + localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; + + localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data + ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel + 1 + // valid + 1 + // startofpacket + 1 + // endofpacket + ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error + ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty + 1; // ready + + localparam MTAP_W = ST_BEATSPERCYCLE*TAP_W; + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Streaming Sink Interface + input [lindex(ST_MDATA_W) : 0] sink_data; + input [lindex(ST_MCHANNEL_W) : 0] sink_channel; + input [lindex(ST_BEATSPERCYCLE) : 0] sink_valid; + input [lindex(ST_BEATSPERCYCLE) : 0] sink_startofpacket; + input [lindex(ST_BEATSPERCYCLE) : 0] sink_endofpacket; + input [lindex(ST_MERROR_W) : 0] sink_error; + input [lindex(ST_MEMPTY_W) : 0] sink_empty; + output sink_ready; + + // =head2 Avalon Streaming Source Interface + output [lindex(ST_MDATA_W) : 0] src_data; + output [lindex(ST_MCHANNEL_W) : 0] src_channel; + output [lindex(ST_BEATSPERCYCLE) : 0] src_valid; + output [lindex(ST_BEATSPERCYCLE) : 0] src_startofpacket; + output [lindex(ST_BEATSPERCYCLE) : 0] src_endofpacket; + output [lindex(ST_MERROR_W) : 0] src_error; + output [lindex(ST_MEMPTY_W) : 0] src_empty; + input src_ready; + + // =cut + + function int lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + + // outputs + logic sink_ready; + logic [lindex(ST_MDATA_W) : 0] src_data; + logic [lindex(ST_MCHANNEL_W) : 0] src_channel; + logic [lindex(ST_BEATSPERCYCLE) : 0] src_valid; + logic [lindex(ST_BEATSPERCYCLE) : 0] src_startofpacket; + logic [lindex(ST_BEATSPERCYCLE) : 0] src_endofpacket; + logic [lindex(ST_MERROR_W) : 0] src_error; + logic [lindex(ST_MEMPTY_W) : 0] src_empty; + + logic [(MTAP_W)-ST_BEATSPERCYCLE : 0] tap; + + always @(*) begin + sink_ready <= src_ready; + src_data <= sink_data; + src_channel <= sink_channel; + src_valid <= sink_valid; + src_startofpacket <= sink_startofpacket; + src_endofpacket <= sink_endofpacket; + src_error <= sink_error; + src_empty <= sink_empty; + + tap <= { + sink_data, + sink_channel, + sink_valid, + sink_startofpacket, + sink_endofpacket, + sink_error, + sink_empty, + src_ready + }; + end + + //-------------------------------------------------------------------------- + // =head1 ALTERA_AVALON_ST_MONITOR_ASSERTION + // This module implements Avalon-ST protocol simulation assertion checkers + // =cut + //-------------------------------------------------------------------------- + altera_avalon_st_monitor_assertion + #( + .ST_SYMBOL_W (ST_SYMBOL_W), + .ST_NUMSYMBOLS (ST_NUMSYMBOLS), + .ST_CHANNEL_W (ST_CHANNEL_W), + .ST_ERROR_W (ST_ERROR_W), + .ST_EMPTY_W (ST_EMPTY_W), + + .ST_READY_LATENCY(ST_READY_LATENCY), + .ST_MAX_CHANNELS (ST_MAX_CHANNELS), + .ST_BEATSPERCYCLE(ST_BEATSPERCYCLE), + + .USE_PACKET (USE_PACKET), + .USE_CHANNEL (USE_CHANNEL), + .USE_ERROR (USE_ERROR), + .USE_READY (USE_READY), + .USE_VALID (USE_VALID), + .USE_EMPTY (USE_EMPTY) + ) + monitor_assertion ( + .clk (clk), + .reset (reset), + .tap (tap) + ); + + //-------------------------------------------------------------------------- + // =head1 ALTERA_AVALON_ST_MONITOR_COVERAGE + // This module implements Avalon-ST protocol functional coverage measurements + // =cut + //-------------------------------------------------------------------------- + altera_avalon_st_monitor_coverage + #( + .ST_SYMBOL_W (ST_SYMBOL_W), + .ST_NUMSYMBOLS (ST_NUMSYMBOLS), + .ST_CHANNEL_W (ST_CHANNEL_W), + .ST_ERROR_W (ST_ERROR_W), + .ST_EMPTY_W (ST_EMPTY_W), + .ST_BEATSPERCYCLE (ST_BEATSPERCYCLE), + + .ST_READY_LATENCY (ST_READY_LATENCY), + .ST_MAX_CHANNELS (ST_MAX_CHANNELS), + + .USE_PACKET (USE_PACKET), + .USE_CHANNEL (USE_CHANNEL), + .USE_ERROR (USE_ERROR), + .USE_READY (USE_READY), + .USE_VALID (USE_VALID), + .USE_EMPTY (USE_EMPTY), + .ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE) + ) + monitor_coverage ( + .clk (clk), + .reset (reset), + .tap (tap) + ); + + //-------------------------------------------------------------------------- + // =head1 ALTERA_AVALON_ST_MONITOR_TRANSACTIONS + // This module implements Avalon-ST the transaction recorder. + // =cut + //-------------------------------------------------------------------------- + + `ifdef ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING + altera_avalon_st_monitor_transactions + #( + .ST_SYMBOL_W (ST_SYMBOL_W), + .ST_NUMSYMBOLS (ST_NUMSYMBOLS), + .ST_CHANNEL_W (ST_CHANNEL_W), + .ST_ERROR_W (ST_ERROR_W), + .ST_EMPTY_W (ST_EMPTY_W), + .ST_BEATSPERCYCLE (ST_BEATSPERCYCLE), + + .ST_READY_LATENCY (ST_READY_LATENCY), + .ST_MAX_CHANNELS (ST_MAX_CHANNELS), + + .USE_PACKET (USE_PACKET), + .USE_CHANNEL (USE_CHANNEL), + .USE_ERROR (USE_ERROR), + .USE_READY (USE_READY), + .USE_VALID (USE_VALID), + .USE_EMPTY (USE_EMPTY), + .ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE) + ) + monitor_trans ( + .clk (clk), + .reset (reset), + .tap (tap) + ); + `endif + + // synthesis translate_off + import verbosity_pkg::*; + + localparam VERSION = "17.1"; + + function automatic void hello(); + // introduction message to the console + string message; + $sformat(message, "%m: - Hello from altera_avalon_st_monitor"); + print(VERBOSITY_INFO, message); + `ifdef DISABLE_ALTERA_AVALON_SIM_SVA + $sformat(message, "%m: - Assertions disabled (DISABLE_ALTERA_AVALON_SIM_SVA defined)"); + `else + $sformat(message, "%m: - Assertions enabled (DISABLE_ALTERA_AVALON_SIM_SVA undefined)"); + `endif + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Revision: #1 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Date: 2017/07/30 $"); + print(VERBOSITY_INFO, message); + print_divider(VERBOSITY_INFO); + endfunction + + initial begin + hello(); + end + + // synthesis translate_on + +endmodule Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv (revision 49) @@ -0,0 +1,550 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/main/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_tap.sv $ +// $Revision: #7 $ +// $Date: 2009/04/16 $ +// $Author: pscheidt $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_monitor_assertion +// =head1 SYNOPSIS +// Streaming Avalon Bus Protocol Checker +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module implements Avalon ST protocol assertion checking for simulation. +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_avalon_st_monitor_assertion( + clk, + reset, + tap + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // number of bits in one symbols + parameter ST_NUMSYMBOLS = 4; // number of symbols in one data + parameter ST_CHANNEL_W = 0; // width of channel signal + parameter ST_ERROR_W = 0; // width of error signal + parameter ST_EMPTY_W = 0; // width of empty signal, ST_EMPTY_W = log2(`ST_NUMSYMBOLS) + + parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles + parameter ST_MAX_CHANNELS = 1; // maximum number of channels + + parameter USE_PACKET = 0; // data transfer in packet format + parameter USE_CHANNEL = 0; // use channel port + parameter USE_ERROR = 0; // use error port + parameter USE_READY = 1; // use ready port + parameter USE_VALID = 1; // use valid port + parameter USE_EMPTY = 0; // use empty port + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MAX_EMPTY = 2**(ST_EMPTY_W) - 1; + localparam NUM_CHANNEL = ST_MAX_CHANNELS+1; + + localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data + ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel + 1 + // valid + 1 + // startofpacket + 1 + // endofpacket + ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error + ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty + 1; // ready + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Monitor Interface - will be defined as Streaming Sink + input [(TAP_W*ST_BEATSPERCYCLE)-ST_BEATSPERCYCLE:0] tap; + + // =cut + + function int lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + + //-------------------------------------------------------------------------- + // synthesis translate_off + + import verbosity_pkg::*; + + typedef bit [lindex(ST_DATA_W) :0] STData_t; + typedef bit [lindex(ST_CHANNEL_W) :0] STChannel_t; + typedef bit [lindex(ST_EMPTY_W) :0] STEmpty_t; + typedef bit [lindex(ST_ERROR_W) :0] STError_t; + + event signal_fatal_error; + + event event_a_valid_legal; + event event_a_empty_legal; + event event_a_no_data_outside_packet; + event event_a_non_missing_endofpacket; + event event_a_non_missing_startofpacket; + event event_a_less_than_max_channel; + + string fatal_message = "*unitialized*"; + string message = "*unitialized*"; + + bit enable_a_valid_legal = 1; + bit enable_a_empty_legal = 1; + bit enable_a_no_data_outside_packet = 1; + bit enable_a_non_missing_endofpacket = 1; + bit enable_a_non_missing_startofpacket = 1; + bit enable_a_less_than_max_channel = 1; + + //-------------------------------------------------------------------------- + // unpack Avalon bus interface tap into individual port signals + logic ready; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_DATA_W):0] data; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] channel; + logic [lindex(ST_BEATSPERCYCLE):0] valid; + logic [lindex(ST_BEATSPERCYCLE):0] startofpacket; + logic [lindex(ST_BEATSPERCYCLE):0] endofpacket; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_ERROR_W):0] error; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_EMPTY_W):0] empty; + + always_comb begin + data <= tap[lindex(ST_DATA_W*ST_BEATSPERCYCLE)+lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+ + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4: + lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4]; + + channel <= (USE_CHANNEL == 1)? + tap[lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+ + lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3] : 0; + + valid <= (USE_VALID == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+3] : 1; + + startofpacket <= (USE_PACKET == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+3] : 0; + + endofpacket <= (USE_PACKET == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3] : 0; + + error <= (USE_ERROR == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2: + lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2] : 0; + + empty <= (USE_EMPTY == 1)? tap[lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+1:1] : 0; + + ready <= (USE_READY == 1)? tap[0:0] : 1; + end + + //-------------------------------------------------------------------------- + // General Statistics Counters + //-------------------------------------------------------------------------- + + logic [31:0] clock_counter; + logic [31:0] sop_counter; + logic [31:0] eop_counter; + + logic sop_counter_reset = 0; + logic eop_counter_reset = 0; + logic [255:0] sop_channel_used = '0; + logic [255:0] eop_channel_used = '1; + logic [lindex(ST_BEATSPERCYCLE):0] sop_error_in_channel = '0; + logic [lindex(ST_BEATSPERCYCLE):0] eop_error_in_channel = '0; + logic [lindex(ST_BEATSPERCYCLE):0] data_outside_packet = '0; + + always @(posedge clk) begin + if (reset) + clock_counter <= 0; + else + clock_counter <= clock_counter + 1; + end + + always @(posedge clk) begin + if (reset) begin + sop_counter <= 0; + end else if (sop_counter_reset) begin + sop_counter_reset <= 0; + sop_counter <= 0; + end else begin + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + sop_counter <= (USE_PACKET && valid[i] && startofpacket[i]) ? sop_counter + 1 : sop_counter; + end + end + end + end + end + + always @(posedge clk) begin + if (reset) begin + eop_counter <= 0; + end else if (eop_counter_reset) begin + eop_counter_reset <= 0; + eop_counter <= 0; + end else begin + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + eop_counter <= (USE_PACKET && valid[i] && endofpacket[i]) ? eop_counter + 1 : eop_counter; + end + end + end + end + end + + //-------------------------------------------------------------------------- + // Private Methods + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // which instantiates and controls and queries state of this component. + // Test programs must only use these public access methods and events to + // communicate with this BFM component. The API and the module pins + // are the only interfaces in this component that are guaranteed to be + // stable. The API will be maintained for the life of the product. + // While we cannot prevent a test program from directly accessing internal + // tasks, functions, or data private to the BFM, there is no guarantee that + // these will be present in the future. In fact, it is best for the user + // to assume that the underlying implementation of this component can + // and will change. + // =cut + //-------------------------------------------------------------------------- + // Master Assertions API + function automatic void set_enable_a_valid_legal( // public + bit assert_enable + ); + // enable or disable a_valid_legal assertion + + enable_a_valid_legal = assert_enable; + endfunction + + function automatic void set_enable_a_empty_legal( // public + bit assert_enable + ); + // enable or disable a_empty_legal assertion + + enable_a_empty_legal = assert_enable; + endfunction + + function automatic void set_enable_a_no_data_outside_packet( // public + bit assert_enable + ); + // enable or disable a_no_data_outside_packet assertion + + enable_a_no_data_outside_packet = assert_enable; + endfunction + + function automatic void set_enable_a_non_missing_endofpacket( // public + bit assert_enable + ); + // enable or disable a_non_missing_endofpacket assertion + + enable_a_non_missing_endofpacket = assert_enable; + endfunction + + function automatic void set_enable_a_non_missing_startofpacket( // public + bit assert_enable + ); + // enable or disable a_non_missing_startofpacket assertion + + enable_a_non_missing_startofpacket = assert_enable; + endfunction + + function automatic void set_enable_a_less_than_max_channel( // public + bit assert_enable + ); + // enable or disable a_less_than_max_channel assertion + + enable_a_less_than_max_channel = assert_enable; + endfunction + // =cut + + function automatic logic [31:0] get_sop_counter(); + return sop_counter; + if (USE_PACKET == 0) begin + $sformat(message, "%m: No packet signals in this stream (USE_PACKET=0)."); + print(VERBOSITY_WARNING, message); + end + endfunction + + function automatic void reset_sop_counter(); + sop_counter_reset = 1'b1; + endfunction + + function automatic logic [31:0] get_eop_counter(); + return eop_counter; + if (USE_PACKET == 0) begin + $sformat(message, "%m: No packet signals in this stream (USE_PACKET=0)."); + print(VERBOSITY_WARNING, message); + end + endfunction + + function automatic void reset_eop_counter(); + eop_counter_reset = 1'b1; + endfunction + + // remaining API declarations will go here + //-------------------------------------------------------------------------- + event fatal_error; + + always @(fatal_error) begin + $sformat(message, "%m: Terminate simulation."); + print(VERBOSITY_FAILURE, message); + abort_simulation(); + end + + //-------------------------------------------------------------------------- + // =head1 Assertion Checkers and Coverage Monitors + // The assertion checkers in this module are only executable on simulators + // supporting the SystemVerilog Assertion (SVA) language. + // Mentor Modelsim AE and SE do not support this. + // Simulators that are supported include: Synopsys VCS and Mentor questasim. + // The assertion checking logic in this module must be explicitly enabled + // so that designs using this module can still be compiled on Modelsim without + // changes. To disable assertions define the following macro in the testbench + // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA. + // =cut + //-------------------------------------------------------------------------- + + function automatic void print_assertion( + string message_in + ); + string message_out; + $sformat(message_out, "ASSERTION: %s", message_in); + print(VERBOSITY_FAILURE, message_out); + endfunction + + + // Counter for general assertion counters + always @(posedge clk) + begin + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + check_sop_eop_valid(i); + end + end else begin + data_outside_packet[i] = 0; + end + end + end + + always @(posedge clk) + begin + if (reset) begin + sop_channel_used = '0; + eop_channel_used = '1; + sop_error_in_channel = '0; + eop_error_in_channel = '0; + data_outside_packet = '0; + end + end + + task automatic check_sop_eop_valid(int current_beat); + if (startofpacket[current_beat]) begin + if (sop_channel_used[channel[current_beat]] == 1) + sop_error_in_channel[current_beat] = 1; + else begin + sop_channel_used[channel[current_beat]] = 1; + sop_error_in_channel[current_beat] = 0; + end + eop_channel_used[channel[current_beat]] = 0; + end + + if (endofpacket[current_beat]) begin + if (eop_channel_used[channel[current_beat]] == 1) + eop_error_in_channel[current_beat] = 1; + else begin + eop_channel_used[channel[current_beat]] = 1; + eop_error_in_channel[current_beat] = 0; + end + sop_channel_used[channel[current_beat]] = 0; + end + + if (!startofpacket[current_beat] && !endofpacket[current_beat]) begin + if (!sop_channel_used[channel[current_beat]]) begin + data_outside_packet[current_beat] = 1; + end else begin + data_outside_packet[current_beat] = 0; + end + end else begin + data_outside_packet[current_beat] = 0; + end + + endtask + + + // SVA assertion code lives within the following section block + // which is disabled when the macro DISABLE_ALTERA_AVALON_SIM_SVA is defined + + `ifdef DISABLE_ALTERA_AVALON_SIM_SVA + // SVA assertion code has been disabled + + `else + //-------------------------------------------------------------------------- + // ASSERTION CODE BEGIN + //-------------------------------------------------------------------------- + //------------------------------------------------------------------------------- + // =head2 Avalon Streaming Assertions + // The following are the assertions code focus on Streaming Source and Sink + // component checking + //------------------------------------------------------------------------------- + + //------------------------------------------------------------------------------------ + // =head3 p_valid_legal + // This property check if valid is not deasserted ST_READY_LATENCY cycle after ready + // is deasserted. + //------------------------------------------------------------------------------------ + property p_valid_legal(current_beat); + @(posedge clk && enable_a_valid_legal && USE_VALID && USE_READY && ST_READY_LATENCY > 0) + disable iff (reset) + !ready |-> ##ST_READY_LATENCY !valid[current_beat]; + endproperty + + genvar i; + for (i=0; i event_a_valid_legal; + print_assertion("valid asserted after ready deasserted"); + end + end + + //------------------------------------------------------------------------------------ + // =head3 p_empty_legal + // This property check if empty non zero while endofpacket is asserted or empty value + // larger or equal to ST_NUMSYMBOLS + //------------------------------------------------------------------------------------ + property p_empty_legal(current_beat); + @(posedge clk && enable_a_empty_legal && USE_EMPTY && USE_PACKET) + disable iff (reset) + valid[current_beat] && (empty[current_beat] > 0) && (clock_counter > 0) && + ((USE_READY && (ST_READY_LATENCY == 0) && ready) || + !USE_READY || (ST_READY_LATENCY > 0)) + |-> endofpacket[current_beat] && (empty[current_beat] < ST_NUMSYMBOLS); + endproperty + + for (i=0; i event_a_empty_legal; + print_assertion("illegal empty value"); + end + end + + //------------------------------------------------------------------------------------ + // =head3 p_no_data_outside_packet + // This property check if that valid is asserted outside the packet transfer + //------------------------------------------------------------------------------------ + property p_no_data_outside_packet(current_beat); + @(posedge clk && enable_a_no_data_outside_packet && USE_VALID && USE_PACKET) + disable iff (reset) + valid[current_beat] && !startofpacket[current_beat] && !endofpacket[current_beat] && + ((USE_READY && (ST_READY_LATENCY == 0) && ready) || + !USE_READY || (ST_READY_LATENCY > 0)) + |-> ##1 !data_outside_packet[current_beat]; + endproperty + + for (i=0; i event_a_no_data_outside_packet; + print_assertion("valid is asserted outside the packet transfer"); + end + end + + //------------------------------------------------------------------------------------ + // =head3 p_non_missing_endofpacket + // This property check if consecutive startofpacket without endofpacket occurs + //------------------------------------------------------------------------------------ + property p_non_missing_endofpacket(current_beat); + @(posedge clk && enable_a_non_missing_endofpacket && USE_PACKET) + disable iff (reset) + startofpacket[current_beat] && valid[current_beat] && + ((USE_READY && (ST_READY_LATENCY == 0) && ready) || + !USE_READY || (ST_READY_LATENCY > 0)) + |-> ##1 !sop_error_in_channel[current_beat]; + endproperty + + for (i=0; i event_a_non_missing_endofpacket; + print_assertion("consecutive startofpacket without endofpacket"); + end + end + + //------------------------------------------------------------------------------------ + // =head3 p_non_missing_startofpacket + // This property check if consecutive endofpacket without endofpacket occurs + //------------------------------------------------------------------------------------ + property p_non_missing_startofpacket(current_beat); + @(posedge clk && enable_a_non_missing_startofpacket && USE_PACKET) + disable iff (reset) + endofpacket[current_beat] && valid[current_beat] && !startofpacket[current_beat] && + ((USE_READY && (ST_READY_LATENCY == 0) && ready) || + !USE_READY || (ST_READY_LATENCY > 0)) + |-> ##1 !eop_error_in_channel[current_beat]; + endproperty + + for (i=0; i event_a_non_missing_startofpacket; + print_assertion("consecutive endofpacket without startofpacket"); + end + end + + //------------------------------------------------------------------------------------ + // =head3 p_less_than_max_channel + // This property checks if channel size is less than ST_MAX_CHANNELS + //------------------------------------------------------------------------------------ + property p_less_than_max_channel(current_beat); + @(posedge clk && enable_a_less_than_max_channel && USE_CHANNEL) + disable iff (reset) + valid[current_beat] && (channel[current_beat] > 0) && (clock_counter > 0) && + ((USE_READY && (ST_READY_LATENCY == 0) && ready) || + !USE_READY || (ST_READY_LATENCY > 0)) + |-> (channel[current_beat] <= ST_MAX_CHANNELS); + endproperty + + for (i=0; i event_a_less_than_max_channel; + print_assertion("channel size must be within ST_MAX_CHANNELS"); + end + end + + // =cut + + //-------------------------------------------------------------------------- + // ASSERTION CODE END + //-------------------------------------------------------------------------- + `endif + + // synthesis translate_on + +endmodule + + Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_coverage.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_coverage.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_coverage.sv (revision 49) @@ -0,0 +1,1651 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/main/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_coverage.sv $ +// $Revision: #7 $ +// $Date: 2009/04/16 $ +// $Author: klong $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_monitor_coverage +// =head1 SYNOPSIS +// Streaming Avalon Bus Protocol Checker +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module implements Avalon ST protocol coverage processing for simulation. +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_avalon_st_monitor_coverage( + clk, + reset, + tap + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // number of bits in one symbols + parameter ST_NUMSYMBOLS = 4; // number of symbols in one data + parameter ST_CHANNEL_W = 0; // width of channel signal + parameter ST_ERROR_W = 0; // width of error signal + parameter ST_EMPTY_W = 0; // width of empty signal + + parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles + parameter ST_MAX_CHANNELS = 1; // maximum number of channels + + parameter USE_PACKET = 0; // data transfer in packet format + parameter USE_CHANNEL = 0; // use channel port + parameter USE_ERROR = 0; // use error port + parameter USE_READY = 1; // use ready port + parameter USE_VALID = 1; // use valid port + parameter USE_EMPTY = 0; // use empty port + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + + parameter ST_MAX_PACKET_SIZE = 1; // Max number of packet size covered + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MAX_EMPTY = 2**(ST_EMPTY_W) - 1; + localparam NUM_CHANNEL = ST_MAX_CHANNELS+1; + + + localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data + ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel + 1 + // valid + 1 + // startofpacket + 1 + // endofpacket + ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error + ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty + 1; // ready + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Monitor Interface - will be defined as Streaming Sink + input [(TAP_W*ST_BEATSPERCYCLE)-ST_BEATSPERCYCLE:0] tap; + + // =cut + + function int lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + + function automatic int __floor1( + bit [31:0] arg + ); + __floor1 = (arg <1) ? 1 : arg; + endfunction + + + //-------------------------------------------------------------------------- + // synthesis translate_off + + import verbosity_pkg::*; + + typedef bit [lindex(ST_DATA_W) :0] STData_t; + typedef bit [lindex(ST_CHANNEL_W) :0] STChannel_t; + typedef bit [lindex(ST_EMPTY_W) :0] STEmpty_t; + typedef bit [lindex(ST_ERROR_W) :0] STError_t; + + string message = "*unitialized*"; + + bit covergroup_settings_changed_flag = 0; + bit enable_c_packet_no_idles_no_back_pressure = 1; + bit enable_c_packet_with_idles = 1; + bit enable_c_packet_with_back_pressure = 1; + bit enable_c_channel_change_in_packet = 1; + bit enable_c_empty = 1; + bit enable_c_transfer = 1; + bit enable_c_error = 1; + bit enable_c_packet = 1; + bit enable_c_b2b_packet_different_channel = 1; + bit enable_c_b2b_packet_same_channel = 1; + bit enable_c_b2b_data_different_channel = 1; + bit enable_c_b2b_data_same_channel = 1; + bit enable_c_valid_non_ready = 1; + bit enable_c_non_valid_ready = 1; + bit enable_c_non_valid_non_ready = 1; + bit enable_c_transaction_after_reset = 1; + bit enable_c_packet_size = 1; + bit enable_c_multiple_packet_per_cycle = 1; + bit enable_c_single_packet_per_cycle = 1; + bit enable_c_idle_beat_between_packet = 1; + bit enable_c_all_idle_beats = 1; + bit enable_c_all_valid_beats = 1; + bit enable_c_partial_valid_beats = 1; + bit enable_c_b2b_packet_within_single_cycle = 1; + bit enable_c_b2b_packet_in_different_cycle = 1; + bit enable_c_error_in_middle_of_packet = 1; + + //-------------------------------------------------------------------------- + // unpack Avalon bus interface tap into individual port signals + logic ready; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_DATA_W):0] data; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] channel; + logic [lindex(ST_BEATSPERCYCLE):0] valid; + logic [lindex(ST_BEATSPERCYCLE):0] startofpacket; + logic [lindex(ST_BEATSPERCYCLE):0] endofpacket; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_ERROR_W):0] error; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_EMPTY_W):0] empty; + + always_comb begin + data <= tap[lindex(ST_DATA_W*ST_BEATSPERCYCLE)+lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+ + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4: + lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4]; + + channel <= (USE_CHANNEL == 1)? + tap[lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+ + lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3] : 0; + + valid <= (USE_VALID == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+3] : + (reset == 1)? 'x: 1; + + startofpacket <= (USE_PACKET == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+3] : 0; + + endofpacket <= (USE_PACKET == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+2: + lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3] : 0; + + error <= (USE_ERROR == 1)? + tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2: + lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2] : 0; + + empty <= (USE_EMPTY == 1)? tap[lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+1:1] : 0; + + ready <= (USE_READY == 1)? tap[0:0] : 1; + end + + //-------------------------------------------------------------------------- + // General Statistics Counters + //-------------------------------------------------------------------------- + + logic [31:0] clock_counter; + logic [31:0] sop_counter; + logic [31:0] eop_counter; + + logic sop_counter_reset = 0; + logic eop_counter_reset = 0; + + logic [lindex(NUM_CHANNEL):0] packet_no_idles_no_back_pressure_flag = '1; + logic [lindex(NUM_CHANNEL):0] packet_with_back_pressure_flag = 0; + logic [lindex(NUM_CHANNEL):0] channel_change_in_packet_flag = 0; + logic [lindex(NUM_CHANNEL):0] packet_with_idles_flag = 0; + logic [31:0] idles_between_b2b_packet_same_channel_counter = 0; + logic [31:0] idles_between_b2b_packet_different_channel_counter = 0; + logic [31:0] idles_between_b2b_data_same_channel_counter = 0; + logic [31:0] idles_between_b2b_data_different_channel_counter = 0; + logic [lindex(NUM_CHANNEL):0] current_packet = 0; + logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] past_channel = 0; + logic [lindex(ST_BEATSPERCYCLE):0] past_endofpacket = 0; + logic idles_between_packet_same_channel_sampled = 0; + logic idles_between_packet_different_channel_sampled = 0; + logic non_valid_ready_sampled = 0; + logic non_valid_non_ready_sampled = 0; + logic [lindex(ST_BEATSPERCYCLE):0] current_beat = 0; + logic [lindex(ST_BEATSPERCYCLE):0] current_beat_2 = 0; + logic [31:0] error_bit_num = 0; + logic [31:0] changed_channel = 0; + logic transaction_after_reset = 0; + logic all_valid_beats_flag = 0; + logic all_invalid_beats_flag = 0; + logic partial_valid_beats_flag = 0; + logic [31:0] idles_between_b2b_packet_transaction_counter = 0; + logic [31:0] idles_between_packet_within_single_transaction_sampled = 0; + logic [31:0] packet_per_transaction = 0; + logic [lindex(NUM_CHANNEL):0][31:0] packet_size = 0; + logic [31:0] error_in_middle_of_packet = 0; + logic [31:0] idles_between_packet_in_different_transaction_sampled = 0; + logic [31:0] invalid_beat_between_packet = 0; + logic packet_per_transaction_flag = 0; + logic channel_change = 0; + logic reset_status = 0; + + always @(posedge clk) begin + if (reset) + clock_counter <= 0; + else + clock_counter <= clock_counter + 1; + end + + always @(posedge clk) begin + if (reset) begin + sop_counter <= 0; + end else if (sop_counter_reset) begin + sop_counter_reset <= 0; + sop_counter <= 0; + end else begin + sop_counter <= (USE_PACKET && valid && startofpacket) ? + sop_counter + 1 : + sop_counter; + end + end + + always @(posedge clk) begin + if (reset) begin + eop_counter <= 0; + end else if (eop_counter_reset) begin + eop_counter_reset <= 0; + eop_counter <= 0; + end else begin + eop_counter <= (USE_PACKET && valid && endofpacket) ? + eop_counter + 1 : eop_counter; + end + end + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // which instantiates and controls and queries state of this component. + // Test programs must only use these public access methods and events to + // communicate with this BFM component. The API and the module pins + // are the only interfaces in this component that are guaranteed to be + // stable. The API will be maintained for the life of the product. + // While we cannot prevent a test program from directly accessing internal + // tasks, functions, or data private to the BFM, there is no guarantee that + // these will be present in the future. In fact, it is best for the user + // to assume that the underlying implementation of this component can + // and will change. + // =cut + //-------------------------------------------------------------------------- + + // ST Coverage API + function automatic void set_enable_c_packet_no_idles_no_back_pressure( // public + bit cover_enable + ); + // enable or disable c_packet_no_idles_no_back_pressure cover group + + enable_c_packet_no_idles_no_back_pressure = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_packet_no_idles_no_back_pressure"); + endfunction + + function automatic void set_enable_c_packet_with_idles( // public + bit cover_enable + ); + // enable or disable c_packet_with_idles cover group + + enable_c_packet_with_idles = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_packet_with_idles"); + endfunction + + function automatic void set_enable_c_packet_with_back_pressure( // public + bit cover_enable + ); + // enable or disable c_packet_with_back_pressure cover group + + enable_c_packet_with_back_pressure = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_packet_with_back_pressure"); + endfunction + + function automatic void set_enable_c_channel_change_in_packet( // public + bit cover_enable + ); + // enable or disable c_channel_change_in_packet cover group + + enable_c_channel_change_in_packet = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_channel_change_in_packet"); + endfunction + + function automatic void set_enable_c_empty( // public + bit cover_enable + ); + // enable or disable c_empty cover group + + enable_c_empty = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_empty"); + endfunction + + function automatic void set_enable_c_transfer( // public + bit cover_enable + ); + // enable or disable c_transfer cover group + + enable_c_transfer = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_transfer"); + endfunction + + function automatic void set_enable_c_error( // public + bit cover_enable + ); + // enable or disable c_error cover group + + enable_c_error = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_error"); + endfunction + + function automatic void set_enable_c_packet( // public + bit cover_enable + ); + // enable or disable c_packet cover group + + enable_c_packet = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_packet"); + endfunction + + function automatic void set_enable_c_b2b_packet_different_channel( // public + bit cover_enable + ); + // enable or disable c_b2b_packet_different_channel cover group + + enable_c_b2b_packet_different_channel = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_different_channel"); + endfunction + + function automatic void set_enable_c_b2b_packet_same_channel( // public + bit cover_enable + ); + // enable or disable c_b2b_packet_same_channel cover group + + enable_c_b2b_packet_same_channel = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_same_channel"); + endfunction + + function automatic void set_enable_c_b2b_data_different_channel( // public + bit cover_enable + ); + // enable or disable c_b2b_data_different_channel cover group + + enable_c_b2b_data_different_channel = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_data_different_channel"); + endfunction + + function automatic void set_enable_c_b2b_data_same_channel( // public + bit cover_enable + ); + // enable or disable c_b2b_data_same_channel cover group + + enable_c_b2b_data_same_channel = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_data_same_channel"); + endfunction + + function automatic void set_enable_c_valid_non_ready( // public + bit cover_enable + ); + // enable or disable c_valid_non_ready cover group + + enable_c_valid_non_ready = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_valid_non_ready"); + endfunction + + function automatic void set_enable_c_non_valid_ready( // public + bit cover_enable + ); + // enable or disable c_non_valid_ready cover group + + enable_c_non_valid_ready = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_non_valid_ready"); + endfunction + + function automatic void set_enable_c_non_valid_non_ready( // public + bit cover_enable + ); + // enable or disable c_non_valid_non_ready cover group + + enable_c_non_valid_non_ready = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_non_valid_non_ready"); + endfunction + + function automatic void set_enable_c_transaction_after_reset( // public + bit cover_enable + ); + // enable or disable transaction_after_reset cover group + + enable_c_transaction_after_reset = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_transaction_after_reset"); + endfunction + + function automatic void set_enable_c_packet_size( // public + bit cover_enable + ); + // enable or disable c_packet_size cover group + + enable_c_packet_size = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_packet_size"); + endfunction + + function automatic void set_enable_c_multiple_packet_per_cycle( // public + bit cover_enable + ); + // enable or disable c_multiple_packet_per_cycle cover group + + enable_c_multiple_packet_per_cycle = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_multiple_packet_per_cycle"); + endfunction + + function automatic void set_enable_c_single_packet_per_cycle( // public + bit cover_enable + ); + // enable or disable c_single_packet_per_cycle cover group + + enable_c_single_packet_per_cycle = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_single_packet_per_cycle"); + endfunction + + function automatic void set_enable_c_idle_beat_between_packet( // public + bit cover_enable + ); + // enable or disable c_idle_beat_between_packet cover group + + enable_c_idle_beat_between_packet = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_idle_beat_between_packet"); + endfunction + + function automatic void set_enable_c_all_valid_beats( // public + bit cover_enable + ); + // enable or disable c_all_valid_beats cover group + + enable_c_all_valid_beats = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_all_valid_beats"); + endfunction + + function automatic void set_enable_c_all_idle_beats( // public + bit cover_enable + ); + // enable or disable c_all_idle_beats cover group + + enable_c_all_idle_beats = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_all_idle_beats"); + endfunction + + function automatic void set_enable_c_partial_valid_beats( // public + bit cover_enable + ); + // enable or disable c_partial_valid_beats cover group + + enable_c_partial_valid_beats = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_partial_valid_beats"); + endfunction + + function automatic void set_enable_c_b2b_packet_within_single_cycle( // public + bit cover_enable + ); + // enable or disable c_b2b_packet_within_single_cycle cover group + + enable_c_b2b_packet_within_single_cycle = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_within_single_cycle"); + endfunction + + function automatic void set_enable_c_b2b_packet_in_different_transaction( // public + bit cover_enable + ); + // enable or disable c_b2b_packet_in_different_transaction cover group + + enable_c_b2b_packet_in_different_cycle = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_in_different_cycle"); + endfunction + + function automatic void set_enable_c_error_in_middle_of_packet( // public + bit cover_enable + ); + // enable or disable c_error_in_middle_of_packet cover group + + enable_c_error_in_middle_of_packet = cover_enable; + coverage_settings_check(covergroup_settings_changed_flag, "c_error_in_middle_of_packet"); + endfunction + + // =cut + + function automatic logic [31:0] get_sop_counter(); + return sop_counter; + if (USE_PACKET == 0) begin + $sformat(message, "%m: No packet signals in this stream (USE_PACKET = 0)."); + print(VERBOSITY_WARNING, message); + end + endfunction + + function automatic void reset_sop_counter(); + sop_counter_reset = 1'b1; + endfunction + + function automatic logic [31:0] get_eop_counter(); + return eop_counter; + if (USE_PACKET == 0) begin + $sformat(message, "%m: No packet signals in this stream (USE_PACKET = 0)."); + print(VERBOSITY_WARNING, message); + end + endfunction + + function automatic void reset_eop_counter(); + eop_counter_reset = 1'b1; + endfunction + + function void coverage_settings_check( + bit cover_flag, + string cover_name + ); + string message; + if (cover_flag) begin + $sformat(message, "%m: - Changing %s covergroup settings during run-time will not be reflected", + cover_name); + print(VERBOSITY_WARNING, message); + end + endfunction + + `ifdef DISABLE_ALTERA_AVALON_SIM_SVA + // SVA coverage code is disabled when this macro is defined + `else + //-------------------------------------------------------------------------- + // COVERAGE CODE BEGIN + //-------------------------------------------------------------------------- + + function automatic void print_assertion( //private + string message_in + ); + string message_out; + $sformat(message_out, "ASSERTION: %s", message_in); + print(VERBOSITY_FAILURE, message_out); + endfunction + + function logic [1023:0] pow( //private + input int power_value + ); + // This method return the maximum supported value for the port width. + pow = (2**(power_value) - 1); + endfunction + + function automatic logic [31:0] count_ones ( //private + input logic [1023:0] value + ); + // This method return number of 1 bits + if (value == 0) + count_ones = 0; + else if (value == 'x) begin + count_ones = 'x; + end else begin + for( count_ones = 0; value!= 0; value = value >> 1 ) + count_ones += value & 1'b1; + end + endfunction + + function integer log2( //private + input int value + ); + // Mathematic logarithm function with base as 2. + value = value-1; + for (log2=0; value>0; log2=log2+1) + begin + value = value>>1; + end + endfunction + + task sample_non_valid_ready(); + fork + begin + repeat(ST_READY_LATENCY) begin + @(posedge clk); + end + non_valid_ready_sampled = 1; + end + join_none + endtask + + //-------------------------------------------------------------------------- + // =head1 Assertion Checkers and Coverage Monitors + // The assertion checkers in this module are only executable on simulators + // supporting the SystemVerilog Assertion (SVA) language. + // Mentor Modelsim AE and SE do not support this. + // Simulators that are supported include: Synopsys VCS and Mentor questasim. + // The assertion checking logic in this module must be explicitly enabled + // so that designs using this module can still be compiled on Modelsim without + // changes. To disable assertions define the following macro in the testbench + // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA. + // =cut + //-------------------------------------------------------------------------- + + + always @(posedge clk) + begin + if (!reset) begin + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + + if (enable_c_transaction_after_reset && USE_VALID) begin + c_transaction_after_reset.sample(); + transaction_after_reset = 0; + end + + if (enable_c_transfer && USE_VALID && USE_READY) begin + c_transfer.sample(); + end + + if (enable_c_empty && USE_EMPTY) begin + c_empty.sample(); + end + + if (enable_c_error && USE_ERROR) begin + for (int j = 0; j < ST_ERROR_W; j++) begin + if (error[current_beat][j] == 1) begin + error_bit_num = j; + c_error.sample(); + end + end + end + + if (startofpacket[i]) begin + if (!endofpacket[i]) begin + current_packet[channel[i]] = 1; + end else begin + packet_size[channel[i]]++; + end + + if (error[i] > 0) begin + error_in_middle_of_packet = 1; + end else begin + error_in_middle_of_packet = 0; + end + + if (enable_c_error_in_middle_of_packet && USE_ERROR && USE_PACKET) begin + c_error_in_middle_of_packet.sample(); + error_in_middle_of_packet = 0; + end + + packet_no_idles_no_back_pressure_flag[channel[i]] = 1; + + //counter to determine time to sample signal + if (i == 0) begin + if (channel[i] != past_channel[ST_BEATSPERCYCLE-1]) begin + idles_between_packet_same_channel_sampled = 0; + if (past_endofpacket[ST_BEATSPERCYCLE-1] == 1) begin + idles_between_packet_different_channel_sampled = 1; + idles_between_packet_in_different_transaction_sampled = 1; + end else begin + idles_between_packet_different_channel_sampled = 0; + idles_between_packet_in_different_transaction_sampled = 0; + end + end else begin + idles_between_packet_different_channel_sampled = 0; + if (past_endofpacket[ST_BEATSPERCYCLE-1] == 1) begin + idles_between_packet_same_channel_sampled = 1; + idles_between_packet_in_different_transaction_sampled = 1; + end else begin + idles_between_packet_same_channel_sampled = 0; + idles_between_packet_in_different_transaction_sampled = 0; + end + end + idles_between_packet_within_single_transaction_sampled = 0; + end else begin + if (channel[i] != channel[i-1]) begin + idles_between_packet_same_channel_sampled = 0; + if (endofpacket[i-1] == 1) begin + idles_between_packet_different_channel_sampled = 1; + idles_between_packet_within_single_transaction_sampled = 1; + end else begin + idles_between_packet_different_channel_sampled = 0; + idles_between_packet_within_single_transaction_sampled = 0; + end + end else begin + idles_between_packet_different_channel_sampled = 0; + if (endofpacket[i-1] == 1) begin + idles_between_packet_same_channel_sampled = 1; + idles_between_packet_within_single_transaction_sampled = 1; + end else begin + idles_between_packet_same_channel_sampled = 0; + idles_between_packet_within_single_transaction_sampled = 0; + end + end + idles_between_packet_in_different_transaction_sampled = 0; + end + + if (enable_c_b2b_packet_different_channel && USE_CHANNEL && USE_PACKET && USE_VALID && (ST_MAX_CHANNELS > 0)) begin + if (idles_between_packet_different_channel_sampled) begin + c_b2b_packet_different_channel.sample(); + end + end + + if (enable_c_b2b_packet_same_channel && USE_PACKET && USE_VALID) begin + if (idles_between_packet_same_channel_sampled) begin + c_b2b_packet_same_channel.sample(); + end + end + + if (enable_c_b2b_packet_within_single_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + if (idles_between_packet_within_single_transaction_sampled) begin + c_b2b_packet_within_single_cycle.sample(); + end + end + + if (enable_c_b2b_packet_in_different_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + if (idles_between_packet_in_different_transaction_sampled) begin + c_b2b_packet_in_different_cycle.sample(); + end + end + + if ((count_ones(current_packet) == 1) || ((count_ones(current_packet) == 0) &&(endofpacket[i]))) begin + if (enable_c_idle_beat_between_packet && USE_VALID && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin + c_idle_beat_between_packet.sample(); + invalid_beat_between_packet = 0; + end + end + end + + for (int j = 0; j 0)) begin + c_channel_change_in_packet.sample(); + channel_change_in_packet_flag[channel[i]] = 0; + end + + if (enable_c_packet_with_back_pressure && USE_READY && USE_PACKET) begin + c_packet_with_back_pressure.sample(); + packet_with_back_pressure_flag[channel[i]] = 0; + end + + if (enable_c_packet_size && USE_PACKET) begin + c_packet_size.sample(); + packet_size[channel[i]] = 0; + end + + end + + if (i == 0) begin + if (channel[i] != past_channel[ST_BEATSPERCYCLE-1]) begin + if (((count_ones(current_packet) == 1) && !startofpacket[i]) || + (count_ones(current_packet) > 1)) begin + if(current_packet[past_channel[ST_BEATSPERCYCLE-1]] == 1) begin + channel_change_in_packet_flag[past_channel[ST_BEATSPERCYCLE-1]] = 1; + end + end + end + end else begin + if (channel[i] != channel[i-1]) begin + if (((count_ones(current_packet) == 1) && !startofpacket[i]) || + (count_ones(current_packet) > 1)) begin + if(current_packet[channel[i-1]] == 1) begin + channel_change_in_packet_flag[channel[i-1]] = 1; + end + end + end + end + + end else begin + if (count_ones(current_packet) == 0) begin + invalid_beat_between_packet = 1; + end + end + end else if (USE_VALID && (valid[i] == 0)) begin + if (count_ones(current_packet) == 0) begin + invalid_beat_between_packet = 1; + end + end + + //counter for idles transaction + if (!valid[i]) begin + for (int j = 0; j 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + if (endofpacket[i]) begin + idles_between_b2b_packet_same_channel_counter = 0; + idles_between_b2b_packet_different_channel_counter = 0; + idles_between_b2b_packet_transaction_counter = 0; + end + end + + if ((!startofpacket[i] && !endofpacket[i]) || (USE_READY && (ST_READY_LATENCY == 0) && !ready)) begin + idles_between_b2b_packet_different_channel_counter++; + idles_between_b2b_packet_transaction_counter++; + end + end + + if (((USE_VALID && valid[i]) || !USE_VALID)) begin + if ((ST_READY_LATENCY > 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + if (enable_c_b2b_data_different_channel && USE_CHANNEL && USE_VALID && (ST_MAX_CHANNELS > 0)) begin + c_b2b_data_different_channel.sample(); + idles_between_b2b_data_different_channel_counter = 0; + end + + if (enable_c_b2b_data_same_channel && USE_VALID) begin + c_b2b_data_same_channel.sample(); + idles_between_b2b_data_same_channel_counter = 0; + end + end + end + + if (!reset_status) + transaction_after_reset = 0; + end + + // counter to capture previous cycle signal value + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + past_endofpacket[i] <= endofpacket[i]; + for (int k = i; k < ST_BEATSPERCYCLE; k++) begin + past_channel[k] <= channel[k]; + end + end else + past_endofpacket[i] <= 0; + end else begin + past_endofpacket[i] <= 0; + end + end + reset_status = 0; + end + end + + always @(posedge clk) + begin + if (!reset) begin + if (ready) begin + if (ST_READY_LATENCY == 0) begin + non_valid_ready_sampled = 1; + end else begin + sample_non_valid_ready(); + end + end + + if (enable_c_valid_non_ready && USE_READY && USE_VALID && (ST_READY_LATENCY == 0)) begin + for (int i=0; i 1)) begin + if ((ST_READY_LATENCY > 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + if (count_ones(valid) == ST_BEATSPERCYCLE) begin + all_valid_beats_flag = 1; + end else begin + all_valid_beats_flag = 0; + end + + if ((count_ones(valid) == 0) && (valid[0] == 0)) begin + all_invalid_beats_flag = 1; + end else begin + all_invalid_beats_flag = 0; + end + + if ((count_ones(valid) > 0) && (count_ones(valid) < ST_BEATSPERCYCLE)) begin + partial_valid_beats_flag = 1; + end else begin + partial_valid_beats_flag = 0; + end + + if (enable_c_all_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_all_valid_beats.sample(); + end + if (enable_c_all_idle_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_all_idle_beats.sample(); + end + if (enable_c_partial_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_partial_valid_beats.sample(); + end + end + end + + if (USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin + for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin + if (((USE_VALID && valid[i]) || !USE_VALID)) begin + if (i > 0) begin + for (int j = 0; j < i; j++) begin + if (valid[j] == 1) begin + packet_per_transaction_flag = 1; + end + if ((channel[i] != channel[j]) && valid[j]) begin + channel_change = 1; + end + end + if (channel_change && packet_per_transaction_flag) begin + packet_per_transaction++; + end else begin + if ((startofpacket[i]) && packet_per_transaction_flag) begin + packet_per_transaction++; + end + end + channel_change = 0; + end + end + + if (i == (ST_BEATSPERCYCLE-1)) begin + if (enable_c_multiple_packet_per_cycle && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin + c_multiple_packet_per_cycle.sample(); + end + + if (enable_c_single_packet_per_cycle && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin + if ((valid > 0)) begin + c_single_packet_per_cycle.sample(); + end + end + packet_per_transaction = 0; + end + end + end + packet_per_transaction_flag = 0; + end + end + end + + + always @(negedge reset) + begin + non_valid_non_ready_sampled = 1; + end + + //counter while reset + always @(posedge clk) + begin + if (reset) begin + non_valid_ready_sampled = 0; + non_valid_non_ready_sampled = 0; + packet_no_idles_no_back_pressure_flag = '1; + packet_with_back_pressure_flag = 0; + idles_between_b2b_packet_same_channel_counter = 0; + idles_between_b2b_packet_different_channel_counter = 0; + channel_change_in_packet_flag = 0; + packet_with_idles_flag = 0; + idles_between_packet_same_channel_sampled = 0; + idles_between_packet_different_channel_sampled = 0; + current_packet = 0; + idles_between_b2b_data_same_channel_counter = 0; + idles_between_b2b_data_different_channel_counter = 0; + past_channel = 0; + past_endofpacket = 0; + transaction_after_reset = 1; + current_beat = 0; + current_beat_2 = 0; + changed_channel = 0; + all_valid_beats_flag = 0; + all_invalid_beats_flag = 0; + partial_valid_beats_flag = 0; + idles_between_b2b_packet_transaction_counter = 0; + idles_between_packet_within_single_transaction_sampled = 0; + packet_per_transaction = 0; + packet_size = 0; + error_in_middle_of_packet = 0; + idles_between_packet_in_different_transaction_sampled = 0; + invalid_beat_between_packet = 0; + packet_per_transaction_flag = 0; + reset_status = 1; + channel_change = 0; + end + end + + // Flag for initial coverage settings + initial begin + #1 covergroup_settings_changed_flag = 1; + end + + //------------------------------------------------------------------------------- + // =head2 Streaming Coverages + // The following are the cover group code focus on ST Monitor component coverage + //------------------------------------------------------------------------------- + + //------------------------------------------------------------------------------- + // =head3 c_empty + // This cover group covers the different empty value + //------------------------------------------------------------------------------- + + covergroup cg_empty; + cp_empty: coverpoint empty[current_beat] + { + bins cg_empty_cp_empty [] = {[0:ST_MAX_EMPTY]}; + } + option.per_instance = 1; + endgroup + + cg_empty c_empty; + + initial begin + #1 if (enable_c_empty && USE_EMPTY) begin + c_empty = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_error + // This cover group covers the different error value + //------------------------------------------------------------------------------- + + covergroup cg_error; + cp_error: coverpoint error_bit_num + { + bins cg_error_cp_error [] = {[0:lindex(ST_ERROR_W)]}; + } + option.per_instance = 1; + endgroup + + cg_error c_error; + + initial begin + #1 if (enable_c_error && USE_ERROR) begin + c_error = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_transfer + // This cover group covers valid is asserted for different channel. + //------------------------------------------------------------------------------- + + covergroup cg_transfer; + cp_transfer: coverpoint (channel[current_beat]) + { + bins cg_transfer_cp_transfer [] = {[0:(USE_CHANNEL == 0? 0:lindex(NUM_CHANNEL))]}; + } + option.per_instance = 1; + endgroup + + cg_transfer c_transfer; + + initial begin + #1 if (enable_c_transfer && USE_VALID && USE_READY) begin + c_transfer = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_packet + // This cover group covers packet transfer for different channel. + //------------------------------------------------------------------------------- + + covergroup cg_packet; + cp_packet: coverpoint (channel[current_beat]) + { + bins cg_packet_cp_packet [] = {[0:(USE_CHANNEL == 0? 0:lindex(NUM_CHANNEL))]}; + } + option.per_instance = 1; + endgroup + + cg_packet c_packet; + + initial begin + #1 if (enable_c_packet && USE_PACKET) begin + c_packet = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_valid_non_ready + // This cover group covers valid is asserted while ready is deasserted. + //------------------------------------------------------------------------------- + + covergroup cg_valid_non_ready; + cp_valid_non_ready: coverpoint ready + { + bins cg_valid_non_ready_cp_valid_non_ready = {0}; + } + option.per_instance = 1; + endgroup + + cg_valid_non_ready c_valid_non_ready; + + initial begin + #1 if (enable_c_valid_non_ready && USE_READY + && USE_VALID && (ST_READY_LATENCY == 0)) begin + c_valid_non_ready = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_non_valid_ready + // This cover group covers valid is deasserted at the N+ST_READ_LATENCY + // clock cycle if ready is asserted at N clock cycle. + //------------------------------------------------------------------------------- + + covergroup cg_non_valid_ready; + cp_non_valid_ready: coverpoint valid[current_beat_2] + { + bins cg_non_valid_ready_cp_non_valid_ready = {0}; + } + option.per_instance = 1; + endgroup + + cg_non_valid_ready c_non_valid_ready; + + initial begin + #1 if (enable_c_non_valid_ready && USE_READY && USE_VALID) begin + c_non_valid_ready = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_non_valid_non_ready + // This cover group covers idle cycle. + //------------------------------------------------------------------------------- + + covergroup cg_non_valid_non_ready; + cp_non_valid_non_ready: coverpoint ready + { + bins cg_non_valid_non_ready_cp_non_valid_non_ready = {0}; + } + option.per_instance = 1; + endgroup + + cg_non_valid_non_ready c_non_valid_non_ready; + + initial begin + #1 if (enable_c_non_valid_non_ready && USE_READY && USE_VALID) begin + c_non_valid_non_ready = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_packet_no_idles_no_back_pressure + // This cover group covers packet transaction without back pressure and idle + // cycles. + //------------------------------------------------------------------------------- + + covergroup cg_packet_no_idles_no_back_pressure; + cp_packet_no_idles_no_back_pressure: coverpoint packet_no_idles_no_back_pressure_flag[channel[current_beat]] + { + bins cg_packet_no_idles_no_back_pressure_cp_packet_no_idles_no_back_pressure = {1}; + } + option.per_instance = 1; + endgroup + + cg_packet_no_idles_no_back_pressure c_packet_no_idles_no_back_pressure; + + initial begin + #1 if (enable_c_packet_no_idles_no_back_pressure && USE_READY && USE_VALID && USE_PACKET) begin + c_packet_no_idles_no_back_pressure = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_packet_with_back_pressure + // This cover group covers packet transaction being back pressured. + //------------------------------------------------------------------------------- + + covergroup cg_packet_with_back_pressure; + cp_packet_with_back_pressure: coverpoint packet_with_back_pressure_flag[channel[current_beat]] + { + bins cg_packet_with_back_pressure_cp_packet_with_back_pressure = {1}; + } + option.per_instance = 1; + endgroup + + cg_packet_with_back_pressure c_packet_with_back_pressure; + + initial begin + #1 if (enable_c_packet_with_back_pressure && USE_READY && USE_PACKET) begin + c_packet_with_back_pressure = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_packet_with_idles + // This cover group covers covers packet transaction with idle cycles + //------------------------------------------------------------------------------- + + covergroup cg_packet_with_idles; + cp_packet_with_idles: coverpoint packet_with_idles_flag[channel[current_beat]] + { + bins cg_packet_with_idles_cp_packet_with_idles = {1}; + } + option.per_instance = 1; + endgroup + + cg_packet_with_idles c_packet_with_idles; + + initial begin + #1 if (enable_c_packet_with_idles && USE_PACKET && USE_VALID) begin + c_packet_with_idles = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_channel_change_in_packet + // This cover group covers changing channel within a packet transaction. + //------------------------------------------------------------------------------- + + covergroup cg_channel_change_in_packet; + cp_channel_change_in_packet: coverpoint channel_change_in_packet_flag[channel[current_beat]] + { + bins cg_channel_change_in_packet_cp_channel_change_in_packet = {1}; + } + option.per_instance = 1; + endgroup + + cg_channel_change_in_packet c_channel_change_in_packet; + + initial begin + #1 if (enable_c_channel_change_in_packet && USE_CHANNEL && USE_PACKET && (ST_MAX_CHANNELS > 0)) begin + c_channel_change_in_packet = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_b2b_packet_different_channel + // This cover group covers back to back packet transfer for different channel. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_packet_different_channel; + cp_b2b_packet_different_channel: coverpoint idles_between_b2b_packet_different_channel_counter + { + bins cg_b2b_packet_different_channel_cp_b2b_packet_different_channel = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_packet_different_channel c_b2b_packet_different_channel; + + initial begin + #1 if (enable_c_b2b_packet_different_channel && USE_CHANNEL && USE_PACKET && USE_VALID && (ST_MAX_CHANNELS > 0)) begin + c_b2b_packet_different_channel = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_b2b_packet_same_channel + // This cover group covers back to back packet transfer for same channel. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_packet_same_channel; + cp_b2b_packet_same_channel: coverpoint idles_between_b2b_packet_same_channel_counter + { + bins cg_b2b_packet_same_channel_cp_b2b_packet_same_channel = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_packet_same_channel c_b2b_packet_same_channel; + + initial begin + #1 if (enable_c_b2b_packet_same_channel && USE_PACKET && USE_VALID) begin + c_b2b_packet_same_channel = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_b2b_data_different_channel + // This cover group covers back to back data transfer for different channel. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_data_different_channel; + cp_b2b_data_different_channel: coverpoint idles_between_b2b_data_different_channel_counter + { + bins cg_b2b_data_different_channel_cp_b2b_data_different_channel = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_data_different_channel c_b2b_data_different_channel; + + initial begin + #1 if (enable_c_b2b_data_different_channel && USE_CHANNEL && USE_VALID && (ST_MAX_CHANNELS > 0)) begin + c_b2b_data_different_channel = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_b2b_data_same_channel + // This cover group covers back to back data transfer for same channel. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_data_same_channel; + cp_b2b_data_same_channel: coverpoint idles_between_b2b_data_same_channel_counter + { + bins cg_b2b_data_same_channel_cp_b2b_data_same_channel = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_data_same_channel c_b2b_data_same_channel; + + initial begin + #1 if (enable_c_b2b_data_same_channel && USE_VALID) begin + c_b2b_data_same_channel = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_transaction_after_reset + // This cover group covers first transaction after reset. + //------------------------------------------------------------------------------- + + covergroup cg_transaction_after_reset; + cp_transaction_after_reset: coverpoint transaction_after_reset + { + bins cg_transaction_after_reset_cp_transaction_after_reset = {1}; + } + option.per_instance = 1; + endgroup + + cg_transaction_after_reset c_transaction_after_reset; + + initial begin + #1 if (enable_c_transaction_after_reset && USE_VALID) begin + c_transaction_after_reset = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_packet_size + // This covers different size of packet from one until parameter + // ST_MAX_PACKET_SIZE. For the transaction larger than ST_MAX_PACKET_SIZE will + // count into another bin. + //------------------------------------------------------------------------------- + + covergroup cg_packet_size; + cp_packet_size: coverpoint packet_size[channel[current_beat]] + { + bins cg_packet_size_cp_packet_size [] = {[1:(ST_MAX_PACKET_SIZE < 1)? 1:ST_MAX_PACKET_SIZE]}; + bins cg_packet_size_cp_packet_size_high = {[(ST_MAX_PACKET_SIZE < 1)? 2:ST_MAX_PACKET_SIZE+1:$]}; + } + option.per_instance = 1; + endgroup + + cg_packet_size c_packet_size; + + initial begin + #1 if (enable_c_packet_size && USE_PACKET) begin + c_packet_size = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_multiple_packet_per_cycle + // This cover group covers number of transactions that carry multiple packets + // per single cycle. + //------------------------------------------------------------------------------- + + covergroup cg_multiple_packet_per_cycle; + cp_multiple_packet_per_cycle: coverpoint packet_per_transaction + { + bins cg_multiple_packet_per_cycle_cp_multiple_packet_per_cycle = {[1:(ST_BEATSPERCYCLE > 1)?ST_BEATSPERCYCLE:1]}; + } + option.per_instance = 1; + endgroup + + cg_multiple_packet_per_cycle c_multiple_packet_per_cycle; + + initial begin + #1 if (enable_c_multiple_packet_per_cycle && USE_PACKET && ST_BEATSPERCYCLE > 1) begin + c_multiple_packet_per_cycle = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_single_packet_per_cycle + // This cover group covers number of transactions that carry one packet + // per single cycle. + //------------------------------------------------------------------------------- + + covergroup cg_single_packet_per_cycle; + cp_single_packet_per_cycle: coverpoint packet_per_transaction + { + bins cg_single_packet_per_cycle_cp_single_packet_per_cycle = {0}; + } + option.per_instance = 1; + endgroup + + cg_single_packet_per_cycle c_single_packet_per_cycle; + + initial begin + #1 if (enable_c_single_packet_per_cycle && USE_PACKET && ST_BEATSPERCYCLE > 1) begin + c_single_packet_per_cycle = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_idle_beat_between_packet + // This cover group covers packet transaction that owns idle beats in between. + //------------------------------------------------------------------------------- + + covergroup cg_idle_beat_between_packet; + cp_idle_beat_between_packet: coverpoint invalid_beat_between_packet + { + bins cg_idle_beat_between_packet_cp_idle_beat_between_packet = {1}; + } + option.per_instance = 1; + endgroup + + cg_idle_beat_between_packet c_idle_beat_between_packet; + + initial begin + #1 if (enable_c_idle_beat_between_packet && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_idle_beat_between_packet = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_all_valid_beats + // This cover group covers number of transaction with all beats are valid. + //------------------------------------------------------------------------------- + + covergroup cg_all_valid_beats; + cp_all_valid_beats: coverpoint all_valid_beats_flag + { + bins cg_all_valid_beats_cp_all_valid_beats = {1}; + } + option.per_instance = 1; + endgroup + + cg_all_valid_beats c_all_valid_beats; + + initial begin + #1 if (enable_c_all_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_all_valid_beats = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_all_idle_beats + // This cover group covers number of transaction with all beats are idle. + //------------------------------------------------------------------------------- + + covergroup cg_all_idle_beats; + cp_all_idle_beats: coverpoint all_invalid_beats_flag + { + bins cg_all_idle_beats_cp_all_idle_beats = {1}; + } + option.per_instance = 1; + endgroup + + cg_all_idle_beats c_all_idle_beats; + + initial begin + #1 if (enable_c_all_idle_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_all_idle_beats = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_partial_valid_beats + // This cover group covers number of transaction with some beats are invalid and + // some beats are valid. + //------------------------------------------------------------------------------- + + covergroup cg_partial_valid_beats; + cp_partial_valid_beats: coverpoint partial_valid_beats_flag + { + bins cg_partial_valid_beats_cp_partial_valid_beats = {1}; + } + option.per_instance = 1; + endgroup + + cg_partial_valid_beats c_partial_valid_beats; + + initial begin + #1 if (enable_c_partial_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_partial_valid_beats = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_b2b_packet_within_single_cycle + // This cover group covers back to back packet transfer within single cycle. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_packet_within_single_cycle; + cp_b2b_packet_within_single_cycle: coverpoint idles_between_b2b_packet_transaction_counter + { + bins cg_b2b_packet_within_single_cycle_cp_b2b_packet_within_single_cycle = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_packet_within_single_cycle c_b2b_packet_within_single_cycle; + + initial begin + #1 if (enable_c_b2b_packet_within_single_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_b2b_packet_within_single_cycle = new(); + end + end + + + //------------------------------------------------------------------------------- + // =head3 c_b2b_packet_in_different_cycle + // This cover group covers back to back packet transfer in different cycle. + //------------------------------------------------------------------------------- + + covergroup cg_b2b_packet_in_different_cycle; + cp_b2b_packet_in_different_cycle: coverpoint idles_between_b2b_packet_transaction_counter + { + bins cg_b2b_packet_in_different_cycle_cp_b2b_packet_in_different_cycle = {0}; + } + option.per_instance = 1; + endgroup + + cg_b2b_packet_in_different_cycle c_b2b_packet_in_different_cycle; + + initial begin + #1 if (enable_c_b2b_packet_in_different_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin + c_b2b_packet_in_different_cycle = new(); + end + end + + //------------------------------------------------------------------------------- + // =head3 c_error_in_middle_of_packet + // This cover group covers assert error in the middle of a packet. + //------------------------------------------------------------------------------- + + covergroup cg_error_in_middle_of_packet; + cp_error_in_middle_of_packet: coverpoint error_in_middle_of_packet + { + bins cg_error_in_middle_of_packet_cp_error_in_middle_of_packet = {1}; + } + option.per_instance = 1; + endgroup + + cg_error_in_middle_of_packet c_error_in_middle_of_packet; + + initial begin + #1 if (enable_c_error_in_middle_of_packet && USE_PACKET && USE_ERROR) begin + c_error_in_middle_of_packet = new(); + end + end + + // =cut + + //-------------------------------------------------------------------------- + // COVERAGE CODE END + //-------------------------------------------------------------------------- + `endif + // synthesis translate_on + +endmodule + + Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv (revision 49) @@ -0,0 +1,404 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_transactions.sv $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +// $Author: swbranch $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_monitor_transactions +// =head1 SYNOPSIS +// Streaming Avalon Bus Protocol Checker +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module implements Avalon ST protocol transaction recording. +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_avalon_st_monitor_transactions( + clk, + reset, + tap + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // number of bits in one symbols + parameter ST_NUMSYMBOLS = 4; // number of symbols in one data + parameter ST_CHANNEL_W = 0; // width of channel signal + parameter ST_ERROR_W = 0; // width of error signal + parameter ST_EMPTY_W = 0; // width of empty signal + + parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles + parameter ST_MAX_CHANNELS = 1; // maximum number of channels + + parameter USE_PACKET = 0; // data transfer in packet format + parameter USE_CHANNEL = 0; // use channel port + parameter USE_ERROR = 0; // use error port + parameter USE_READY = 1; // use ready port + parameter USE_VALID = 1; // use valid port + parameter USE_EMPTY = 0; // use empty port + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + + parameter ST_MAX_PACKET_SIZE = 1; // Max number of packet size covered + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; + localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; + localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; + localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; + + localparam ST_MAX_EMPTY = 2**(ST_EMPTY_W) - 1; + localparam NUM_CHANNEL = (ST_MAX_CHANNELS > 1)? ST_MAX_CHANNELS:1; + localparam FIFO_MAX_LEVEL = 100; + localparam FIFO_THRESHOLD = 50; + + localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data + ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel + 1 + // valid + 1 + // startofpacket + 1 + // endofpacket + ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error + ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty + 1; // ready + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Monitor Interface - will be defined as Streaming Sink + input [(TAP_W*ST_BEATSPERCYCLE)-ST_BEATSPERCYCLE:0] tap; + + // =cut + + function int lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + + //-------------------------------------------------------------------------- + // synthesis translate_off + + import verbosity_pkg::*; + + //-------------------------------------------------------------------------- + // Private Types and Variables + //-------------------------------------------------------------------------- + + typedef logic [lindex(ST_DATA_W) :0] STData_t; + typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; + typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; + typedef logic [lindex(ST_ERROR_W) :0] STError_t; + + typedef logic [lindex(ST_MDATA_W) :0] STMData_t; + typedef logic [lindex(ST_MCHANNEL_W) :0] STMChannel_t; + typedef logic [lindex(ST_MEMPTY_W) :0] STMEmpty_t; + typedef logic [lindex(ST_MERROR_W) :0] STMError_t; + typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; + + typedef struct packed + { + bit [31:0] idles; + logic startofpacket; + logic endofpacket; + STChannel_t channel; + STData_t data; + STError_t error; + STEmpty_t empty; + } Transaction_t; + + Transaction_t current_transaction[ST_BEATSPERCYCLE]; + Transaction_t query_transaction; + Transaction_t transaction_queue[$]; + + // unpack Avalon bus interface tap into individual port signals + logic [lindex(ST_MDATA_W): 0] sink_data; + logic [lindex(ST_MCHANNEL_W): 0] sink_channel; + logic [ST_BEATSPERCYCLE-1: 0] sink_valid; + logic [ST_BEATSPERCYCLE-1: 0] sink_startofpacket; + logic [ST_BEATSPERCYCLE-1: 0] sink_endofpacket; + logic [lindex(ST_MERROR_W): 0] sink_error; + logic [lindex(ST_MEMPTY_W): 0] sink_empty; + logic sink_ready; + + string message = "*uninitialized*"; + logic ready = 0; + int idle_ctr = 0; + int transaction_fifo_max = FIFO_MAX_LEVEL; + int transaction_fifo_threshold = FIFO_THRESHOLD; + + STBeats_t sink_valid_qualified; + logic sink_ready_qualified; + + localparam MAX_READY_DELAY = 8; + logic [MAX_READY_DELAY-1:0] sink_ready_delayed; + + //-------------------------------------------------------------------------- + // Private Functions + //-------------------------------------------------------------------------- + + function int __floor(int arg); + // returns the arg if it is greater than 0, else returns 0 + return (arg > 0) ? arg : 0; + endfunction + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // which instantiates and controls and queries state of this component. + // Test programs must only use these public access methods and events to + // communicate with this BFM component. The API and the module pins + // are the only interfaces in this component that are guaranteed to be + // stable. The API will be maintained for the life of the product. + // While we cannot prevent a test program from directly accessing internal + // tasks, functions, or data private to the BFM, there is no guarantee that + // these will be present in the future. In fact, it is best for the user + // to assume that the underlying implementation of this component can + // and will change. + //-------------------------------------------------------------------------- + event signal_fatal_error; // public + // Signal that a fatal error has occurred. Terminates simulation. + + event signal_transaction_received; //public + // Signal that a transaction has been received and queued. + + event signal_transaction_fifo_threshold; // public + // Signal that the transaction FIFO threshold level has been exceeded + + event signal_transaction_fifo_overflow; // public + // Signal that the FIFO is full and further transactions are being dropped + + function automatic string get_version(); // public + // Return component version as a string of three integers separated by periods. + // For example, version 9.1 sp1 is encoded as "9.1.1". + string ret_version = "17.1"; + return ret_version; + endfunction + + function automatic void set_transaction_fifo_max( // public + int level + ); + // Set the maximum fullness level of the FIFO. The event + // signal_transaction_fifo_max is triggered when this + // level is exceeded. + transaction_fifo_max = level; + endfunction + + function automatic int get_transaction_fifo_max(); + // Get the maximum transaction FIFO depth. + return transaction_fifo_max; + endfunction + + function automatic void set_transaction_fifo_threshold( // public + int level + ); + // Set the threshold alert level of the FIFO. The event + // signal_transaction_fifo_threshold is triggered when this + // level is exceeded. + transaction_fifo_threshold = level; + endfunction + + function automatic int get_transaction_fifo_threshold(); + // Get the transaction FIFO threshold level. + return transaction_fifo_threshold; + endfunction + + function automatic void pop_transaction(); // public + // Pop the transaction descriptor from the queue so that it can be + // queried with the get_transaction methods by the test bench. + if (reset) begin + $sformat(message, "%m: Illegal command while reset asserted"); + print(VERBOSITY_ERROR, message); + ->signal_fatal_error; + end + + query_transaction = transaction_queue.pop_back(); + + $sformat(message, "%m: called pop_transaction"); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: Data: %x", query_transaction.data); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: Channel: %0d", query_transaction.channel); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: SOP: %0d EOP: %0d", + query_transaction.startofpacket, + query_transaction.endofpacket); + print(VERBOSITY_DEBUG, message); + endfunction + + function automatic bit[31:0] get_transaction_idles(); // public + // Return the number of idle cycles in the transaction + $sformat(message, "%m: called get_transaction_idles"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.idles; + endfunction + + function automatic logic [ST_DATA_W-1:0] get_transaction_data(); // public + // Return the data in the transaction + $sformat(message, "%m: called get_transaction_data"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.data; + endfunction + + function automatic logic [ST_CHANNEL_W-1:0] get_transaction_channel(); // public + // Return the channel identifier in the transaction + $sformat(message, "%m: called get_transaction_channel"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.channel; + endfunction + + function automatic logic get_transaction_sop(); // public + // Return the start of packet status in the transaction + $sformat(message, "%m: called get_transaction_sop"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.startofpacket; + endfunction + + function automatic logic get_transaction_eop(); // public + // Return the end of packet status in the transaction + $sformat(message, "%m: called get_transaction_eop"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.endofpacket; + endfunction + + function automatic logic [ST_ERROR_W-1:0] get_transaction_error(); // public + // Return the error status in the transaction + $sformat(message, "%m: called get_transaction_error"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.error; + endfunction + + function automatic logic [ST_EMPTY_W-1:0] get_transaction_empty(); // public + // Return the number of empty symbols in the transaction + $sformat(message, "%m: called get_transaction_empty"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.empty; + endfunction + + function automatic int get_transaction_queue_size(); // public + // Return the length of the queue holding received transactions + $sformat(message, "%m: called get_transaction_queue_size"); + print(VERBOSITY_DEBUG, message); + + // Return the number of transactions in the internal queues. + return transaction_queue.size(); + endfunction + + // =cut + + //-------------------------------------------------------------------------- + // Local Machinery + //-------------------------------------------------------------------------- + always @(signal_fatal_error) abort_simulation(); + + always @(*) begin + { + sink_data, + sink_channel, + sink_valid, + sink_startofpacket, + sink_endofpacket, + sink_error, + sink_empty, + sink_ready + } <= tap; + end + + // delay chain for sink_ready back pressure output to account for latency + always @(posedge clk or posedge reset) begin + if (reset) begin + sink_ready_delayed <= 0; + end else begin + sink_ready_delayed <= {sink_ready_delayed[6:0], sink_ready}; + end + end + + always @(*) begin + if (USE_READY == 0) + sink_ready_qualified = 1'b1; + else begin + if (ST_READY_LATENCY == 0) + sink_ready_qualified = sink_ready; + else + sink_ready_qualified = sink_ready_delayed[__floor(ST_READY_LATENCY-1)]; + end + end + + always @(sink_valid) begin + if (USE_VALID > 0) + sink_valid_qualified = sink_valid; + else + sink_valid_qualified = '1; + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + for (int i=0; i 0; clog2 = clog2 + 1) + i = i >> 1; + + return clog2; + endfunction + + function automatic int max( + bit [31:0] one, + bit [31:0] two + ); + if(one > two) + return one; + else + return two; + endfunction + + function automatic int lindex( + bit [31:0] width + ); + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + lindex = (width > 0) ? (width-1) : 0; + endfunction + + typedef enum int { + LOW = 0, + HIGH = 1, + RANDOM = 2, + UNKNOWN = 3 + } IdleOutputValue_t; + +endpackage + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv (revision 49) @@ -0,0 +1,193 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// verbosity_pkg +// =head1 SYNOPSIS +// Package for controlling verbosity of messages sent to the console +//----------------------------------------------------------------------------- +// =head1 COPYRIGHT +// Copyright (c) 2008 Altera Corporation. All Rights Reserved. +// The information contained in this file is the property of Altera +// Corporation. Except as specifically authorized in writing by Altera +// Corporation, the holder of this file shall keep all information +// contained herein confidential and shall protect same in whole or in part +// from disclosure and dissemination to all third parties. Use of this +// program confirms your agreement with the terms of this license. +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module will dump diagnostic messages to the console during +// simulation. The level of verbosity can be controlled in the test +// bench by using the *set_verbosity* method in the imported package +// verbosity_pkg. For a given setting, message at that level and all +// lower levels are dumped. For example, setting VERBOSITY_DEBUG level +// causes all messages to be dumped, while VERBOSITY_FAILURE restricts +// only failure messages and those tagged as VERBOSITY_NONE to be +// dumped. +// The different levels are: +// =over 4 +// =item 1 VERBOSITY_NONE +// Messages tagged with this level are always dumped to the console. +// =item 2 VERBOSITY_FAILURE +// A fatal simulation error has occurred and the simulator will exit. +// =item 3 VERBOSITY_ERROR +// A non-fatal error has occured. An example is a data comparison mismatch. +// =item 4 VERBOSITY_WARNING +// Warn the user that a potential error has occurred. +// =item 5 VERBOSITY_INFO +// Informational message. +// =item 6 VERBOSITY_DEBUG +// Dump enough state to diagnose problem scenarios. +// =back + + +`ifndef _AVALON_VERBOSITY_PKG_ +`define _AVALON_VERBOSITY_PKG_ + +package verbosity_pkg; + + timeunit 1ps; + timeprecision 1ps; + + typedef enum int {VERBOSITY_NONE, + VERBOSITY_FAILURE, + VERBOSITY_ERROR, + VERBOSITY_WARNING, + VERBOSITY_INFO, + VERBOSITY_DEBUG} Verbosity_t; + + Verbosity_t verbosity = VERBOSITY_INFO; + string message = ""; + int dump_file; + int dump = 0; + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // or component which imports this package. + // =cut + //-------------------------------------------------------------------------- + + function automatic Verbosity_t get_verbosity(); // public + // Returns the global verbosity setting. + return verbosity; + endfunction + + function automatic void set_verbosity ( // public + Verbosity_t v + ); + // Sets the global verbosity setting. + + string verbosity_str; + verbosity = v; + + case(verbosity) + VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; + VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; + VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; + VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; + VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; + VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; + default: verbosity_str = "UNKNOWN"; + endcase + $sformat(message, "%m: Setting Verbosity level=%0d (%s)", + verbosity, verbosity_str); + print(VERBOSITY_NONE, message); + endfunction + + function automatic void print( // public + Verbosity_t level, + string message + ); + // Print a message to the console if the verbosity argument + // is less than or equal to the global verbosity setting. + string level_str; + + if (level <= verbosity) begin + case(level) + VERBOSITY_NONE: level_str = ""; + VERBOSITY_FAILURE: level_str = "FAILURE:"; + VERBOSITY_ERROR: level_str = "ERROR:"; + VERBOSITY_WARNING: level_str = "WARNING:"; + VERBOSITY_INFO: level_str = "INFO:"; + VERBOSITY_DEBUG: level_str = "DEBUG:"; + default: level_str = "UNKNOWN:"; + endcase + + $display("%t: %s %s",$time, level_str, message); + if (dump) begin + $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); + end + end + endfunction + + function automatic void print_divider( // public + Verbosity_t level + ); + // Prints a divider line to the console to make a block of related text + // easier to identify and read. + string message; + $sformat(message, + "------------------------------------------------------------"); + print(level, message); + endfunction + + function automatic void open_dump_file ( // public + string dump_file_name = "avalon_bfm_sim.log" + ); + // Opens a dump file which collects console messages. + + if (dump) begin + $sformat(message, "%m: Dump file already open - ignoring open."); + print(VERBOSITY_ERROR, message); + end else begin + dump_file = $fopen(dump_file_name, "w"); + $fdisplay(dump_file, "testing dump file"); + $sformat(message, "%m: Opening dump file: %s", dump_file_name); + print(VERBOSITY_INFO, message); + dump = 1; + end + endfunction + + function automatic void close_dump_file(); // public + // Close the console message dump file. + if (!dump) begin + $sformat(message, "%m: No open dump file - ignoring close."); + print(VERBOSITY_ERROR, message); + end else begin + dump = 0; + $fclose(dump_file); + $sformat(message, "%m: Closing dump file"); + print(VERBOSITY_INFO, message); + end + endfunction + + function automatic void abort_simulation(); + string message; + $sformat(message, "%m: Abort the simulation due to fatal error incident."); + print(VERBOSITY_FAILURE, message); + $stop; + endfunction + +endpackage + +// =cut + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_monitor.qsys =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_monitor.qsys (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_monitor.qsys (revision 49) @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv (revision 49) @@ -0,0 +1,463 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +// $Author: swbranch $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_sink_bfm +// =head1 SYNOPSIS +// Bus Functional Model (BFM) for a Avalon Streaming Sink +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This is a Bus Functional Model (BFM) for a Avalon Streaming Sink. +// The behavior of each clock cycle of the ST protocol on the interface +// is governed by a transaction. Received bus cycles are captured as +// transactions and pushed into a response queue. Clients query received +// transactions by popping them off the queue one by one and extract +// information using the public API methods provided. Back pressure to +// a driving source is also applied using the API method set_ready. +//----------------------------------------------------------------------------- + +`timescale 1ps / 1ps + +module altera_avalon_st_sink_bfm( + clk, + reset, + + sink_data, + sink_channel, + sink_valid, + sink_startofpacket, + sink_endofpacket, + sink_error, + sink_empty, + sink_ready + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // Data symbol width in bits + parameter ST_NUMSYMBOLS = 4; // Number of symbols per word + parameter ST_CHANNEL_W = 0; // Channel width in bits + parameter ST_ERROR_W = 0; // Error width in bits + parameter ST_EMPTY_W = 0; // Empty width in bits + + parameter ST_READY_LATENCY = 0; // Number of cycles latency after ready (0 or 1 only) + parameter ST_MAX_CHANNELS = 1; // Maximum number of channels + + parameter USE_PACKET = 0; // Use packet pins on interface + parameter USE_CHANNEL = 0; // Use channel pins on interface + parameter USE_ERROR = 0; // Use error pin on interface + parameter USE_READY = 1; // Use ready pin on interface + parameter USE_VALID = 1; // Use valid pin on interface + parameter USE_EMPTY = 0; // Use empty pin on interface + + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + parameter VHDL_ID = 0; // VHDL BFM ID number + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; + localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; + localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; + localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Streaming Source Interface + input [lindex(ST_MDATA_W): 0] sink_data; + input [lindex(ST_MCHANNEL_W): 0] sink_channel; + input [ST_BEATSPERCYCLE-1: 0] sink_valid; + input [ST_BEATSPERCYCLE-1: 0] sink_startofpacket; + input [ST_BEATSPERCYCLE-1: 0] sink_endofpacket; + input [lindex(ST_MERROR_W): 0] sink_error; + input [lindex(ST_MEMPTY_W): 0] sink_empty; + output sink_ready; + + // =cut + + function integer lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + +// synthesis translate_off + import verbosity_pkg::*; + + logic sink_ready; + + //-------------------------------------------------------------------------- + // Private Types and Variables + //-------------------------------------------------------------------------- + + typedef logic [lindex(ST_DATA_W) :0] STData_t; + typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; + typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; + typedef logic [lindex(ST_ERROR_W) :0] STError_t; + + typedef logic [lindex(ST_MDATA_W) :0] STMData_t; + typedef logic [lindex(ST_MCHANNEL_W) :0] STMChannel_t; + typedef logic [lindex(ST_MEMPTY_W) :0] STMEmpty_t; + typedef logic [lindex(ST_MERROR_W) :0] STMError_t; + typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; + + typedef struct packed + { + bit [31:0] idles; + logic startofpacket; + logic endofpacket; + STChannel_t channel; + STData_t data; + STError_t error; + STEmpty_t empty; + } Transaction_t; + + Transaction_t current_transaction[ST_BEATSPERCYCLE]; + Transaction_t query_transaction; + + Transaction_t transaction_queue[$]; + + string message = "*uninitialized*"; + logic ready = 0; + int idle_ctr = 0; + + STBeats_t sink_valid_qualified; + logic sink_ready_qualified; + + localparam MAX_READY_DELAY = 8; + logic [MAX_READY_DELAY-1:0] sink_ready_delayed; + + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // which instantiates and controls and queries state in this BFM component. + // Test programs must only use these public access methods and events to + // communicate with this BFM component. The API and the module pins + // are the only interfaces in this component that are guaranteed to be + // stable. The API will be maintained for the life of the product. + // While we cannot prevent a test program from directly accessing internal + // tasks, functions, or data private to the BFM, there is no guarantee that + // these will be present in the future. In fact, it is best for the user + // to assume that the underlying implementation of this component can + // and will change. + // =cut + //-------------------------------------------------------------------------- + + event signal_fatal_error; // public + // Signal that a fatal error has occurred. Terminates simulation. + + event signal_transaction_received; //public + // Signal that a transaction has been received and queued. + + event signal_sink_ready_assert; // public + // Signal that sink_ready is asserted thereby turning off back pressure. + + event signal_sink_ready_deassert; // public + // Signal that sink_ready is deasserted thereby turning on back pressure. + + function automatic string get_version(); // public + // Return BFM version string. For example, version 9.1 sp1 is "9.1sp1" + string ret_version = "__ACDS_VERSION_SHORT__"; + return ret_version; + endfunction + + task automatic init(); // public + // Drive interface to idle state. + $sformat(message, "%m: called init"); + print(VERBOSITY_DEBUG, message); + + drive_interface_idle(); + endtask + + task automatic set_ready( // public + bit state + ); + // Set the value of the interface ready signal. To assert back + // pressure, the state argument is set to 0 i.e. not ready. + // The parameter USE_READY must be set to 1 to enable this signal. + + if (USE_READY > 0) begin + $sformat(message, "%m: called set_ready"); + print(VERBOSITY_DEBUG, message); + + sink_ready <= state; + + if (state == 1'b1) + ->signal_sink_ready_assert; + else + ->signal_sink_ready_deassert; + end else begin + $sformat(message, "%m: Ignore set_ready() when USE_READY == 0"); + print(VERBOSITY_WARNING, message); + sink_ready <= 0; + end + endtask + + function automatic void pop_transaction(); // public + // Pop the transaction descriptor from the queue so that it can be + // queried with the get_transaction methods by the test bench. + if (reset) begin + $sformat(message, "%m: Illegal command while reset asserted"); + print(VERBOSITY_ERROR, message); + ->signal_fatal_error; + end + + query_transaction = transaction_queue.pop_back(); + + $sformat(message, "%m: called pop_transaction"); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: Data: %x", query_transaction.data); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: Channel: %0d", query_transaction.channel); + print(VERBOSITY_DEBUG, message); + $sformat(message, "%m: SOP: %0d EOP: %0d", + query_transaction.startofpacket, + query_transaction.endofpacket); + print(VERBOSITY_DEBUG, message); + endfunction + + function automatic bit[31:0] get_transaction_idles(); // public + // Return the number of idle cycles in the transaction + $sformat(message, "%m: called get_transaction_idles"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.idles; + endfunction + + function automatic logic [ST_DATA_W-1:0] get_transaction_data(); // public + // Return the data in the transaction + $sformat(message, "%m: called get_transaction_data"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.data; + endfunction + + function automatic logic [ST_CHANNEL_W-1:0] get_transaction_channel(); // public + // Return the channel identifier in the transaction + $sformat(message, "%m: called get_transaction_channel"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.channel; + endfunction + + function automatic logic get_transaction_sop(); // public + // Return the start of packet status in the transaction + $sformat(message, "%m: called get_transaction_sop"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.startofpacket; + endfunction + + function automatic logic get_transaction_eop(); // public + // Return the end of packet status in the transaction + $sformat(message, "%m: called get_transaction_eop"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.endofpacket; + endfunction + + function automatic logic [ST_ERROR_W-1:0] get_transaction_error(); // public + // Return the error status in the transaction + $sformat(message, "%m: called get_transaction_error"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.error; + endfunction + + function automatic logic [ST_EMPTY_W-1:0] get_transaction_empty(); // public + // Return the number of empty symbols in the transaction + $sformat(message, "%m: called get_transaction_empty"); + print(VERBOSITY_DEBUG, message); + + return query_transaction.empty; + endfunction + + function automatic int get_transaction_queue_size(); // public + // Return the length of the queue holding received transactions + $sformat(message, "%m: called get_transaction_queue_size"); + print(VERBOSITY_DEBUG, message); + + // Return the number of transactions in the internal queues. + return transaction_queue.size(); + endfunction + + // =cut + + //-------------------------------------------------------------------------- + // Private Methods + //-------------------------------------------------------------------------- + function int __floor( + int arg + ); + // returns the arg if it is greater than 0, else returns 0 + return (arg > 0) ? arg : 0; + endfunction + + task automatic drive_interface_idle(); + set_ready(0); + endtask + + function automatic void __hello(); + // Introduction Message to console + $sformat(message, "%m: - Hello from altera_avalon_st_sink_bfm."); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Revision: #1 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Date: 2017/07/30 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_SYMBOL_W = %0d", + ST_SYMBOL_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_NUMSYMBOLS = %0d", + ST_NUMSYMBOLS); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_CHANNEL_W = %0d", + ST_CHANNEL_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_ERROR_W = %0d", + ST_ERROR_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_EMPTY_W = %0d", + ST_EMPTY_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_READY_LATENCY = %0d", + ST_READY_LATENCY); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_MAX_CHANNELS = %0d", + ST_MAX_CHANNELS); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_BEATSPERCYCLE = %0d", + ST_BEATSPERCYCLE); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_PACKET = %0d", + USE_PACKET); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_CHANNEL = %0d", + USE_CHANNEL); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_ERROR = %0d", + USE_ERROR); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_READY = %0d", + USE_READY); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_VALID = %0d", + USE_VALID); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_EMPTY = %0d", + USE_EMPTY); + print(VERBOSITY_INFO, message); + print_divider(VERBOSITY_INFO); + endfunction + + //-------------------------------------------------------------------------- + initial begin + __hello(); + end + + //-------------------------------------------------------------------------- + // Local Machinery + //-------------------------------------------------------------------------- + always @(signal_fatal_error) abort_simulation(); + + // delay chain for sink_ready back pressure output to account for latency + always @(posedge clk or posedge reset) begin + if (reset) begin + sink_ready_delayed <= 0; + end else begin + sink_ready_delayed <= {sink_ready_delayed[6:0], sink_ready}; + end + end + + assign sink_ready_qualified = (USE_READY == 0)? 1'b1 : + (ST_READY_LATENCY == 0)? sink_ready : + sink_ready_delayed[__floor(ST_READY_LATENCY-1)]; + + assign sink_valid_qualified = (USE_VALID == 0)? 1'b1 : sink_valid; + + always @(posedge clk or posedge reset) begin + if (reset) begin + transaction_queue = {}; + query_transaction = 0; + for (int i=0; i 0; clog2 = clog2 + 1) + i = i >> 1; + + return clog2; + endfunction + + function automatic int max( + bit [31:0] one, + bit [31:0] two + ); + if(one > two) + return one; + else + return two; + endfunction + + function automatic int lindex( + bit [31:0] width + ); + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + lindex = (width > 0) ? (width-1) : 0; + endfunction + + typedef enum int { + LOW = 0, + HIGH = 1, + RANDOM = 2, + UNKNOWN = 3 + } IdleOutputValue_t; + +endpackage + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/verbosity_pkg.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/verbosity_pkg.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/verbosity_pkg.sv (revision 49) @@ -0,0 +1,193 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// verbosity_pkg +// =head1 SYNOPSIS +// Package for controlling verbosity of messages sent to the console +//----------------------------------------------------------------------------- +// =head1 COPYRIGHT +// Copyright (c) 2008 Altera Corporation. All Rights Reserved. +// The information contained in this file is the property of Altera +// Corporation. Except as specifically authorized in writing by Altera +// Corporation, the holder of this file shall keep all information +// contained herein confidential and shall protect same in whole or in part +// from disclosure and dissemination to all third parties. Use of this +// program confirms your agreement with the terms of this license. +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module will dump diagnostic messages to the console during +// simulation. The level of verbosity can be controlled in the test +// bench by using the *set_verbosity* method in the imported package +// verbosity_pkg. For a given setting, message at that level and all +// lower levels are dumped. For example, setting VERBOSITY_DEBUG level +// causes all messages to be dumped, while VERBOSITY_FAILURE restricts +// only failure messages and those tagged as VERBOSITY_NONE to be +// dumped. +// The different levels are: +// =over 4 +// =item 1 VERBOSITY_NONE +// Messages tagged with this level are always dumped to the console. +// =item 2 VERBOSITY_FAILURE +// A fatal simulation error has occurred and the simulator will exit. +// =item 3 VERBOSITY_ERROR +// A non-fatal error has occured. An example is a data comparison mismatch. +// =item 4 VERBOSITY_WARNING +// Warn the user that a potential error has occurred. +// =item 5 VERBOSITY_INFO +// Informational message. +// =item 6 VERBOSITY_DEBUG +// Dump enough state to diagnose problem scenarios. +// =back + + +`ifndef _AVALON_VERBOSITY_PKG_ +`define _AVALON_VERBOSITY_PKG_ + +package verbosity_pkg; + + timeunit 1ps; + timeprecision 1ps; + + typedef enum int {VERBOSITY_NONE, + VERBOSITY_FAILURE, + VERBOSITY_ERROR, + VERBOSITY_WARNING, + VERBOSITY_INFO, + VERBOSITY_DEBUG} Verbosity_t; + + Verbosity_t verbosity = VERBOSITY_INFO; + string message = ""; + int dump_file; + int dump = 0; + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // or component which imports this package. + // =cut + //-------------------------------------------------------------------------- + + function automatic Verbosity_t get_verbosity(); // public + // Returns the global verbosity setting. + return verbosity; + endfunction + + function automatic void set_verbosity ( // public + Verbosity_t v + ); + // Sets the global verbosity setting. + + string verbosity_str; + verbosity = v; + + case(verbosity) + VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; + VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; + VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; + VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; + VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; + VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; + default: verbosity_str = "UNKNOWN"; + endcase + $sformat(message, "%m: Setting Verbosity level=%0d (%s)", + verbosity, verbosity_str); + print(VERBOSITY_NONE, message); + endfunction + + function automatic void print( // public + Verbosity_t level, + string message + ); + // Print a message to the console if the verbosity argument + // is less than or equal to the global verbosity setting. + string level_str; + + if (level <= verbosity) begin + case(level) + VERBOSITY_NONE: level_str = ""; + VERBOSITY_FAILURE: level_str = "FAILURE:"; + VERBOSITY_ERROR: level_str = "ERROR:"; + VERBOSITY_WARNING: level_str = "WARNING:"; + VERBOSITY_INFO: level_str = "INFO:"; + VERBOSITY_DEBUG: level_str = "DEBUG:"; + default: level_str = "UNKNOWN:"; + endcase + + $display("%t: %s %s",$time, level_str, message); + if (dump) begin + $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); + end + end + endfunction + + function automatic void print_divider( // public + Verbosity_t level + ); + // Prints a divider line to the console to make a block of related text + // easier to identify and read. + string message; + $sformat(message, + "------------------------------------------------------------"); + print(level, message); + endfunction + + function automatic void open_dump_file ( // public + string dump_file_name = "avalon_bfm_sim.log" + ); + // Opens a dump file which collects console messages. + + if (dump) begin + $sformat(message, "%m: Dump file already open - ignoring open."); + print(VERBOSITY_ERROR, message); + end else begin + dump_file = $fopen(dump_file_name, "w"); + $fdisplay(dump_file, "testing dump file"); + $sformat(message, "%m: Opening dump file: %s", dump_file_name); + print(VERBOSITY_INFO, message); + dump = 1; + end + endfunction + + function automatic void close_dump_file(); // public + // Close the console message dump file. + if (!dump) begin + $sformat(message, "%m: No open dump file - ignoring close."); + print(VERBOSITY_ERROR, message); + end else begin + dump = 0; + $fclose(dump_file); + $sformat(message, "%m: Closing dump file"); + print(VERBOSITY_INFO, message); + end + endfunction + + function automatic void abort_simulation(); + string message; + $sformat(message, "%m: Abort the simulation due to fatal error incident."); + print(VERBOSITY_FAILURE, message); + $stop; + endfunction + +endpackage + +// =cut + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_sink.qsys =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_sink.qsys (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_sink.qsys (revision 49) @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv (revision 49) @@ -0,0 +1,908 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +// $Author: swbranch $ +//----------------------------------------------------------------------------- +// =head1 NAME +// altera_avalon_st_source_bfm +// =head1 SYNOPSIS +// Bus Functional Model (BFM) for a Avalon Streaming Source +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This is a Bus Functional Model (BFM) for a Avalon Streaming Source. +// The behavior of each clock cycle of the ST protocol on the interface +// is governed by a transaction. Transactions are constructed using the +// the public API methods provided and are then pushed into a dispatch +// queue, either one at a time or as entire sequences. Response transactions +// are popped out of a separate response queue and inform the client of +// statistics such as back pressure latency. +//----------------------------------------------------------------------------- +`timescale 1ps / 1ps + +module altera_avalon_st_source_bfm ( + clk, + reset, + + src_data, + src_channel, + src_valid, + src_startofpacket, + src_endofpacket, + src_error, + src_empty, + src_ready + ); + + // =head1 PARAMETERS + parameter ST_SYMBOL_W = 8; // Data symbol width in bits + parameter ST_NUMSYMBOLS = 4; // Number of symbols per word + parameter ST_CHANNEL_W = 0; // Channel width in bits + parameter ST_ERROR_W = 0; // Error width in bits + parameter ST_EMPTY_W = 0; // Empty width in bits + + parameter ST_READY_LATENCY = 0; // Number of cycles latency after ready + parameter ST_MAX_CHANNELS = 1; // Maximum number of channels + + parameter USE_PACKET = 0; // Use packet pins on interface + parameter USE_CHANNEL = 0; // Use channel pins on interface + parameter USE_ERROR = 0; // Use error pin on interface + parameter USE_READY = 1; // Use ready pin on interface + parameter USE_VALID = 1; // Use valid pin on interface + parameter USE_EMPTY = 0; // Use empty pin on interface + + parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle + parameter VHDL_ID = 0; // VHDL BFM ID number + + localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; + localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; + localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; + localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; + localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; + + // =head1 PINS + // =head2 Clock Interface + input clk; + input reset; + + // =head2 Avalon Streaming Source Interface + output [lindex(ST_MDATA_W): 0] src_data; + output [lindex(ST_MCHANNEL_W): 0] src_channel; + output [ST_BEATSPERCYCLE-1: 0] src_valid; + output [ST_BEATSPERCYCLE-1: 0] src_startofpacket; + output [ST_BEATSPERCYCLE-1: 0] src_endofpacket; + output [lindex(ST_MERROR_W): 0] src_error; + output [lindex(ST_MEMPTY_W): 0] src_empty; + input src_ready; + + // =cut + + function int lindex; + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + input [31:0] width; + lindex = (width > 0) ? (width-1) : 0; + endfunction + +// synthesis translate_off + import verbosity_pkg::*; + import avalon_utilities_pkg::*; + + typedef logic [lindex(ST_DATA_W) :0] STData_t; + typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; + typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; + typedef logic [lindex(ST_ERROR_W) :0] STError_t; + typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; + + logic [ST_BEATSPERCYCLE-1 :0] src_valid; + logic [lindex(ST_MDATA_W) :0] src_data; + logic [lindex(ST_MCHANNEL_W) :0] src_channel; + logic [lindex(ST_MERROR_W) :0] src_error; + logic [lindex(ST_MEMPTY_W) :0] src_empty; + logic [ST_BEATSPERCYCLE-1 :0] src_startofpacket; + logic [ST_BEATSPERCYCLE-1 :0] src_endofpacket; + + logic [ST_BEATSPERCYCLE-1 :0] src_valid_temp; + logic [lindex(ST_MDATA_W) :0] src_data_temp, src_data_slices; + logic [lindex(ST_MCHANNEL_W) :0] src_channel_temp, src_channel_slices; + logic [lindex(ST_MERROR_W) :0] src_error_temp, src_error_slices; + logic [lindex(ST_MEMPTY_W) :0] src_empty_temp, src_empty_slices; + logic [ST_BEATSPERCYCLE-1 :0] src_startofpacket_temp; + logic [ST_BEATSPERCYCLE-1 :0] src_endofpacket_temp; + + //-------------------------------------------------------------------------- + // Private Types and Variables + //-------------------------------------------------------------------------- + typedef struct packed + { + bit [31:0] idles; + logic startofpacket; + logic endofpacket; + STChannel_t channel; + STData_t data; + STError_t error; + STEmpty_t empty; + bit valid; + } Transaction_t; + + typedef struct packed + { + int latency; + int count; + } Response_t; + + Transaction_t new_transaction; + Transaction_t current_transaction[ST_BEATSPERCYCLE]; + Transaction_t transaction_queue[$]; + + Response_t current_response; + Response_t new_response; + Response_t response_queue[$]; + + int response_timeout = 100; + string message = ""; + + int idle_ctr = 0; + bit idle_state = 0; + int ready_latency_ctr = 0; + bit transaction_pending = 0; + int transaction_queue_size = 0; + int transaction_ctr = 0; + int max_transaction_queue_size = 256; + int min_transaction_queue_size = 2; + + bit start = 0; + bit complete = 0; + + logic src_ready_qualified; + logic src_is_now_ready; + logic load_transaction = 0; + STBeats_t src_valid_local; + + IdleOutputValue_t idle_output_config = UNKNOWN; + + localparam MAX_READY_DELAY = 8; + logic [MAX_READY_DELAY-1:0] src_ready_delayed; + + //-------------------------------------------------------------------------- + // Private Methods + //-------------------------------------------------------------------------- + function int __floor( + int arg + ); + // returns the arg if it is greater than 0, else returns 0 + return (arg > 0) ? arg : 0; + endfunction + + task __drive_temp_interface_idle(); + case (idle_output_config) + LOW: begin + src_valid_temp <= 0; + src_startofpacket_temp <= '0; + src_endofpacket_temp <= '0; + src_channel_temp <= '0; + src_data_temp <= '0; + src_error_temp <= '0; + src_empty_temp <= '0; + end + HIGH: begin + src_valid_temp <= 0; + src_startofpacket_temp <= '1; + src_endofpacket_temp <= '1; + src_channel_temp <= '1; + src_data_temp <= '1; + src_error_temp <= '1; + src_empty_temp <= '1; + end + RANDOM: begin + src_valid_temp <= 0; + src_startofpacket_temp <= $random; + src_endofpacket_temp <= $random; + src_channel_temp <= $random; + src_data_temp <= $random; + src_error_temp <= $random; + src_empty_temp <= $random; + end + UNKNOWN: begin + src_valid_temp <= 0; + src_startofpacket_temp <= 'x; + src_endofpacket_temp <= 'x; + src_channel_temp <= 'x; + src_data_temp <= 'x; + src_error_temp <= 'x; + src_empty_temp <= 'x; + end + default: begin + src_valid_temp <= 0; + src_startofpacket_temp <= 'x; + src_endofpacket_temp <= 'x; + src_channel_temp <= 'x; + src_data_temp <= 'x; + src_error_temp <= 'x; + src_empty_temp <= 'x; + end + endcase + endtask + + task __drive_interface_idle(); + case (idle_output_config) + LOW: begin + src_valid = '0; + src_startofpacket = '0; + src_endofpacket = '0; + src_data = '0; + src_channel = '0; + src_error = '0; + src_empty = '0; + end + HIGH: begin + src_valid = '0; + src_startofpacket = '1; + src_endofpacket = '1; + src_data = '1; + src_channel = '1; + src_error = '1; + src_empty = '1; + end + RANDOM: begin + src_valid = '0; + src_startofpacket = $random; + src_endofpacket = $random; + src_data = $random; + src_channel = $random; + src_error = $random; + src_empty = $random; + end + UNKNOWN: begin + src_valid = '0; + src_startofpacket = 'x; + src_endofpacket = 'x; + src_data = 'x; + src_channel = 'x; + src_error = 'x; + src_empty = 'x; + end + default: begin + src_valid = '0; + src_startofpacket = 'x; + src_endofpacket = 'x; + src_data = 'x; + src_channel = 'x; + src_error = 'x; + src_empty = 'x; + end + endcase + endtask + + function automatic void __hello(); + // Introduction Message to console + $sformat(message, "%m: - Hello from altera_avalon_st_source_bfm."); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Revision: #1 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Date: 2017/07/30 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_SYMBOL_W = %0d", + ST_SYMBOL_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_NUMSYMBOLS = %0d", + ST_NUMSYMBOLS); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_CHANNEL_W = %0d", + ST_CHANNEL_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_ERROR_W = %0d", + ST_ERROR_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_EMPTY_W = %0d", + ST_EMPTY_W); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_READY_LATENCY = %0d", + ST_READY_LATENCY); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_MAX_CHANNELS = %0d", + ST_MAX_CHANNELS); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ST_BEATSPERCYCLE = %0d", + ST_BEATSPERCYCLE); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_PACKET = %0d", + USE_PACKET); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_CHANNEL = %0d", + USE_CHANNEL); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_ERROR = %0d", + USE_ERROR); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_READY = %0d", + USE_READY); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_VALID = %0d", + USE_VALID); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - USE_EMPTY = %0d", + USE_EMPTY); + print(VERBOSITY_INFO, message); + print_divider(VERBOSITY_INFO); + endfunction + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // which instantiates and controls and queries state in this BFM component. + // Test programs must only use these public access methods and events to + // communicate with this BFM component. The API and the module pins + // are the only interfaces in this component that are guaranteed to be + // stable. The API will be maintained for the life of the product. + // While we cannot prevent a test program from directly accessing local + // tasks, functions, or data private to the BFM, there is no guarantee that + // these will be present in the future. In fact, it is best for the user + // to assume that the underlying implementation of this component can + // and will change. + // =cut + //-------------------------------------------------------------------------- + event signal_fatal_error; // public + // Signal that a fatal error has occurred. Terminates simulation. + + event signal_response_done; // public + // Signal + + event signal_src_ready; // public + // Signal the assertion of the src_ready port. + + event signal_src_not_ready; // public + // Signal the deassertion of the src_ready port implying sink backpressure + + event signal_src_transaction_complete; // public + // Signal that all pending transactions have completed + + event signal_src_transaction_almost_complete; // public + // Signal that BFM is driving the last pending transaction + + event signal_src_driving_transaction; // public + // Signal that the source is driving the transaction onto the bus + + event signal_max_transaction_queue_size; // public + // This event signals that the pending transaction queue size + // threshold has been exceeded + + event signal_min_transaction_queue_size; // public + // This event signals that the pending transaction queue size + // is below the minimum threshold + + function automatic string get_version(); // public + // Return BFM version string. For example, version 9.1 sp1 is "9.1sp1" + string ret_version = "17.1"; + return ret_version; + endfunction + + function automatic void set_idle_state_output_configuration( // public + // Set the configuration of output signal value during interface idle + IdleOutputValue_t output_config + ); + $sformat(message, "%m: method called"); + print(VERBOSITY_DEBUG, message); + + idle_output_config = output_config; + endfunction + + function automatic IdleOutputValue_t get_idle_state_output_configuration(); + // Get the configuration of output signal value during interface idle + $sformat(message, "%m: method called"); + print(VERBOSITY_DEBUG, message); + + return idle_output_config; + endfunction + + function automatic bit get_src_transaction_complete(); // public + // Return the transaction complete status + $sformat(message, "%m: called get_src_transaction_complete"); + print(VERBOSITY_DEBUG, message); + return complete; + endfunction + + function automatic logic get_src_ready(); // public + // Return the value of the src_ready port. + $sformat(message, "%m: called get_src_ready"); + print(VERBOSITY_DEBUG, message); + return src_ready; + endfunction + + function automatic void set_response_timeout( // public + int cycles = 100 + ); + // Set the number of cycles that may elapse during backpressure before + // the time out error is asserted. Disable the timeout by setting + // the cycles argument to zero. + response_timeout = cycles; + $sformat(message, "%m: called set_response_timeout"); + print(VERBOSITY_DEBUG, message); + + $sformat(message, "%m: Response timeout set to %0d cycles", response_timeout); + print(VERBOSITY_INFO, message); + endfunction + + task automatic init(); // public + // Drive interface to idle state. + $sformat(message, "%m: called init"); + print(VERBOSITY_DEBUG, message); + __drive_temp_interface_idle(); + endtask + + function automatic void push_transaction(); // public + // Push a new transaction into the local transaction queue. + // The BFM will drive the appropriate signals on the ST bus + // according to the transaction field values. + Transaction_t idle_transaction; + + $sformat(message, "%m: called push_transaction"); + print(VERBOSITY_DEBUG, message); + + if (reset) begin + $sformat(message, "%m: Illegal command while reset asserted"); + print(VERBOSITY_ERROR, message); + ->signal_fatal_error; + end + + // Idle cycles, defined as preceding the actual transaction are + // converted to an equal number of dummy transactions with the + // valid field set to 0. These are pushed into the queue before + // the actual transaction. + + if (USE_VALID == 1) begin + idle_transaction.idles = 0; + idle_transaction.valid = 1'b0; + for (int i=0; i 0) begin + $sformat(message, "%m: called set_transaction_idles - %h", + idle_cycles); + print(VERBOSITY_DEBUG, message); + new_transaction.idles = idle_cycles; + end else begin + $sformat(message, "%m: Ignored. Idles set to 0 when USE_VALID == 0"); + print(VERBOSITY_WARNING, message); + new_transaction.idles = 0; + end + endfunction + + function automatic void set_transaction_sop( // public + bit sop + ); + // Set the transaction start of packet value + $sformat(message, "%m: called set_transaction_sop - %b", sop); + print(VERBOSITY_DEBUG, message); + new_transaction.startofpacket = sop; + endfunction + + function automatic void set_transaction_eop( // public + bit eop + ); + // Set the transaction end of packet value + $sformat(message, "%m: called set_transaction_eop - %b", eop); + print(VERBOSITY_DEBUG, message); + new_transaction.endofpacket = eop; + endfunction + + function automatic void set_transaction_error( // public + bit [ST_ERROR_W-1:0] error + ); + // Set the transaction error value + $sformat(message, "%m: called set_transaction_error - %h", error); + print(VERBOSITY_DEBUG, message); + new_transaction.error = error; + endfunction + + function automatic void set_transaction_empty( // public + bit [ST_EMPTY_W-1:0] empty + ); + // Set the transaction empty value + $sformat(message, "%m: called set_transaction_empty - %h", empty); + print(VERBOSITY_DEBUG, message); + new_transaction.empty = empty; + endfunction + + function automatic void pop_response(); // public + // Pop the response transaction from the queue before querying contents + string message; + + $sformat(message, "%m: called pop_response - queue depth %0d", + response_queue.size()); + print(VERBOSITY_DEBUG, message); + + if (response_queue.size() == 0) begin + $sformat(message, "%m: Illegal command: response queue is empty"); + print(VERBOSITY_ERROR, message); + ->signal_fatal_error; + end + + current_response = response_queue.pop_front(); + endfunction + + function automatic int get_response_latency(); // public + // Return the response latency due to back pressure for a + // transaction. The value is in terms of clock cycles. + $sformat(message, "%m: called get_response_latency - %0d", + current_response.latency); + print(VERBOSITY_DEBUG, message); + return current_response.latency; + endfunction + + function automatic void set_max_transaction_queue_size( // public + int size + ); + // Set the pending transaction maximum queue size threshold. + // The public event signal_max_transaction_queue_size + // will fire when the threshold is exceeded. + max_transaction_queue_size = size; + endfunction + + function automatic void set_min_transaction_queue_size( // public + int size + ); + // Set the pending transaction minimum queue size threshold. + // The public event signal_min_transaction_queue_size + // will fire when the queue level is below this threshold. + min_transaction_queue_size = size; + endfunction + + //=cut + + initial begin + __hello(); + end + + always @(posedge clk) begin + if (transaction_queue.size() > max_transaction_queue_size) begin + ->signal_max_transaction_queue_size; + end else if (transaction_queue.size() < min_transaction_queue_size) begin + ->signal_min_transaction_queue_size; + end + end + + always @(signal_fatal_error) abort_simulation(); + + + // The ST_BEATSPERCYCLE parameter complicates the driving of transactions + // somewhat as not all beats in a given cycle need to be valid. + // The following scenarios are possible: + // Transactions with no idle cycles: + // 1 There are an integral multiple of ST_BEATSPERCYCLE transactions + // in the pending transaction queue: + // All transactions fit neatly into an integral number of cycles + // with all beats valid and no resulting bubbles. + // 2 There are a non integral multiple of ST_BEATSPERCYCLE transactions + // in the pending transaction queue: + // The final pending transaction(s) in the queue need to be driven + // out with unused beats being marked as invalid i.e. there are one + // or more bubbles (invalid beats) at the end of the transaction + // sequence. + // A transaction with idle cycles defined is decomposed into a sequence of + // transactions. First there is a sequence of non valid, empty transaction + // beats which define the idle cycles or bubbles. And finally, there is + // one valid transaction beat. + + // delay chain for src_ready back pressure input to account for latency + always @(posedge clk or posedge reset) begin + if (reset) begin + src_ready_delayed <= 0; + end else begin + src_ready_delayed <= {src_ready_delayed[6:0], src_ready}; + end + end + + assign src_ready_qualified = (USE_READY == 0)? 1'b1 : + (ST_READY_LATENCY == 0)? src_ready : + src_ready_delayed[__floor(ST_READY_LATENCY-1)]; + + assign src_is_now_ready = (USE_READY == 0)? 1'b1 : + (ST_READY_LATENCY <= 1)? src_ready : + src_ready_delayed[__floor(ST_READY_LATENCY-2)]; + + always @(*) begin + src_valid_local = src_valid_temp; + + if (USE_VALID > 0) begin + if (USE_READY == 0 || ST_READY_LATENCY == 0) begin + src_valid = src_valid_temp; + src_startofpacket = src_startofpacket_temp; + src_endofpacket = src_endofpacket_temp; + src_data = src_data_temp; + src_channel = src_channel_temp; + src_error = src_error_temp; + src_empty = src_empty_temp; + end else begin + if (src_ready_qualified) begin + src_valid = src_valid_temp; + src_startofpacket = src_startofpacket_temp; + src_endofpacket = src_endofpacket_temp; + src_data = src_data_temp; + src_channel = src_channel_temp; + src_error = src_error_temp; + src_empty = src_empty_temp; + end else begin + __drive_interface_idle(); + end + end + end else begin + src_valid = 0; + src_startofpacket = src_startofpacket_temp; + src_endofpacket = src_endofpacket_temp; + src_data = src_data_temp; + src_channel = src_channel_temp; + src_error = src_error_temp; + src_empty = src_empty_temp; + end + + end + + bit pending; + int response_transaction_ctr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + ready_latency_ctr <= 0; + complete <= 0; + response_transaction_ctr = 0; + new_response = 0; + current_response = 0; + response_queue = {}; + end else begin + if (src_ready_qualified && ((src_valid != 0) || (USE_VALID == 0))) begin + ready_latency_ctr <= 0; + + if (transaction_pending) begin + new_response.count = response_transaction_ctr++; + new_response.latency = ready_latency_ctr; + response_queue.push_back(new_response); + ->signal_response_done; + end + + end else begin + if (transaction_pending && ((src_valid != 0) || (USE_VALID == 0))) + ready_latency_ctr <= ready_latency_ctr + 1; + end + + if ((get_transaction_queue_size() == 0) && src_ready_qualified && + (USE_READY == 0 || src_valid != 0)) begin + complete <= 1; + ->signal_src_transaction_complete; + end else if (complete && + ((get_transaction_queue_size() > 0) || transaction_pending)) begin + complete <= 0; + end + + if ((response_timeout != 0) && (ready_latency_ctr > response_timeout)) begin + $sformat(message, "%m: Response Timeout"); + print(VERBOSITY_FAILURE, message); + ->signal_fatal_error; + end + + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + idle_ctr <= 0; + transaction_pending = 0; // keep blocking + + __drive_temp_interface_idle(); + + new_transaction = 0; + transaction_queue = {}; + for (int i=0; i 0 && src_ready_qualified == 1) begin + transaction_pending = 0; + end + + if (~transaction_pending && get_transaction_queue_size() > 0) begin + transaction_pending = 1; + load_transaction = 1; + + // initialize all beats to be invalid + for (int i=0; isignal_src_driving_transaction; + load_transaction = 0; + end else if (ST_READY_LATENCY > 0 && src_is_now_ready == 1) begin + ->signal_src_driving_transaction; + load_transaction = 0; + end + end + end + end + join_none + end else begin + idle_ctr = idle_ctr - 1; + end + end + + end + end + + always@(signal_src_driving_transaction) begin + if (get_transaction_queue_size() == 0) + -> signal_src_transaction_almost_complete; + end + + always @(posedge src_ready_qualified or negedge src_ready_qualified) begin + if (src_ready_qualified) + ->signal_src_ready; + else + ->signal_src_not_ready; + end +// synthesis translate_on + +endmodule + +// =head1 SEE ALSO +// avalon_st_sink_bfm +// =cut + + + + + + + + Index: qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv (revision 49) @@ -0,0 +1,80 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/avalon_utilities_pkg.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// avalon_utilities_pkg +// =head1 SYNOPSIS +// Package for shared types and functions +//----------------------------------------------------------------------------- +// =head1 COPYRIGHT +// Copyright (c) 2008 Altera Corporation. All Rights Reserved. +// The information contained in this file is the property of Altera +// Corporation. Except as specifically authorized in writing by Altera +// Corporation, the holder of this file shall keep all information +// contained herein confidential and shall protect same in whole or in part +// from disclosure and dissemination to all third parties. Use of this +// program confirms your agreement with the terms of this license. +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This package contains shared types and functions. +// =cut +`timescale 1ns / 1ns + +`ifndef _AVALON_UTILITIES_PKG_ +`define _AVALON_UTILITIES_PKG_ + +package avalon_utilities_pkg; + + function automatic int clog2( + bit [31:0] Depth + ); + int i= Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + + return clog2; + endfunction + + function automatic int max( + bit [31:0] one, + bit [31:0] two + ); + if(one > two) + return one; + else + return two; + endfunction + + function automatic int lindex( + bit [31:0] width + ); + // returns the left index for a vector having a declared width + // when width is 0, then the left index is set to 0 rather than -1 + lindex = (width > 0) ? (width-1) : 0; + endfunction + + typedef enum int { + LOW = 0, + HIGH = 1, + RANDOM = 2, + UNKNOWN = 3 + } IdleOutputValue_t; + +endpackage + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv (revision 49) @@ -0,0 +1,193 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/07/30 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// verbosity_pkg +// =head1 SYNOPSIS +// Package for controlling verbosity of messages sent to the console +//----------------------------------------------------------------------------- +// =head1 COPYRIGHT +// Copyright (c) 2008 Altera Corporation. All Rights Reserved. +// The information contained in this file is the property of Altera +// Corporation. Except as specifically authorized in writing by Altera +// Corporation, the holder of this file shall keep all information +// contained herein confidential and shall protect same in whole or in part +// from disclosure and dissemination to all third parties. Use of this +// program confirms your agreement with the terms of this license. +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module will dump diagnostic messages to the console during +// simulation. The level of verbosity can be controlled in the test +// bench by using the *set_verbosity* method in the imported package +// verbosity_pkg. For a given setting, message at that level and all +// lower levels are dumped. For example, setting VERBOSITY_DEBUG level +// causes all messages to be dumped, while VERBOSITY_FAILURE restricts +// only failure messages and those tagged as VERBOSITY_NONE to be +// dumped. +// The different levels are: +// =over 4 +// =item 1 VERBOSITY_NONE +// Messages tagged with this level are always dumped to the console. +// =item 2 VERBOSITY_FAILURE +// A fatal simulation error has occurred and the simulator will exit. +// =item 3 VERBOSITY_ERROR +// A non-fatal error has occured. An example is a data comparison mismatch. +// =item 4 VERBOSITY_WARNING +// Warn the user that a potential error has occurred. +// =item 5 VERBOSITY_INFO +// Informational message. +// =item 6 VERBOSITY_DEBUG +// Dump enough state to diagnose problem scenarios. +// =back + + +`ifndef _AVALON_VERBOSITY_PKG_ +`define _AVALON_VERBOSITY_PKG_ + +package verbosity_pkg; + + timeunit 1ps; + timeprecision 1ps; + + typedef enum int {VERBOSITY_NONE, + VERBOSITY_FAILURE, + VERBOSITY_ERROR, + VERBOSITY_WARNING, + VERBOSITY_INFO, + VERBOSITY_DEBUG} Verbosity_t; + + Verbosity_t verbosity = VERBOSITY_INFO; + string message = ""; + int dump_file; + int dump = 0; + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // or component which imports this package. + // =cut + //-------------------------------------------------------------------------- + + function automatic Verbosity_t get_verbosity(); // public + // Returns the global verbosity setting. + return verbosity; + endfunction + + function automatic void set_verbosity ( // public + Verbosity_t v + ); + // Sets the global verbosity setting. + + string verbosity_str; + verbosity = v; + + case(verbosity) + VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; + VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; + VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; + VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; + VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; + VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; + default: verbosity_str = "UNKNOWN"; + endcase + $sformat(message, "%m: Setting Verbosity level=%0d (%s)", + verbosity, verbosity_str); + print(VERBOSITY_NONE, message); + endfunction + + function automatic void print( // public + Verbosity_t level, + string message + ); + // Print a message to the console if the verbosity argument + // is less than or equal to the global verbosity setting. + string level_str; + + if (level <= verbosity) begin + case(level) + VERBOSITY_NONE: level_str = ""; + VERBOSITY_FAILURE: level_str = "FAILURE:"; + VERBOSITY_ERROR: level_str = "ERROR:"; + VERBOSITY_WARNING: level_str = "WARNING:"; + VERBOSITY_INFO: level_str = "INFO:"; + VERBOSITY_DEBUG: level_str = "DEBUG:"; + default: level_str = "UNKNOWN:"; + endcase + + $display("%t: %s %s",$time, level_str, message); + if (dump) begin + $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); + end + end + endfunction + + function automatic void print_divider( // public + Verbosity_t level + ); + // Prints a divider line to the console to make a block of related text + // easier to identify and read. + string message; + $sformat(message, + "------------------------------------------------------------"); + print(level, message); + endfunction + + function automatic void open_dump_file ( // public + string dump_file_name = "avalon_bfm_sim.log" + ); + // Opens a dump file which collects console messages. + + if (dump) begin + $sformat(message, "%m: Dump file already open - ignoring open."); + print(VERBOSITY_ERROR, message); + end else begin + dump_file = $fopen(dump_file_name, "w"); + $fdisplay(dump_file, "testing dump file"); + $sformat(message, "%m: Opening dump file: %s", dump_file_name); + print(VERBOSITY_INFO, message); + dump = 1; + end + endfunction + + function automatic void close_dump_file(); // public + // Close the console message dump file. + if (!dump) begin + $sformat(message, "%m: No open dump file - ignoring close."); + print(VERBOSITY_ERROR, message); + end else begin + dump = 0; + $fclose(dump_file); + $sformat(message, "%m: Closing dump file"); + print(VERBOSITY_INFO, message); + end + endfunction + + function automatic void abort_simulation(); + string message; + $sformat(message, "%m: Abort the simulation due to fatal error incident."); + print(VERBOSITY_FAILURE, message); + $stop; + endfunction + +endpackage + +// =cut + +`endif + Index: qaz_libs/trunk/avalon_lib/syn/ast_source.qsys =================================================================== --- qaz_libs/trunk/avalon_lib/syn/ast_source.qsys (nonexistent) +++ qaz_libs/trunk/avalon_lib/syn/ast_source.qsys (revision 49) @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: qaz_libs/trunk/camera_link/docs/CameraLink5.pdf =================================================================== --- qaz_libs/trunk/camera_link/docs/CameraLink5.pdf (nonexistent) +++ qaz_libs/trunk/camera_link/docs/CameraLink5.pdf (revision 49) @@ -0,0 +1,13633 @@ +%PDF-1.3 +% +1729 0 obj +<< +/Linearized 1 +/O 1735 +/H [ 3218 904 ] +/L 293444 +/E 27744 +/N 34 +/T 258744 +>> +endobj + xref +1729 119 +0000000016 00000 n +0000002755 00000 n +0000002940 00000 n +0000003083 00000 n +0000003116 00000 n +0000003175 00000 n +0000004122 00000 n +0000004457 00000 n +0000004527 00000 n +0000004737 00000 n +0000004838 00000 n +0000004971 00000 n +0000005108 00000 n +0000005251 00000 n +0000005307 00000 n +0000005457 00000 n +0000005592 00000 n +0000005725 00000 n +0000005781 00000 n +0000005929 00000 n +0000006087 00000 n +0000006259 00000 n +0000006389 00000 n +0000006472 00000 n +0000006652 00000 n +0000006782 00000 n +0000006891 00000 n +0000007003 00000 n +0000007130 00000 n +0000007303 00000 n +0000007487 00000 n +0000007575 00000 n +0000007743 00000 n +0000007841 00000 n +0000007934 00000 n +0000008050 00000 n +0000008175 00000 n +0000008275 00000 n +0000008425 00000 n +0000008543 00000 n +0000008658 00000 n +0000008713 00000 n +0000008768 00000 n +0000008884 00000 n +0000008999 00000 n +0000009114 00000 n +0000009245 00000 n +0000009417 00000 n +0000009586 00000 n +0000009728 00000 n +0000009874 00000 n +0000010016 00000 n +0000010170 00000 n +0000010324 00000 n +0000010479 00000 n +0000010634 00000 n +0000010787 00000 n +0000010917 00000 n +0000010973 00000 n +0000011074 00000 n +0000011175 00000 n +0000011275 00000 n +0000011375 00000 n +0000011475 00000 n +0000011576 00000 n +0000011676 00000 n +0000011776 00000 n +0000011876 00000 n +0000011976 00000 n +0000012076 00000 n +0000012177 00000 n +0000012277 00000 n +0000012377 00000 n +0000012477 00000 n +0000012577 00000 n +0000012677 00000 n +0000012777 00000 n +0000012877 00000 n +0000012978 00000 n +0000013078 00000 n +0000013179 00000 n +0000013279 00000 n +0000013379 00000 n +0000013479 00000 n +0000013580 00000 n +0000013680 00000 n +0000013780 00000 n +0000013881 00000 n +0000013981 00000 n +0000014080 00000 n +0000014179 00000 n +0000014279 00000 n +0000014378 00000 n +0000014477 00000 n +0000014577 00000 n +0000014676 00000 n +0000014775 00000 n +0000014874 00000 n +0000014974 00000 n +0000015073 00000 n +0000015172 00000 n +0000015271 00000 n +0000015369 00000 n +0000015467 00000 n +0000015568 00000 n +0000015750 00000 n +0000016265 00000 n +0000016288 00000 n +0000016595 00000 n +0000016987 00000 n +0000017468 00000 n +0000017864 00000 n +0000018242 00000 n +0000018691 00000 n +0000020267 00000 n +0000024238 00000 n +0000027472 00000 n +0000003218 00000 n +0000004099 00000 n +trailer +<< +/Size 1848 +/Info 1722 0 R +/Encrypt 1731 0 R +/Root 1730 0 R +/Prev 258732 +/ID[] +>> +startxref +0 +%%EOF + +1730 0 obj +<< +/Type /Catalog +/Pages 1724 0 R +/Outlines 1736 0 R +/Threads 1732 0 R +/Names 1734 0 R +/OpenAction [ 1735 0 R /XYZ null null null ] +/PageMode /UseOutlines +>> +endobj +1731 0 obj +<< +/Filter /Standard +/V 1 +/R 2 +/O ( 4os*! j7XF4) +/U (*\n^_ ps+++?\(Ɲ KX) +/P -12 +>> +endobj +1732 0 obj +[ +1733 0 R +] +endobj +1733 0 obj +<< +/I << /Title ()>> +/F 1831 0 R +>> +endobj +1734 0 obj +<< +/Dests 1720 0 R +>> +endobj +1846 0 obj +<< /S 1026 /O 1265 /E 1281 /Filter /FlateDecode /Length 1847 0 R >> +stream +IgB'K 9DgfoYEkhX'H1T缱v8o0V0{#赵)Qt(~NQ +|3EP %K7Q +51oDadR 3OS ŢvîDi +l߬6͌3v GTxkySHXJ\[VXFt^1"Yp+ ~TsP+d O[|d#g$Iã]wTIElib +j_Wg fɰ^ +g𤅺6:]=;ZN}tri}@.j 7?.:q4XT"K 2I̘M, hnDÊގx0+ym4>Ģ#98P.) +br"J:wS@>$ ~T Q@3y 3'{WDbv d=4'D菫 ^&Tױ>DO.>s ۏ8h&6]5)!7Dzƿ}qlYsݦ2=aFdOsq'sP祼|# x8k.+r˚ndy}zf!k*Xy'dr4bd?u> /ColorSpace << /CS1 1833 0 R >> +/ExtGState << /R12 1845 0 R >> /ProcSet [ /PDF /Text ] >> +/Contents 1834 0 R +/CropBox [ 54 72 558 720 ] +/B [ 1787 0 R 1788 0 R 1832 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +1736 0 obj +<< +/Count 15 +/First 1737 0 R +/Last 1737 0 R +>> +endobj +1737 0 obj +<< +/Title (%py8w.cai֐\r|` лyw#%F0F{VR\)={6\ +7$yL&\(pj?) +/Dest (In-) +/Parent 1736 0 R +/First 1738 0 R +/Last 1739 0 R +/Count 14 +>> +endobj +1738 0 obj +<< +/Title (-f`iq\nM@w) +/A 1786 0 R +/Next 1768 0 R +/Parent 1737 0 R +>> +endobj +1739 0 obj +<< +/Title () +/Count -9 +/Last 1740 0 R +/First 1741 0 R +/A 1742 0 R +/Prev 1743 0 R +/Parent 1737 0 R +>> +endobj +1740 0 obj +<< +/Title («šr!esw G>Z3BpN0\nfd tRQRYӚ) +/Dest (閏f) +/Prev 1785 0 R +/Parent 1739 0 R +>> +endobj +1741 0 obj +<< +/Title (j.s\rKi|AY4m+̏R\(~9qa/l) +/Dest (583) +/Parent 1739 0 R +/Next 1779 0 R +>> +endobj +1742 0 obj +<< +/S /GoTo +/D [ 46 0 R /Fit ] +>> +endobj +1743 0 obj +<< +/Title (p18eL) +/Count -6 +/Last 1744 0 R +/First 1745 0 R +/A 1746 0 R +/Next 1739 0 R +/Prev 1747 0 R +/Parent 1737 0 R +>> +endobj +1744 0 obj +<< +/Title (C$VNH̋z#^K/.0) +/Dest (B^LGsu) +/Prev 1778 0 R +/Parent 1743 0 R +>> +endobj +1745 0 obj +<< +/Title (d,:4\\Q^RB\\{ˢPIK") +/Dest (eq|fH) +/Count 0 +/Parent 1743 0 R +/Next 1775 0 R +>> +endobj +1746 0 obj +<< +/S /GoTo +/D [ 46 0 R /Fit ] +>> +endobj +1747 0 obj +<< +/Title (\r${VSJf\nVК%o7w3W 0) +/Dest ( eURPj) +/Parent 1737 0 R +/Prev 1748 0 R +/Next 1743 0 R +>> +endobj +1748 0 obj +<< +/Title (^೮vitAY'%=RP'\)Յ.Xc]R7GJ) +/Dest (XXI) +/Parent 1737 0 R +/Prev 1749 0 R +/Next 1747 0 R +>> +endobj +1749 0 obj +<< +/Title (>"*h) +/Dest (e) +/Parent 1737 0 R +/Prev 1750 0 R +/Next 1748 0 R +/First 1751 0 R +/Last 1751 0 R +/Count -1 +>> +endobj +1750 0 obj +<< +/Title (R5sB> +endobj +1751 0 obj +<< +/Title (?hC@&) +/Dest (0> +endobj +1752 0 obj +<< +/Title (T|@5@TQ:! ڛ4N[) +/Dest (L/) +/Parent 1737 0 R +/Prev 1753 0 R +/Next 1750 0 R +/First 1754 0 R +/Last 1755 0 R +/Count -3 +>> +endobj +1753 0 obj +<< +/Title (\)aA/ʧį%_\n0) +/Dest (v.k) +/Parent 1737 0 R +/Prev 1757 0 R +/Next 1752 0 R +>> +endobj +1754 0 obj +<< +/Title (*4\n~ujzM) +/Dest (V'\n) +/Parent 1752 0 R +/Next 1756 0 R +>> +endobj +1755 0 obj +<< +/Title ( &2'$ln-~W) +/Dest (adq) +/Prev 1756 0 R +/Parent 1752 0 R +>> +endobj +1756 0 obj +<< +/Title (a=Oxn;Ȣ q) +/Dest (ۺ"jX) +/Next 1755 0 R +/Prev 1754 0 R +/Parent 1752 0 R +>> +endobj +1757 0 obj +<< +/Title ( rg/FFN2"we) +/Dest (U44k) +/Parent 1737 0 R +/Prev 1758 0 R +/Next 1753 0 R +/First 1759 0 R +/Last 1759 0 R +/Count -1 +>> +endobj +1758 0 obj +<< +/Title (=~l~S݀}cOS2Ry\n-< 4Q ) +/Dest (`1V*-) +/Parent 1737 0 R +/Prev 1760 0 R +/Next 1757 0 R +/First 1761 0 R +/Last 1762 0 R +/Count -4 +>> +endobj +1759 0 obj +<< +/Title ( J;`Ip{) +/Dest (7S\r\)2) +/Parent 1757 0 R +>> +endobj +1760 0 obj +<< +/Title (cϼ㎩Mbo) +/Dest (?V) +/Parent 1737 0 R +/Next 1758 0 R +/First 1765 0 R +/Last 1766 0 R +/Count -4 +/Prev 1767 0 R +>> +endobj +1761 0 obj +<< +/Title (\)?&>/sm) +/Dest (uupc9J) +/Parent 1758 0 R +/Next 1764 0 R +>> +endobj +1762 0 obj +<< +/Title (TW) +/Dest (\rJ) +/Parent 1758 0 R +/Prev 1763 0 R +>> +endobj +1763 0 obj +<< +/Title (†U[Pg) +/Dest ( _U) +/Parent 1758 0 R +/Prev 1764 0 R +/Next 1762 0 R +>> +endobj +1764 0 obj +<< +/Title (b$CᘎiO>D) +/Dest ("sT) +/Parent 1758 0 R +/Prev 1761 0 R +/Next 1763 0 R +>> +endobj +1765 0 obj +<< +/Title (a|Ǜ') +/Dest (q\\ !) +/Next 1774 0 R +/Parent 1760 0 R +>> +endobj +1766 0 obj +<< +/Title ({.ʇY c}4) +/Dest (hc) +/Count -2 +/First 1771 0 R +/Last 1772 0 R +/Prev 1773 0 R +/Parent 1760 0 R +>> +endobj +1767 0 obj +<< +/Title ($/N8VI|) +/Next 1760 0 R +/Prev 1768 0 R +/Parent 1737 0 R +/A 1769 0 R +>> +endobj +1768 0 obj +<< +/Title (0Cw]/Z%p) +/A 1770 0 R +/Next 1767 0 R +/Prev 1738 0 R +/Parent 1737 0 R +>> +endobj +1769 0 obj +<< +/S /GoTo +/D [ 6 0 R /Fit ] +>> +endobj +1770 0 obj +<< +/S /GoTo +/D [ 1 0 R /Fit ] +>> +endobj +1771 0 obj +<< +/Title (y׶z> +endobj +1772 0 obj +<< +/Title ( wm WrWc톬?>y) +/Dest (>6S) +/Parent 1766 0 R +/Prev 1771 0 R +>> +endobj +1773 0 obj +<< +/Title (!sqRc6#) +/Dest (%/],;) +/Next 1766 0 R +/Prev 1774 0 R +/Parent 1760 0 R +>> +endobj +1774 0 obj +<< +/Title (V\n/$6}&w) +/Dest (4a~\\[) +/Next 1773 0 R +/Prev 1765 0 R +/Parent 1760 0 R +>> +endobj +1775 0 obj +<< +/Title (se7"ط˓P\(\(?Ŏ>%d8/vɁ~>I7% \rnnIv) +/Dest (r:wpɽ) +/Next 1776 0 R +/Prev 1745 0 R +/Parent 1743 0 R +>> +endobj +1776 0 obj +<< +/Title (lpL鯚s8 C>G\n^0E ϵϺm?݁Iy.؀L) +/Dest (%]bJ) +/Next 1777 0 R +/Prev 1775 0 R +/Parent 1743 0 R +>> +endobj +1777 0 obj +<< +/Title (GYQRt?YH) +/Dest (FHFU) +/Count 0 +/Next 1778 0 R +/Prev 1776 0 R +/Parent 1743 0 R +>> +endobj +1778 0 obj +<< +/Title ( ?#R]*aLP.2m) +/Dest (TPʇ) +/Next 1744 0 R +/Prev 1777 0 R +/Parent 1743 0 R +>> +endobj +1779 0 obj +<< +/Title (R{͗?3\n Gjhwndd]13G) +/Dest (cʳ) +/Next 1780 0 R +/Prev 1741 0 R +/Parent 1739 0 R +>> +endobj +1780 0 obj +<< +/Title (%3h>\\ Pb3Mgr 6;2) +/Dest (67iJ") +/Count 0 +/Next 1781 0 R +/Prev 1779 0 R +/Parent 1739 0 R +>> +endobj +1781 0 obj +<< +/Title (?-|\\Y;$-sѲ:&pMz>BQSkصP) +/Dest (,u0/) +/Next 1782 0 R +/Prev 1780 0 R +/Parent 1739 0 R +>> +endobj +1782 0 obj +<< +/Title (C,Sk0tJpzGxP'zE1-Y \nűJ@) +/Dest (?'=) +/Next 1783 0 R +/Prev 1781 0 R +/Parent 1739 0 R +>> +endobj +1783 0 obj +<< +/Title (Aq_G?nm%uM{.KBkoP%;L s5sOb) +/Dest (Q%Ha:) +/Next 1784 0 R +/Prev 1782 0 R +/Parent 1739 0 R +>> +endobj +1784 0 obj +<< +/Title (Ώ4ۜ<3m~,RkQ'W<<ّ;@eg.> +endobj +1785 0 obj +<< +/Title (]Ef?7:\)OnjD) +/Dest (\\7) +/Next 1740 0 R +/Prev 1784 0 R +/Parent 1739 0 R +>> +endobj +1786 0 obj +<< +/S /GoTo +/D [ 10 0 R /Fit ] +>> +endobj +1787 0 obj +<< +/N 1788 0 R +/P 1735 0 R +/R [ 99 534 387 600 ] +/V 1789 0 R +/T 1733 0 R +>> +endobj +1788 0 obj +<< +/P 1735 0 R +/R [ 99 225 387 513 ] +/V 1787 0 R +/N 1832 0 R +/T 1733 0 R +>> +endobj +1789 0 obj +<< +/P 186 0 R +/R [ 99 122 522 670 ] +/V 1790 0 R +/N 1787 0 R +/T 1733 0 R +>> +endobj +1790 0 obj +<< +/P 182 0 R +/R [ 90 122 513 670 ] +/V 1791 0 R +/N 1789 0 R +/T 1733 0 R +>> +endobj +1791 0 obj +<< +/P 178 0 R +/R [ 99 122 522 642 ] +/V 1792 0 R +/N 1790 0 R +/T 1733 0 R +>> +endobj +1792 0 obj +<< +/P 178 0 R +/R [ 456 629 522 702 ] +/V 1793 0 R +/N 1791 0 R +/T 1733 0 R +>> +endobj +1793 0 obj +<< +/P 174 0 R +/R [ 99 122 522 670 ] +/V 1794 0 R +/N 1792 0 R +/T 1733 0 R +>> +endobj +1794 0 obj +<< +/P 170 0 R +/R [ 90 122 513 670 ] +/V 1795 0 R +/N 1793 0 R +/T 1733 0 R +>> +endobj +1795 0 obj +<< +/P 166 0 R +/R [ 99 122 522 670 ] +/V 1796 0 R +/N 1794 0 R +/T 1733 0 R +>> +endobj +1796 0 obj +<< +/P 162 0 R +/R [ 90 122 513 670 ] +/V 1797 0 R +/N 1795 0 R +/T 1733 0 R +>> +endobj +1797 0 obj +<< +/P 158 0 R +/R [ 99 122 522 642 ] +/V 1798 0 R +/N 1796 0 R +/T 1733 0 R +>> +endobj +1798 0 obj +<< +/P 158 0 R +/R [ 456 629 522 702 ] +/V 1799 0 R +/N 1797 0 R +/T 1733 0 R +>> +endobj +1799 0 obj +<< +/P 154 0 R +/R [ 99 122 522 670 ] +/V 1800 0 R +/N 1798 0 R +/T 1733 0 R +>> +endobj +1800 0 obj +<< +/P 150 0 R +/R [ 90 122 513 670 ] +/V 1801 0 R +/N 1799 0 R +/T 1733 0 R +>> +endobj +1801 0 obj +<< +/P 146 0 R +/R [ 99 122 522 670 ] +/V 1802 0 R +/N 1800 0 R +/T 1733 0 R +>> +endobj +1802 0 obj +<< +/P 142 0 R +/R [ 90 122 513 670 ] +/V 1803 0 R +/N 1801 0 R +/T 1733 0 R +>> +endobj +1803 0 obj +<< +/P 138 0 R +/R [ 99 122 522 670 ] +/V 1804 0 R +/N 1802 0 R +/T 1733 0 R +>> +endobj +1804 0 obj +<< +/P 134 0 R +/R [ 90 122 513 670 ] +/V 1805 0 R +/N 1803 0 R +/T 1733 0 R +>> +endobj +1805 0 obj +<< +/P 130 0 R +/R [ 99 122 522 642 ] +/V 1806 0 R +/N 1804 0 R +/T 1733 0 R +>> +endobj +1806 0 obj +<< +/P 130 0 R +/R [ 456 629 522 702 ] +/V 1807 0 R +/N 1805 0 R +/T 1733 0 R +>> +endobj +1807 0 obj +<< +/P 126 0 R +/R [ 99 122 522 642 ] +/V 1808 0 R +/N 1806 0 R +/T 1733 0 R +>> +endobj +1808 0 obj +<< +/P 126 0 R +/R [ 456 629 522 702 ] +/V 1809 0 R +/N 1807 0 R +/T 1733 0 R +>> +endobj +1809 0 obj +<< +/P 122 0 R +/R [ 99 122 522 670 ] +/V 1810 0 R +/N 1808 0 R +/T 1733 0 R +>> +endobj +1810 0 obj +<< +/P 118 0 R +/R [ 90 122 513 670 ] +/V 1811 0 R +/N 1809 0 R +/T 1733 0 R +>> +endobj +1811 0 obj +<< +/P 114 0 R +/R [ 99 122 522 642 ] +/V 1812 0 R +/N 1810 0 R +/T 1733 0 R +>> +endobj +1812 0 obj +<< +/P 114 0 R +/R [ 456 629 522 702 ] +/V 1813 0 R +/N 1811 0 R +/T 1733 0 R +>> +endobj +1813 0 obj +<< +/P 110 0 R +/R [ 90 122 513 670 ] +/V 1814 0 R +/N 1812 0 R +/T 1733 0 R +>> +endobj +1814 0 obj +<< +/P 106 0 R +/R [ 99 122 522 642 ] +/V 1815 0 R +/N 1813 0 R +/T 1733 0 R +>> +endobj +1815 0 obj +<< +/P 106 0 R +/R [ 456 629 522 702 ] +/V 1816 0 R +/N 1814 0 R +/T 1733 0 R +>> +endobj +1816 0 obj +<< +/P 102 0 R +/R [ 99 122 522 670 ] +/V 1817 0 R +/N 1815 0 R +/T 1733 0 R +>> +endobj +1817 0 obj +<< +/P 98 0 R +/R [ 90 122 513 670 ] +/V 1818 0 R +/N 1816 0 R +/T 1733 0 R +>> +endobj +1818 0 obj +<< +/P 94 0 R +/R [ 99 122 522 642 ] +/V 1819 0 R +/N 1817 0 R +/T 1733 0 R +>> +endobj +1819 0 obj +<< +/P 94 0 R +/R [ 456 629 522 702 ] +/V 1820 0 R +/N 1818 0 R +/T 1733 0 R +>> +endobj +1820 0 obj +<< +/P 90 0 R +/R [ 90 122 513 670 ] +/V 1821 0 R +/N 1819 0 R +/T 1733 0 R +>> +endobj +1821 0 obj +<< +/P 86 0 R +/R [ 99 122 522 642 ] +/V 1822 0 R +/N 1820 0 R +/T 1733 0 R +>> +endobj +1822 0 obj +<< +/P 86 0 R +/R [ 456 629 522 702 ] +/V 1823 0 R +/N 1821 0 R +/T 1733 0 R +>> +endobj +1823 0 obj +<< +/P 82 0 R +/R [ 99 122 522 670 ] +/V 1824 0 R +/N 1822 0 R +/T 1733 0 R +>> +endobj +1824 0 obj +<< +/P 78 0 R +/R [ 90 122 513 670 ] +/V 1825 0 R +/N 1823 0 R +/T 1733 0 R +>> +endobj +1825 0 obj +<< +/P 74 0 R +/R [ 99 122 522 642 ] +/V 1826 0 R +/N 1824 0 R +/T 1733 0 R +>> +endobj +1826 0 obj +<< +/P 74 0 R +/R [ 456 629 522 702 ] +/V 1827 0 R +/N 1825 0 R +/T 1733 0 R +>> +endobj +1827 0 obj +<< +/P 46 0 R +/R [ 90 122 513 670 ] +/V 1828 0 R +/N 1826 0 R +/T 1733 0 R +>> +endobj +1828 0 obj +<< +/P 10 0 R +/R [ 99 122 522 626 ] +/V 1829 0 R +/N 1827 0 R +/T 1733 0 R +>> +endobj +1829 0 obj +<< +/P 10 0 R +/R [ 99 648 522 685 ] +/V 1830 0 R +/N 1828 0 R +/T 1733 0 R +>> +endobj +1830 0 obj +<< +/P 6 0 R +/R [ 99 122 522 626 ] +/V 1831 0 R +/N 1829 0 R +/T 1733 0 R +>> +endobj +1831 0 obj +<< +/P 6 0 R +/R [ 99 648 522 685 ] +/V 1832 0 R +/N 1830 0 R +/T 1733 0 R +>> +endobj +1832 0 obj +<< +/P 1735 0 R +/R [ 405 99 522 137 ] +/V 1788 0 R +/N 1831 0 R +/T 1733 0 R +>> +endobj +1833 0 obj +[ +/CalRGB << /WhitePoint [ 0.9505 1 1.089 ] /Gamma [ 2.22221 2.22221 2.22221 ] +/Matrix [ 0.4124 0.2126 0.0193 0.3576 0.71519 0.1192 0.1805 0.0722 0.9505 ] >> + +] +endobj +1834 0 obj +<< /Filter /FlateDecode /Length 1835 0 R >> +stream +#Άi=^ ctˉ-,@fOe7a3ki5+e^{1[DkrQ{Kwo_ɛʰPQ)z GyE@Z&ZP'ElW l.gx5`> ~Z/-²)0vDXFyi=1 I?C7?JnB#%ԣw{[> +endobj +1837 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 114 +/Widths [ 315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 630 630 630 630 630 0 0 0 0 0 +0 0 0 0 0 0 742 668 667 761 0 0 0 0 0 0 0 556 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 592 0 0 0 572 0 0 0 320 0 629 0 990 664 0 +0 0 463 ] +/Encoding /WinAnsiEncoding +/BaseFont /GFGILM+StoneSans-Bold +/FontDescriptor 1836 0 R +>> +endobj +1838 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 121 +/Widths [ 250 0 0 0 0 0 0 0 0 0 0 0 0 333 333 0 0 500 500 500 500 500 500 0 +0 0 0 0 0 0 0 0 0 556 556 556 611 0 500 611 611 278 0 0 500 778 +611 611 556 0 611 556 500 0 556 833 0 0 0 0 0 0 0 0 0 500 500 444 +500 500 278 500 500 278 0 444 278 778 500 500 500 500 333 444 278 +500 0 667 444 444 ] +/Encoding /WinAnsiEncoding +/BaseFont /GFGIMD+Helvetica-Condensed-Bold +/FontDescriptor 1839 0 R +>> +endobj +1839 0 obj +<< +/Type /FontDescriptor +/Ascent 750 +/CapHeight 750 +/Descent -189 +/Flags 262176 +/FontBBox [ -169 -250 1091 991 ] +/FontName /GFGIMD+Helvetica-Condensed-Bold +/ItalicAngle 0 +/StemV 130 +/XHeight 564 +/CharSet (e\nuLI4L_+Y1X'\rP/j OӨmTt^B\ +/{\rtG #Dо&1kr aBFՄ xGC0d ) +/FontFile3 1843 0 R +>> +endobj +1840 0 obj +<< +/Type /FontDescriptor +/Ascent 750 +/CapHeight 750 +/Descent -189 +/Flags 32 +/FontBBox [ -174 -250 1071 990 ] +/FontName /GFGINE+Helvetica-Condensed +/ItalicAngle 0 +/StemV 79 +/XHeight 556 +/CharSet (,?1{vN"f f9`Fzi'&{Iw XjRrsP$JfX\\!Q+F\ +JJ{ゕ8YP7\rة6!b&9}cY-"t) +/FontFile3 1844 0 R +>> +endobj +1841 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 117 +/Widths [ 250 0 0 0 0 0 0 0 333 333 0 0 250 333 0 0 500 0 500 500 0 0 500 0 +0 0 0 0 0 0 0 0 0 556 556 556 611 0 444 0 0 278 0 0 500 778 611 +611 556 0 611 556 0 0 0 0 0 0 0 0 0 0 0 0 0 444 500 444 500 444 +278 500 500 222 0 444 222 778 500 500 500 0 333 444 278 500 ] +/Encoding /WinAnsiEncoding +/BaseFont /GFGINE+Helvetica-Condensed +/FontDescriptor 1840 0 R +>> +endobj +1842 0 obj +<< /Filter /FlateDecode /Length 1481 /Subtype /Type1C >> +stream +pOGGifyv!y9÷vB +jǓz/kt QNg)6XВ^}L0vٳ'tk3_J-n`A`i +EJTֵD6zNJIGۆ4po.2J+i`C*[ wcdBX̾v dfu>[([%ExmrCLÒUw7F+_wX_ +}6b&zDuICAk\⒟cʾ.٨ZK'_zto +'IkIv3n3ؠrNn\hv7&T36A+ [;^:cF,Bf N.M79h_φ8D8!'[D>w ?9L/͚Ο,侄ÝelIQhy//ZߞȦb.vEly5 +JhbJeZ ?vEF{s ҼIoG^G Fj( +.ֿf|4 VOeZa B[sY r=n%2ouA=Y̲gi \!d,||Ex:L,ia7D nc}ε[0RYuD{+ +zPdKmQepuN0lmɄ&!Es}9_G-.MapV! ӶkAq;!/j qWOvBm6`քkr|50'ӺT5J,0{7OG9ӧvm(DL+%'0Jy^,;:[PFґBhA03 +CNh;kD&w2\V91(XnzAT`A9nsw#1NKu0qNK|QSX6: CRA}@X^~߇7,F[}Jsn<0S}.h/m+'Ĭ$*tv$ePb\XAC/NºA7:-C,o?O &G3z?#5m*ÓW)c=VO Д+#lT#$Û4L{|X*5 맳{9,6sJtEyk55ķQFl&IiHf@6Ihw9ʗCt6EQI ,? RIHVtS\r3Q [Éoܯ}&X'.A[jRIH7ƶ?uß>헔舼~ 8 aW=B< =L +endstream +endobj +1843 0 obj +<< /Filter /FlateDecode /Length 3876 /Subtype /Type1C >> +stream +EDih 웠K-D.z2IrJ~h:=Unu^Un;{!P'V Hn.]Lvt8~Fcy +>ᓗ^rDؗO_'i;MY"#]p|xΠ_9xD:eΗ%-w13> +g[.1eKġ 4В.2[Wu(:|)D]ϫbcRˡ"/,F;.ŕ_6EvTK ,n.="Jxʳ,R'[4xF+%ŽU\R'AÏ@mܳ*(&[yBZ4Ms ,1KL* <^ +ط-sG1E3d) ^5w#l5rd 5>Lzb$c<b%Mx:2ǐ/WD.@auiD !(TZ ܻ2b_ j%E5!)y0Y-]ΝTLAη-j7NBt'`mfКXs6$;a)`5 ;&d8qWRVȝ1;]XPn9?Or?TD/D+|ϯplش2Cdb#c_>}OK8fW-R;t Y&xSGkQX%!1u9fnIU=`I-MկsU4i-s,bC?aaLٵ1R5\'xGہ.Kr +bhXWFf.M(Y}/N@)MQWøIՔMm~N,m +RzkaJdz{xY$Y[շ.>ݗ?wSh׍:BCeshF@9OŁO૎}Ι%Y% p d'=T2PaRX-x&?3ou- +_zkI~Lo ,uh"a4?K=WlyO +he0זF-hDv;;NlSť`?2z T G/zi z͍h A4ﯩFoĝ7 }AeeQ8a4Q[- Хui5 +0NjU0%XٕI k¾>ME2HIt6ȗ9X]@/Km T7pgJ/z[09ߣuE>Ql$ٜ -#rqM 6$@)lBJ"uW9y-;Bk0| zux`}M[ +}rf7}00RƔ!Yo`l$hǁ[{ +A܁HOf@, ~pIu^k}B`xj3?S, U[=87^5$VuAD,(`_%q}-d&>Drt&':8cSYKjy!GIt*C,4BN]x~D?vըj0Er  @ 08`&8eezg$e= [{:,#^eu},? Vl\>C]Z!? ~~EwsfߤWajL'f:2],ʥɖ{DoL'uͬ= t3hXyN"OGFɟGTz[;xuهys5!Jh(X7_PB(+ ˰[\jjTGО{hG!]NH-Pe'nl\oڞdy4?g: +M*6f*,)YrWԕu!ëZhƼϦ$%a3:@kx,uFSݷsQ|1YkGՁ7e'`)*h9{Gĺ ԝىr +h 6 9sg JCN*4KdrjМUfr1ɕnytoQeod_ H'*ۉc1J̀DT`.l+ IaD +Nz?4@)h$eT-YvhM$`4+$jw +%!TOmhVΪrJ-YP>4LLP?6UmL~}^{(3~Ǧ !!p +V~AkzJŸi?;2ÊB_C4 o _+ItR}ls&.ONRkfHtj+']OF1i1Mӈ$eO. ^) 'WP2#,h%[KN!/Iv8ɕ ib hx7CgΥX*E~nM? NR<AιxSHjѓ),nil9KV%X[̿Z)imWi+LS8EYįY4኿r)Rn#/%n) +쀶 5aY+=rr'm7V/5a suZ8Hpnh((MDkxI Y܌LTRNSwgftZJk +œ.jÛv"hwK!$+=2抜wQN@:+BDrDX{F&巇OJ"{mX`l!Nr!0|2V8+= 2+ `u%F zҸ_PAKylPdԼ%wA#V>8Cބ{ȤtVm%7DLw <mCWsgwWm*%r}lo Ȳ`?2$ߘ!ꃒ"4%Rg5A򑙠6Jl>'(; ?_|ʖ76U9c7h_MERFnhY!#[DLlDD iK\kUaYk,hn*S@~UV.aϴ;ͦOi?'Af|:Wq{~ه$&D8qbim`Y0{~' +уtD3u#^ѿeg* +QP'Eh4/6𗪅!G:3Xh4@5EK5pBI~jzN>i?LTLc3OSǡI}NkF^MOfG3{XɄa22O +PguiLgʂjc/vX"}^ CסgSLy/"[h +endstream +endobj +1844 0 obj +<< /Filter /FlateDecode /Length 3139 /Subtype /Type1C >> +stream + |P1O4.u/)=d}E٠NEf*609#F~c +mشte5nx1G`c֕ͭ'0惢F`#*85Lv>3-!T|~#rR}e R8Y`V-Sށ,M61تI&;SܐkF_"jDfWc X2 `[#}3!(I_eVr襏8EJqov-ʁwԭ,px m/e.C%3P[Z`d[PauF%UNϺE.k)i|SR@M +#ew>doە@,d\] b?YٶՉ:䗑RK'DY]@aq3d4Ω^۶e b;2HQuW +sinx9'r +A33"{lR >i*ڦ? qA&qZ'V"B^gPA(t-u>/vH(l(6qʯ C-XouS|h8{N&\ @˸*DgyȰ +|^XYyc5B$KcVr5f(3۟gid04裐sbwo*亞F%@E"!>`m21: +;)Pwr Hϱg;hzf[.[$xQԊMe&4KN>[wJ[zZ5!@ej'\*}l>.i<56J$[FٶXE+-m:2MrSE)y[+ұc 9pWl &''9s5ŪB"AAJw0ϵ.zډ8v`\5ZW=D.Z +=|p+[)fWgIJ꾢>/99 /f1{Hy</ZF<ccU+2?+u۬%:] {qdd x}GΎvRgβԺ ۺ#n`aAO233q~Z +VPd%=boo=lG9]-%1ڷy1_v'޺Gscz)fPTM|V٢e;'Q©3se:S9ChgU_, T&'ݢ]f[V:T 'U}6e\= t` Lh^ }mf>yS~;ŽcO‰Ҕ#B!(A opg)B"#=X^C:F'daK̲ .@{S8dZ2ҤCr9>ĐӆsGCImnOI(*VH*,PFzp_Y#4h+7`X"NQi{ۛE@~ez?d-Vf(F\T+W +o/"(o6\8p'D˗4OeUv +k/h}0% +DqSe;TQwƷn5D*:cOZ* A!w=)Hr(k%ݖ*Q6+Rn Lͦ׾t@UPٖaZZ?"2t:]R-!ըaqƠ0iӨ;Ƙ&ϠY37;9UʹW_`[~#O4Ff|d1M +HdNJ Y~*ٺحޑ+%(NƓu]ox-yX,#2"Jȶ$̍ _ɂP[W{m@RnV[N.$siǠϢ|YR7[+]s )!c<O &Hjƕg*)n3HI\M?q?ԝY)Mg;y5v\WTx\ N~|%@˲S`,~?VJn^zS>Cm}XYJ{`:juL + + +u:-TvRZ?*q.lYkQQs| +endstream +endobj +1845 0 obj +<< +/Type /ExtGState +/SA false +/SM 0.02 +/TR /Identity +>> +endobj +1 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 3 0 R +/Contents 4 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 2 0 R ] +/B [ null null ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +2 0 obj +<< +/Dest ( ^) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +3 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 208 0 R /F5 205 0 R /F6 190 0 R >> +/ExtGState << /GS1 5 0 R >> +/ColorSpace << /Cs5 204 0 R >> +>> +endobj +4 0 obj +<< /Length 1624 /Filter /FlateDecode >> +stream +Fw{mӁ|0р$y)‹h =C=,i>Z1|+tA~ +>@pYcq)F\YGA8(a V;wbB'-O)WE +L5%5o3o׿cfWU2ahNM0OAm4Ĭ5Fi!njwE.%5Xj h e[`~S6*[jw0eӀOMV! {HS/oF Wބz3NR<LIy*XDe V' N{BQ %u>M=w;~``JRl#$ۨPKbG_whMQ`Q.q'^1;KN( O)w'qWwpqQߝG{d-ș5]$o> +endobj +6 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 8 0 R +/Contents 9 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 7 0 R ] +/B [ 1831 0 R 1830 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +7 0 obj +<< +/Dest (^:5\nZTuݼbp1Q2liwnHH\rs~&z Nmt) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +8 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +9 0 obj +<< /Length 661 /Filter /FlateDecode >> +stream +\ji_lA!VҼ]9"֩ƑF#&E +V}]& +BF$ݮo60o{$<&.O:&111C~vWt$LQWI̧O1 ݓ?HF?ڟ7(!mi˅wsݼHWQp cYݏpwTFS=4)4 ֥̀fȦ]/?R~{PL|BZ">;4eӥ=3Y5Z.HRG6&o 헧z884#ᓋ@^\Tsu D' f!4a;j`b"ccn  `Ea{_cSM5 +ktkg%6\JQjȟ/NyʄKtF!2>i9{ZB!en-MnNhnVSR՗[ \| +1y8|d/'J2Ly4郘G%,<=ęPZ),;nTTÍ-R!DN#UEvcc +endstream +endobj +10 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 41 0 R +/Contents 42 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 11 0 R 12 0 R 13 0 R 14 0 R 15 0 R 16 0 R 17 0 R 18 0 R 19 0 R 20 0 R +21 0 R 22 0 R 23 0 R 24 0 R 25 0 R 26 0 R 27 0 R 28 0 R 29 0 R 30 0 R +31 0 R 32 0 R 33 0 R 34 0 R 35 0 R 36 0 R 37 0 R 38 0 R 39 0 R 40 0 R +] +/B [ 1829 0 R 1828 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +11 0 obj +<< +/A 43 0 R +/Type /Annot +/Subtype /Link +/Rect [ 108 604 513 622 ] +/Border [ 0 0 0 ] +/H /I +>> +endobj +12 0 obj +<< +/A 44 0 R +/Type /Annot +/Subtype /Link +/Rect [ 108 591 513 602 ] +/Border [ 0 0 0 ] +/H /I +>> +endobj +13 0 obj +<< +/A 45 0 R +/Type /Annot +/Subtype /Link +/Rect [ 108 579 513 590 ] +/Border [ 0 0 0 ] +/H /I +>> +endobj +14 0 obj +<< +/Dest (U!jb) +/Type /Annot +/Subtype /Link +/Rect [ 108 551 513 569 ] +/Border [ 0 0 0 ] +>> +endobj +15 0 obj +<< +/Dest (:') +/Type /Annot +/Subtype /Link +/Rect [ 108 522 513 540 ] +/Border [ 0 0 0 ] +>> +endobj +16 0 obj +<< +/Dest (OJ) +/Type /Annot +/Subtype /Link +/Rect [ 108 505 513 523 ] +/Border [ 0 0 0 ] +>> +endobj +17 0 obj +<< +/Dest (=Z5) +/Type /Annot +/Subtype /Link +/Rect [ 108 492 513 503 ] +/Border [ 0 0 0 ] +>> +endobj +18 0 obj +<< +/Dest (ET!=S) +/Type /Annot +/Subtype /Link +/Rect [ 108 480 513 491 ] +/Border [ 0 0 0 ] +>> +endobj +19 0 obj +<< +/Dest (\\斜) +/Type /Annot +/Subtype /Link +/Rect [ 108 468 513 479 ] +/Border [ 0 0 0 ] +>> +endobj +20 0 obj +<< +/Dest (,ic) +/Type /Annot +/Subtype /Link +/Rect [ 108 456 513 467 ] +/Border [ 0 0 0 ] +>> +endobj +21 0 obj +<< +/Dest (qoH1) +/Type /Annot +/Subtype /Link +/Rect [ 108 444 513 455 ] +/Border [ 0 0 0 ] +>> +endobj +22 0 obj +<< +/Dest (/VZl) +/Type /Annot +/Subtype /Link +/Rect [ 108 432 513 443 ] +/Border [ 0 0 0 ] +>> +endobj +23 0 obj +<< +/Dest (mK:A) +/Type /Annot +/Subtype /Link +/Rect [ 108 404 513 422 ] +/Border [ 0 0 0 ] +>> +endobj +24 0 obj +<< +/Dest (GPj>) +/Type /Annot +/Subtype /Link +/Rect [ 108 387 513 405 ] +/Border [ 0 0 0 ] +>> +endobj +25 0 obj +<< +/Dest ("O6) +/Type /Annot +/Subtype /Link +/Rect [ 108 374 513 385 ] +/Border [ 0 0 0 ] +>> +endobj +26 0 obj +<< +/Dest (,"a) +/Type /Annot +/Subtype /Link +/Rect [ 108 362 513 373 ] +/Border [ 0 0 0 ] +>> +endobj +27 0 obj +<< +/Dest (ت0U|) +/Type /Annot +/Subtype /Link +/Rect [ 108 350 513 361 ] +/Border [ 0 0 0 ] +>> +endobj +28 0 obj +<< +/Dest (f) +/Type /Annot +/Subtype /Link +/Rect [ 108 338 513 349 ] +/Border [ 0 0 0 ] +>> +endobj +29 0 obj +<< +/Dest (.Ś\(y) +/Type /Annot +/Subtype /Link +/Rect [ 108 310 513 327 ] +/Border [ 0 0 0 ] +>> +endobj +30 0 obj +<< +/Dest (##) +/Type /Annot +/Subtype /Link +/Rect [ 108 293 513 311 ] +/Border [ 0 0 0 ] +>> +endobj +31 0 obj +<< +/Dest (#0!m) +/Type /Annot +/Subtype /Link +/Rect [ 108 280 513 291 ] +/Border [ 0 0 0 ] +>> +endobj +32 0 obj +<< +/Dest (ܮ) +/Type /Annot +/Subtype /Link +/Rect [ 108 252 513 270 ] +/Border [ 0 0 0 ] +>> +endobj +33 0 obj +<< +/Dest (O\r) +/Type /Annot +/Subtype /Link +/Rect [ 108 235 513 252 ] +/Border [ 0 0 0 ] +>> +endobj +34 0 obj +<< +/Dest ($Mۭ`) +/Type /Annot +/Subtype /Link +/Rect [ 108 206 108 224 ] +/Border [ 0 0 0 ] +>> +endobj +35 0 obj +<< +/Dest (RR) +/Type /Annot +/Subtype /Link +/Rect [ 108 206 513 224 ] +/Border [ 0 0 0 ] +>> +endobj +36 0 obj +<< +/Dest (l{A) +/Type /Annot +/Subtype /Link +/Rect [ 108 189 513 207 ] +/Border [ 0 0 0 ] +>> +endobj +37 0 obj +<< +/Dest (t%2D) +/Type /Annot +/Subtype /Link +/Rect [ 108 176 513 187 ] +/Border [ 0 0 0 ] +>> +endobj +38 0 obj +<< +/Dest (AhR͛) +/Type /Annot +/Subtype /Link +/Rect [ 108 164 513 175 ] +/Border [ 0 0 0 ] +>> +endobj +39 0 obj +<< +/Dest (OtP[) +/Type /Annot +/Subtype /Link +/Rect [ 108 152 513 163 ] +/Border [ 0 0 0 ] +>> +endobj +40 0 obj +<< +/Dest (#εUIpžk`OoVOXiTWDEa6\)&5U릓\)>&t62;) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +41 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +42 0 obj +<< /Length 1200 /Filter /FlateDecode >> +stream +, Rp"!%2=tNQN['^AeG$㛁χ .kH|;|jHT@ FHb!-\9a%r<&/l3tc8%Q'ǤVkYj#01Ա)~3_iȇM9zHkw-5À^sg&ŧg_H$u;CrwU[ȲAI7/"KC9a3v` +b#̸ +y*~;3yX[4UZ;?YrVPLݐY[Z: f%pO;=bmDnPW@]"lAWPjZ)ASL[mQl7zGV{/ QRmBB2*j5q +1uc35)6s4b~&Jן`a0m/VNWjw +AuP%&܃ +jye55~@3 + T FvyA14]_ٳ?qv2IǠ`r@ +/[喳PהP^QN@;QC$n'& ˿-6 R^ML'(Wŋ\d!:04!.5qNDup\ +Dl"1?u? װ&~L-d[& +dpygo~PכAukz4O~Ou?IpNgur#,7yp2Kwf f?wU96&XASş~oU%v?[lгp5⛥f!/T\tБQoHpYkbv> +endobj +44 0 obj +<< +/S /GoTo +/D [ 1 0 R /Fit ] +>> +endobj +45 0 obj +<< +/S /GoTo +/D [ 1 0 R /Fit ] +>> +endobj +46 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 72 0 R +/Contents 73 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 47 0 R 48 0 R 49 0 R 50 0 R 51 0 R 52 0 R 53 0 R 54 0 R 55 0 R 56 0 R +57 0 R 58 0 R 59 0 R 60 0 R 61 0 R 62 0 R 63 0 R 64 0 R 65 0 R 66 0 R +67 0 R 68 0 R 69 0 R 70 0 R 71 0 R ] +/B [ 1827 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +47 0 obj +<< +/Dest (M?) +/Type /Annot +/Subtype /Link +/Rect [ 135 451 504 462 ] +/Border [ 0 0 0 ] +>> +endobj +48 0 obj +<< +/Dest (|za5FP) +/Type /Annot +/Subtype /Link +/Rect [ 99 427 504 438 ] +/Border [ 0 0 0 ] +>> +endobj +49 0 obj +<< +/Dest (L) +/Type /Annot +/Subtype /Link +/Rect [ 99 415 504 426 ] +/Border [ 0 0 0 ] +>> +endobj +50 0 obj +<< +/Dest (/wI) +/Type /Annot +/Subtype /Link +/Rect [ 99 391 504 402 ] +/Border [ 0 0 0 ] +>> +endobj +51 0 obj +<< +/Dest (jּq-m) +/Type /Annot +/Subtype /Link +/Rect [ 99 367 504 378 ] +/Border [ 0 0 0 ] +>> +endobj +52 0 obj +<< +/Dest (_.3=) +/Type /Annot +/Subtype /Link +/Rect [ 99 355 504 366 ] +/Border [ 0 0 0 ] +>> +endobj +53 0 obj +<< +/Dest (sX0~v) +/Type /Annot +/Subtype /Link +/Rect [ 99 314 504 325 ] +/Border [ 0 0 0 ] +>> +endobj +54 0 obj +<< +/Dest (eeRR) +/Type /Annot +/Subtype /Link +/Rect [ 108 152 513 163 ] +/Border [ 0 0 0 ] +>> +endobj +55 0 obj +<< +/Dest ( m) +/Type /Annot +/Subtype /Link +/Rect [ 99 648 504 665 ] +/Border [ 0 0 0 ] +>> +endobj +56 0 obj +<< +/Dest (F1Np|) +/Type /Annot +/Subtype /Link +/Rect [ 99 290 504 301 ] +/Border [ 0 0 0 ] +>> +endobj +57 0 obj +<< +/Dest (p s=) +/Type /Annot +/Subtype /Link +/Rect [ 99 631 504 648 ] +/Border [ 0 0 0 ] +>> +endobj +58 0 obj +<< +/Dest (IJi&) +/Type /Annot +/Subtype /Link +/Rect [ 99 266 504 277 ] +/Border [ 0 0 0 ] +>> +endobj +59 0 obj +<< +/Dest (rmw1٦$X) +/Type /Annot +/Subtype /Link +/Rect [ 99 242 504 253 ] +/Border [ 0 0 0 ] +>> +endobj +60 0 obj +<< +/Dest (퀮;e~) +/Type /Annot +/Subtype /Link +/Rect [ 99 230 504 241 ] +/Border [ 0 0 0 ] +>> +endobj +61 0 obj +<< +/Dest (ǫti) +/Type /Annot +/Subtype /Link +/Rect [ 99 218 504 229 ] +/Border [ 0 0 0 ] +>> +endobj +62 0 obj +<< +/Dest (BRr ) +/Type /Annot +/Subtype /Link +/Rect [ 99 194 504 205 ] +/Border [ 0 0 0 ] +>> +endobj +63 0 obj +<< +/Dest (fRY) +/Type /Annot +/Subtype /Link +/Rect [ 135 182 504 193 ] +/Border [ 0 0 0 ] +>> +endobj +64 0 obj +<< +/Dest (Le*O) +/Type /Annot +/Subtype /Link +/Rect [ 99 602 504 619 ] +/Border [ 0 0 0 ] +>> +endobj +65 0 obj +<< +/Dest (+PS~? >G) +/Type /Annot +/Subtype /Link +/Rect [ 99 585 504 602 ] +/Border [ 0 0 0 ] +>> +endobj +66 0 obj +<< +/Dest (VTtr/) +/Type /Annot +/Subtype /Link +/Rect [ 99 556 504 573 ] +/Border [ 0 0 0 ] +>> +endobj +67 0 obj +<< +/Dest (63@A) +/Type /Annot +/Subtype /Link +/Rect [ 99 539 504 556 ] +/Border [ 0 0 0 ] +>> +endobj +68 0 obj +<< +/Dest (RZ2) +/Type /Annot +/Subtype /Link +/Rect [ 99 510 504 527 ] +/Border [ 0 0 0 ] +>> +endobj +69 0 obj +<< +/Dest (G{1) +/Type /Annot +/Subtype /Link +/Rect [ 99 493 504 510 ] +/Border [ 0 0 0 ] +>> +endobj +70 0 obj +<< +/Dest (ʖ&^ Z6) +/Type /Annot +/Subtype /Link +/Rect [ 135 451 135 462 ] +/Border [ 0 0 0 ] +>> +endobj +71 0 obj +<< +/Dest (G@\nSey~*Wqj 24{́]#w\\畢Dr}`5nZB") +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +72 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +73 0 obj +<< /Length 1189 /Filter /FlateDecode >> +stream +#kt .J"_):# +ޮ' `HoNcQJȂAm`Yi'dY%&"`\yqwxxGFE9)$4%G+*[ +IS>U>cWj+Q"&P +N{~daaMv R6ψmΔJ.{BH|SNzr6؆ +PH,51f{r(ˉӽd|mT|"5 ?stGPTt@̅.jI6U&IpS^_D%CRsnm:)%]K-BE z 6cb:6빱gh}1]¬=sux>}zwy*:zRF) |9)jf(Hv2'p\ +|4Ӹe6[FfKV!/M|d4" +j~.קŒߏݡmAV*[sݭD$K7@*#J]zurI3]S)lV$mwʹ]OI_37Sr7ly? +{3T +|uH0)+]?QC. [cu~%h>r>oB +4Dݝiq-NK͵XU<"1ꓐ:v@ Zbth7Hhll[9&B#DNC1 Ygsh +}go +]5ly!H?XXd +endstream +endobj +74 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 76 0 R +/Contents 77 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 75 0 R ] +/B [ 1826 0 R 1825 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +75 0 obj +<< +/Dest (f; S_X K"Ovp x?˓8]HL#$~.) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +76 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +77 0 obj +<< /Length 2022 /Filter /FlateDecode >> +stream +7& +KP4V*J ayy=L(mٵo݂ y}9T0J|pw \6%b΄ÉCG3` Vz aWy߶O0X^ތ6S/2dwgӣ}Kcy$W]x}}e: ,ѧ~6߉ Kt2Cu*1qz-95\QK嗐 Veg(a&s,*6 gW +t5IdP3{!W5ym:, +9Eq8'ӥ3^VG6-Tv0q +#o0'ёdn)<2c|'P@RG^b(hQ#bu;} |k>XHY"MN^F~K(*׈=A3<)#^Q/>u1P|y̳42DZ]i"ڒ&~z1W!yDdeEPծSzXhiM8<׍2rh~AGBß7/2 5<"! L!B %Kx7plmG_ɁȮ wdm|8hJPɊΓ!‡QBѯNۉS +Z۲Zxj +`kel'@st2Ρ1V*B;t0iw(umfB?e"L-ڣd6Mv*%/bs"$DҗV 9H +mЁ# +f3#O"cd \W-Z Xpܷq&mzhefar1a@=Iy;Q=!Fҷ +2u?Iy<( +|%94Pk|/'m#9<6W)=qmPbKѕG0g=+upD)Sutxug.iktݎhH9o( +PI8ڥiv'ܓS +endstream +endobj +78 0 obj +<< +/Type /Page +/Parent 1723 0 R +/Resources 80 0 R +/Contents 81 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 79 0 R ] +/B [ 1824 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +79 0 obj +<< +/Dest (\)Co`$Sk/]g^Hi~,}*X"AɝE}֫=U) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +80 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F9 192 0 R /F10 193 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +81 0 obj +<< /Length 6028 /Filter /FlateDecode >> +stream +|im6ɚpbZIL_NZ̰q@8ȇe+HB$GBp ,f"A +a H +(5ai$AT'Ye[% "y"v'F9]s_]L}ݧ}p$YIggd5ʪ@2:}|j!_1򷫯<.GoP2y!n;RDYM Y9͸؝ csʖ23Sc3az]Sab{f_OOTDXW>5vX>Jok=WSؿ&"bߔ`p۽AAGid2Y1~BWם#;0D5 Y +v4F84&om ;EVUe/U<+ٲM Rk{J(}m@Pv>!da>ѧ:v: P28\/*_QmzMo +/s"؈8P8T*JSi +7a[Ca簊J nONvȶ p}h/l13cˬ۵-[qHnxXJJiK2st;Ltjw~~  +YZ 7Mqv7Q]DD쳞tJ6DK Z8!:5Ek?u/3N aTd=F)MXKv}QsO4S,Bq\%P+Brp=? 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#"6ol"&{־`\0⩮v)O4xA=F߱JlJ)LU[|: aC4); N?7§{5mx_kK/nG>9kfHc]"lVRjPuĺ'.Ԯ:ߊ$h|rI~mt*zY ʍ kY+o+T ;*HQ&7A=0$d:αp]3 ;H sgh)JW-r ݙc$ $-EhwT t+=dÞbWLPg?m` +58SsT|U&& +k}BMʇK2UEdl)'5 Lx +fD XL,._x'm@F%\08¹ܘ91fY&7=kDZ}[$n6~IzC2\ia0!Gc8;U`s%!( +V&> +\>tR 1I#5QF +R8ϣBRh>ŗߛ<'=*d![MN&0ýcShۏ8A&"4)WN{nfl̴QFoDDQ؄$ +J$Sɓ +H;:F,D6G2YundP緷jjMK"]ʺ=(6{`W z]'=\dRVψd +endstream +endobj +90 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 92 0 R +/Contents 93 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 91 0 R ] +/B [ 1820 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +91 0 obj +<< +/Dest (\\p\(S7D,w9e R_\r#+aC` #ԍW {;`=QR4B) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +92 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R /F12 195 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +93 0 obj +<< /Length 1609 /Filter /FlateDecode >> +stream +7\RpsAU{ZJɠlZX]cH<RuT{Sl$@ '1sP+e8 +qӥzU'` `nA^7 F&!o'?5/!9j8)CŠ ~Nwॡ4OX򑞛 <>B4je1<ˢ}g&!?kr2b5Z9@Ƃy.$ +1졓Yyx xQ% +0E; C6&7W8m31SXI"$7p7w4TlH%JߢNm|#m!DJZ)K"V@0ۀ""%9'f|7͇5 +rwJ/piP~/ѠH ZE S5~7 + ݁sl߹1Aꆴ@Xt{GjJ1MOf߈j\=WYmeI +<"HԳ$i)XKp7)n){,m"[NoI=Xi +l{ȈE0MG. +۾稅_9<\z=]׬ڂz8;pNSIJ:/2$겜*2H +;Uyt|킐3Ku9RtL$C }NЀgPNT:,\8`ऻJ|HbACU=3(HŇ:|#;V%F y@ nwb2"mAmH`u_.g=&# <;HԀv [ zJ=C%)GH0 &&?7V.IۑFVY%q p%wnW+fZ:s^L +4+I\ + ɼ͐uR}2N\PjnT-E0K8/$SIYÓ&ȟKv!f[$2GHDd ?,̓tu?Kɬ&)B-Wbi"v"?( p8H-܀#vpm?cUDEۣU Nuat~}l!krNZ]9 +{C4S߁=mͧkS8l eC_':&RK-O+ꠢQ}pԔtPa&g jePu֮ߟ/}&0~^'Ͳcj~&2K%bhM + +endstream +endobj +94 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 96 0 R +/Contents 97 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 95 0 R ] +/B [ 1819 0 R 1818 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +95 0 obj +<< +/Dest (hTKFhu]beRYv5Ư5ȏJW `z\\ԔLˆq\({0) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +96 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R +/F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +97 0 obj +<< /Length 1760 /Filter /FlateDecode >> +stream +T +/z/)!.GN,v^cf-B=D谉%R'r!ũj /QgA6}HP͊74`v !aADC+`?@7AU~ vHn% +G7Li vi`#>XGI>ė||{ k3,4 n(C&ꂾ%o{O3vn69L†MMT,[Tt ~Ǚb[ OJ"xkYj";қKHTF_PP]mW#i$>-uvf:#G7^]vF,!6`f5g(ߦ Tt}([Pۇ?Q +1S6Ia08}To[ cv%a/S/olIHd&{ )~j3{}ۆS46+nT]IE{* +\`Dd;l~+D3ϓ3GL"2א]cuA +: +=6|˚l)Zxݗ/::cW.#]BdAD<̐ a|SH řvN +K;Xa}[lyr b~4 +P!?ҫ1K1 +ncP ೉1 "5'f;p!AM|I-P 5;Pӹq2]O `ຌl+ +5T-ne$?ub.+EkopS͔3Qpʹfj,]_DyEdZ_X#2! +-[ׯ#$Dx@M`WRYPr0VhCݐuEقTi.ʡxʔxљ0TS8:Ϸʘ{g?I*j~w,ħ.467-LT{ HH{!@l^q7 +(>+ptB{ͫ)ظ99G\jvx=hfY`U<:॥U i7xVSnֱBT7QܞpF=&xm|:'p^uJIl,yE>?#gתj@/cFo@u6־('€Zj>%E$ICG.f5gQt2N_G`}y9$1c9:% qF=AG18\?2lE.,!P=,%d9vj*vơ.xׇTCTnO _u L1|k.k\!=S ʻϷb%c[?$ z0lc7a7s>?Ae|=ONzcmQ%bوIgo9 Jl^RਪsutGš).:c[#O + +Oy1l*|x&wVn785 8AKÚ[/=*|g"ri] N3ݷ ieQ)G/-] /^X\0LUFq-(frܙՎ]uRF%minyNU]g:#F_|(@Z<,\64,yL. fi;JOYZz§G%5bIY;3\D.xV +endstream +endobj +98 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 100 0 R +/Contents 101 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 99 0 R ] +/B [ 1817 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +99 0 obj +<< +/Dest (fA!"NŰޓ=Խ+S2IBQi4SBO&@&#P]Pؒy) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +100 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F9 192 0 R /F15 197 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +101 0 obj +<< /Length 2481 /Filter /FlateDecode >> +stream +bcv>SeN'A{MΞ!ay7:HGwb|%|R/PВnM +Ӽ:INb=R +_ :kh[G؅cۭOuHEFw3u@#(qfiHvE!n}K"kPbŗ6bt{+Ŭhl<{k*\,Q~(afB=ߊhe2h1ֽ_ +Ș[ wF '8F*/ 4 NKwmz +yAAnRA9kSfjՍ+ojj^mN(ZgzxSyЭ\:`I{kDI? M +E`&yF:2/2T~ Ω^ĹM=v 4:6 *@0..) +d!SFnJhE^M;)|kwQL +&ȵc%(RҟJC"I7[bOJFL M/$]C(#*%1UރK/u]u[l${O9UԄu߄ Y:vXN,|9WymqK$E! +8|9 +;xth4۔!,qbꝍ5Xj{DW +Zb҈7 +9 +kHr4J?{"e&VB2%K06E6PX`{ԝNCdWcNj]|6|aEFÔ3e?C$!\Hjh-M(>9'ԒyX3Ve u"qB ǡ\LQ+/qt:yO=7֙9 gkPfgz.D$ `kPnZ9ҮE5T­!Ehɥ%Ed?v1+ 'ptղv\6!,̹$fzT}w!rBtLf[c *L a!kq/AQq=,^?C}Wkߠk) + A{3L, +@/ +ŲNy8h;@h:яJ1k#N!Su7`Æ`V# ؐ-\-|1W Pw|!~>BJh(_])eBm\ xnAV.{!"vyKZr)%BȲ+UqJL8Z ؃xZaʍ[|wAđ-j"MD~R^Ě3#SpV<CZ+d&i-jɑ?h}dcNՊ!NQ\z  +oTpI]YQK[.g>Zt& ll=Ζ]!4s݈@L{PehJM,=LʁQɫdVf1P$qctVڢTՈf1;Zޘ=߀8jNjPbt!>ID_3 Qn\Kk;/ëVN.&aE\/|HpS]YrtZ!Y^g+OXɧs~;{Gbh :7k1v->ģ۫Pef;z/ +D陈F +H§C| @(44 +̕RI[<nOM%䁵oK(t2fMv!JYdWR = +ăzmS6ߴ + x3.NHR{[Qmn8vj0cKt-E}gƖXOi5In'3Uh7 + L'MDAM$V]PS +@i=G)y\[(~'}i_-ċ~X{wS7޽VI$JYXax"$"rZJ+(ݦ@1 !3_ +endstream +endobj +102 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 104 0 R +/Contents 105 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 103 0 R ] +/B [ 1816 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +103 0 obj +<< +/Dest ("ih8 =Kcj6뮇O+NPy듔$ځ? Tg? ) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +104 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F9 192 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +105 0 obj +<< /Length 4127 /Filter /FlateDecode >> +stream +_/'t!VIJ?OJjnqE;V߆^30%G&Mv8|8`V.1Lly :}"#n{F 1w4_]~<ɥ6rHZL賧a%:u&p&M9p1M ah+Ju]b "2Ly>EUL:X-Q5g;:$ŦPԐS@b"QZ\1ϷCJZT˄g^[곓R9.TPm~|ܡxTb ˜m;5c@0vwːigW?ݠK>g_KkK@P@\7Jok{* V: +Q k;⒫ЫԼTȺ]7?؝$$Nt^Hb"Q}"btuEBb`͊*+0rYi1rC!y +}Z̋}У+{gb39:gZ}09N/~q`х5v'eJp v>b3gJčmeR$qs5ʕr;0fz7 +ꀐh4@!,ua\LXɑ Kt_}7Yr1a _fy_;CQ%3+0`¤01Pp42%^P`' [iځCQ+`k){898UV4`;+ S(wEqnƃ~qd\f[do26S*)tLԢ]Êg ݛ;l9߈/PD5[yz +@-x,Hx腐pRMj"ؑTHܐ禆T9D_\H3 +]6~HQhf;h:(46uF+هj%zOωU,ŏeM*~s}dTPѲ;c?cvv_= +7NyHc~IR2q`~+ؠ<-[C5Q D203 B6#K?`6og)*=6мMLDyU]w&BaQ%$YW"q/T-^df'mU^2|U-yG\R+}3}~pZ?lM2Pv\L_ƍ[1@Aȟ`rW@Gùgs}>us&u`jHU[E :3ݦ%ČY] n:Hku!xg +%}׺'w$\0 +INkU-N0ޱ:13exp Vt +ܸzWlw.&bϯ'P홾**HeYNڄ()r +'%$a(>/Mlj"ۈ0@|+_2q{t!(>vYW?ngg}Kw.((` mN2WlzYy2ҲF +SA*|$'W2d:?\s+=CAܪh\ 5$LZ +|($kCz1jъxY~DA57Uxrז +($:8h{6J)%7ImN !W*擘Xag[[{HwFFSz-kXlijAx2UgMQAMZ888QRMmRC +{ +u!O FJ'MS3XIT,H7FryiW_U e_JЀJ8rO+yj aG +p+4o(aeeO'M+:7n> +1 "G>G ҮhF:/ +xI52]YCdHN>5 Qdֽ6|Y(s=34A`_z3z}\Qth6k ^0hD&j'YBB d?oN2G|ي@d8cM5py(ÞAԐ|]62@_.F-v">R~>բH)^du>uXa$:1󭌒Jg2nhQ,ks^ʛiW;)ٓpLb&?e +IX_C* +(AhFGRiI/}:2 R}dFѵ ;`&ed-[ ;4žAr)\DFz!2M;v.m5h2d3E'dRLG,0=oz h2m3-r\1 M{+D(YŒYr(ةg$ji8M.ӣP\RUykx!NQWis"DتW ++N&y~P=˨#Ǻ'[6,|~ Оimg{8~ʉ&sܾ|d6*B3ųG'`hgg,atg 6VgsFHKs4A%8kxD,S&ok(@}j1"k +'YT]eMLB8}# +' +s+ft'I4-TP W.=aZ+/b3RD1 :rQ7بrE x}߼f3Wt3,I[l`^Z$3ݔ;zNKjb?I7__-V`R,,@UАJHȼ{/sVu)ZTx =mᦅfwGQ.Oxz:#DonlnZUL;N Rˋ'YP +H1V2l7w,=,7'Ȟ)s\ץzBԗkpqwRŻf֍e煬AhzOQW +B$Krz\EQ+5YKlOSEQ:,[^x-m>64+ +S.?K:TOqJ 6*p픬kWY1fg +endstream +endobj +106 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 108 0 R +/Contents 109 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 107 0 R ] +/B [ 1815 0 R 1814 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +107 0 obj +<< +/Dest (҄|l1K!K.Pgt0?\(b&k8_ >ޢ,Ρ DH) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +108 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F12 195 0 R +/F13 196 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +109 0 obj +<< /Length 3126 /Filter /FlateDecode >> +stream +-K0Lt>•x!ʸb^ 6FСo)XFld ¶ +.#+=*d|}ذmV8о59" +ZUW/靌<pһtRnabCRi06"O>"۔%)PL{)dz756u#eu&Q+3ʱCٸTxĘ0b˭U_o$iĩ5Z7<뛬NB+ݦѤMC?J?7^BGoG1(ى%42HBݳ~Mh<;!`\(rl#Si +/箐۹o9nCt%ov6r9J%lA̦rg1"|a:'׵nJ#8)G8NrPi(BC|E/_[ABU^f 8ƫ +oFWZp>BI"x`!S1"͓DyfB6tgZey1ˁP? 1$VM&ХDݶ&@̄C0wmT?H!_R\Ďtu=P1L c.TC_|;湍zڈK! C +BJγefYnL{+`^d92|{2BwJ,t\tDq%_A%3dW> _4ژ5 +pdqcSHhU ֏9_'<\DCF +6~' &Jb ̌^.!L];tH>kX=LxƄGKvO$-I] +_:n]a)Pr-1G7#B jNSeu֭Ά+'T1գ 9+UVgپVU: N1, yQt02O-g +j r,su }`YiB{˖qb$eLeal† +? +HKP7YSC(#S񎔅[(E)Ω^yr~KWER1 +R9.0Q膥ʏȘH@1֨*F+m +!,ަVE@6AOȔI`bĻɢ;0p̣)K 5 UZQ2\8\QfD@vB稱UrDͰbIstt!ӬH>tsO?>KPDD 2{<=zc +VtuO.9$k)QzVTXmZ_dDPf|#U7ՅEٷz@^' %0&c.6T,*UTm )auU>Ǎ,X|jr (B<#eLٟ +c4뒻Z]u[͙vxq{_Lգ^t=&"V _\!ʠ=vw +endstream +endobj +110 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 112 0 R +/Contents 113 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 111 0 R ] +/B [ 1813 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +111 0 obj +<< +/Dest (GX:\r&B]>򇬈~۔N$u\ru< 9*I$7) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +112 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +113 0 obj +<< /Length 1005 /Filter /FlateDecode >> +stream +RYHyAǢEr!vu.,Io(f8%*PF:d +k.hѬ:Sd)- /2k;fKj߄JiHƕ4,1uv*$;ܦj'zDli0O_KyXC)41n~|}dkqP[rpԮMU3̌:,,ڤ4\,xYC1fDqS;leF} byHbs +;0<IE^pZC0ُ?lf޻KdEBhKe#˜vN}e<`D}<Xc##Ș,W8Qv)P0q<ew3QY3FVeQl"S' gvx3T&ӎ[cJT;^MN0qwR1Fw ߒf#ZAZ [ }݉dVq*=+<xv. #= +4KG_\U(>pG`N/h˵3HМQHIE,Z3͜a A/#|,_ 0`R9nfF +耏%ÙTe!1\ҥS@PC]RK.ڈڥ^@^>n 'MZwO@ =4hc!?A{!w#1Ba5{-+Ciww~mSw'1%=vCN3^ + Wh2ȋU{V:}1!TDﰰi$h_cΝ3FU#MFeIp]&{.9FUВ /ƱMH}[5cm /b!6+hlb +endstream +endobj +114 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 116 0 R +/Contents 117 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 115 0 R ] +/B [ 1812 0 R 1811 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +115 0 obj +<< +/Dest (YangDD䏤"Պ2Wq"$drdEF) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +116 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F9 192 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +117 0 obj +<< /Length 3912 /Filter /FlateDecode >> +stream +kaǠ#HHnъZ),Hȯx;9th/ͮ dB0]JB֪w"~VjyN;~T\w+&;#̥ +}k=3&-zqdx0n)\?JrAE'Ր)| +i&tsA/% VVxR\cY\{obvxqae 댂n +h;b +g08(,֥pVު96k/1ΟB?| +X4#Pg[cs6aNu-Gd# +$".n*M}Sd$\:ړe 7(rq$h {9gmiv;ЬAIJoifXS.q+.Vj[īDS_ܸt5|٥gqdw5M@=#߾[̝qS=[y/$VX%kPxF焆]M +qțY$?g= +/\滇4!3t:s RQu:Ľ+ݤkimT%1k1d8V{2fЃln94M|}^-8lҁ~P%)xV +V@x;oZ(S$ #5ڃ3_'isuMh-Q0H8-aFuȳ&:#8V/W&GgM;(Sf`fѸbc"˳ F[MŜ5.5 +/nEBom@3{R|S#m(qH/x\N@9q!9%X ++!6me{նS=*Xn6X#O;hx1޴ޞ W!6h:0 +yt>#+աluܾTz(n7@ό('迗 |NaKj_g/b2)v}Uඌ|*_JS"U4u֛l7'^1o\vn& .{lb%1QCC̄t)Py_Bho.v-?7xڝ*6KʘrwZTꮉiq 2DR$jc +lcc:i5߅hN/9b;Ydq,! zkG͊Gr$͡6g#,^^΄@HD +mL)YmR= qNpaMg$`PBxs1}-憧یŶZ6a֜uTmԈiŷk]g(m +U?lo' +JoX2?6NTIX5 FsE~U4=w&JAʴJCox1Uy1޴D5gL4 iUuݒơٷ2DɜTC rW(<0w71ݸI^ڴRPCSmMib& +yY~Q6u8pD-4|B}׿IB|?ܳR%9Nt묖K +O F^)b-LLƻi$%|@sjQaCe/nj"Cx܌y3C m9_ͤ(\&Yq/V٨)^6 EvfgqOE)ߵg(g}'bVtP"DN 6Vu[FS3@^{pwPյ;$J-|+|&\OhH9 u! q.9JF4Dl{}l[HپK:/赒GFAP0)ƫ+F8nQubCsÜF +j"vp*T˵Xa)` 4\6!y!1'(o + 1![`z_.xj+8/G, f4-d&hTc12tig7:W"xm)$d݂i,Bp㪛cX0μfJN@L<U^rX0&@(Qڠ2K"_1quȊWgqՒB)q_}Wu|2+h] +>`S5p^U +9Ǡ +($>[~`1 [{&I/E*xZg[UK@sY(K嚁dRt:rGjZ/gբ"5;t|l7hx=5,*l6aEw>(4L2ڲ(=H&WgSQƶX#Wښ*h]#KՄ2 +endstream +endobj +118 0 obj +<< +/Type /Page +/Parent 1725 0 R +/Resources 120 0 R +/Contents 121 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 119 0 R ] +/B [ 1810 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +119 0 obj +<< +/Dest (~J.oZmie{ ߫VVԁcƿ%Nn].Q2F$~$I ) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +120 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F10 193 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +121 0 obj +<< /Length 2830 /Filter /FlateDecode >> +stream +*M@'Sf5_ g*PN"{*[᧬F颐=kNt*"޿9Ü@kĭ?U M `ncmX*S_0]h!"瀫y&% +ߓ`֞_6CWI֒9o%[҇CsQEB1|ġbWVd$GD; +j1JWōƛXޠߠR +VآJ"ϯTq܀XlRQ_XTJ[) +{Pʵ3S0DD u,C~* +ĪJjE_U!yZ|L9EӖ0"3;/6m:JJM{z҉1瘫)P*R)ؿv!y4$duJ?FO!yr8iѓ,@h5>%=H5MBF)SuQ{B^H E!}p{cDK8)etĞi;[oE7EЖ:$ZXIy{Ml#wWh2&O8$?O_XpN};> +zw7? +׆~ެȗnBM5(ꆴު9`c;];uRA5E<CɅWet!EAW|hU`vիJ2pFG6+~+[O +Go[Hlr03C]Ǽu`:z(V7zs9dWZ'(d;X.n%.rGx;Mn +ޯwPŧg#:5QVz +HP4!d{|uTƋI2PeU<qbQ'v#)N+A"Ͳb6ģ0p=ݹEP/AU찔ןΔov3ꇗM_A>f^ Zcޣ<{@V)%ݶᎽ{W롱o\ST4FkZYMAAl +lxGl:P",h<'ɞN\=L6$COɼZG$z|3(Q!% +=~!c^dLn#:hoO t8˫($h 3,&+|3]ɐO.%#[/e}fI$Uhj|J;oH=;YNqtKkO(z .q<.`DڊOg\I.[@r C՞KGN(ZD6Cq[cݱ_.YqvzŽhgO-]\* ov~* j+ +W1AyW;el9 Y&fSpSЄ%vn5D@gMJ9qϑƇ&Z:ȼ,NZ +Oz^HX6S9.@E/YF<\1tO-V QS 9m:DloAq"<+}]XK `E +P}=iLC@+eZNj +mfREЃ{ 'Kq8y.k +B:U `_/Yt0^޾+/I&7A}B_xAENiA^2U_N77%o6op +O18)XHPHŃ΃̢?2qJ2]Ing\?BcQuH +oȽ@d*{dNS8'V%>$˥]3.  +8㦷wFĄ +endstream +endobj +122 0 obj +<< +/Type /Page +/Parent 1726 0 R +/Resources 124 0 R +/Contents 125 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 123 0 R ] +/B [ 1809 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +123 0 obj +<< +/Dest (/\([9>ik:lڶYy|B!]DJ%.$) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +124 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F10 193 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +125 0 obj +<< /Length 3832 /Filter /FlateDecode >> +stream +0`)~̅[%E8J10~dMJ-p1#= QJ~6^9i4ݻHMǝhYXFHJmI-o"~W +2C1c6=͍;*@m&L Wy3;gw r$=n#;|G1*3uuyTxQذ|̷]Ebv Pr1?nWT<=1}].ȥP xI r|ԺJߍꡦ%m]% d +H#qh$!YmIrV*2zڻU ˭QZf#0-# }أe橱T$*X3٦a)Wvs +p SQ+fbFNÖF +_1ޭ ~ a5*[vꥵ$}&TNEDe dd/tl/58j +(UE詍 i(|_0|U7>ԪY!PA +pxVTb&DI†ogtS7TTtVO2<ÿ/fi)Rw(DgU#Y^U@tcW > *ṽ,[[ +""7W*8tӌ&~8t c󹒫2Ќ"icAF=s(o G2ڷCOtg벆qGCx@zӓ'I>"^񜹌;f;.[󛂵 a)?dl1RzvP,+g |tGՓ? +LGuhn]/RNzH,*xnxca +_1v'aDyIk&y6 v_gtrlseQl&Q&$}O紐A;J7y4c" +F4. CCdY^IЫ} +$A&\8`CrtD&"3/ +Yr`֧d5i$Q@Iw9qS{x64`ʀNF=A"Lc˿VN͸gn f%\N̨&52!ŻOԈCqV< LOA)/TN)Sacv0"F1ncr4 n Vt`]LRw5&㟅 +R~Z*zٷs;1H_tLd>z6Fu +9G>W+PfC-]% VnMd}!f}ߺB ݴ;kEShl|VΐsRl/dwP@NejH +i̿㴔`1'hv zMX1?q6a\5Ͱ#[5qܽ`>$7˕Ack΂ X*>u>E4.Lϧ|T?ѵ> +endobj +127 0 obj +<< +/Dest (۰~"\rgjx>nJo }\(ij5`]ýاDh Fj) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +128 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +129 0 obj +<< /Length 1975 /Filter /FlateDecode >> +stream +5a؁qLG+c^M +W1tRDGOt1Udy +m1涭އE$gDeh]o[$&7A {݄Dt L=0aZЌ.Ai)v)".d޵և1W '3i&ìh-Z{tMM]&T7aw2ҶX?WLء$4H^X &}Z[TFKIL->ΓbK#\oZ3L2̤ۨx>nٴ#*͵hUiGŸ S4sU_DzunݮCLIzNӘ>z9,6(93#l➂ .\UƻwkH1@3S` 7g <6Gi~pAstH&V0Byvy^Dzſp[,zAJNY ]_¡=2Gn4Q\Wm`a}BuF;kJ$\SO7*JWԎQXFjE7LV#߸1sFC:?ƭh;mzk $(!TRKC#vf}w 浛#u_C}0o]a5 +g>sZ?Q!-.AaF {]v]6ZjxưET1νh?`T#S/OK;$h y"]7-> -Gkx#\?JWr~=Kf9Wuezn#ƲP{(Bat7!āݣ4 ssUV DCLGg@zm'^*ndj!F4!q~w}Ai#]C8UQ`)tנμ O3&,mݧ +7ô38|#=[J!} f&g7N.\ b#C6'R + +.mIBՔEɷ46-A0(kٔݐR,fo4 ߀d؞qTS + ݆ +'\ŧ2߱7X-,9 HŜ2C-f٨J& ǕRj0Z[r@2łRv +R?"@?On`)NSFF=<+iba;.9bLz=ZaΉ!`%$w 6 +%,ܐkG;[Z mAqjȪ5s)xY1d$gNūI *ǃo +C[D!~לKdys*938Rn#q +endstream +endobj +130 0 obj +<< +/Type /Page +/Parent 1726 0 R +/Resources 132 0 R +/Contents 133 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 131 0 R ] +/B [ 1806 0 R 1805 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +131 0 obj +<< +/Dest (3Z{Wd5jjC.~0\\[ [2U[z󊗩) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +132 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F2 1837 0 R /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +133 0 obj +<< /Length 1249 /Filter /FlateDecode >> +stream + [Q dc4t"jkfisd&_ iBJI="[93=iYboIrz# +I"=U`0_ `rmee%fetZ٬? +bsc(v;'vItIF)/v5nD08)8t'<3(A5_h $UtJ1ٙsLe!_+sy02f43+ْ& 瑭[2ZTldfq[}?FىD<%sˢ +S#atɜ9k%x3Pk?Mvj.ݺ':HnO9t!)B;mKY2 +ݕH!gQm a&u4/®Nמ6]L]xטœI.`߰V쮀և3X{68;]&5V9RSf0vW(s4 NEBBrɎC &Lh.*m:S}lys${JV--֠TG r>Q`V#2/^KBEcnV@"z"vn84Q,*70/L g,3ituQzVO!3V|<ץ6t2kԷ`o:49%WM%bR J5=,] lKYKuC%ۏt9˽;: hFWˆI CΜt0\qL ;*~Pwqc-oǹ@`H\Sn|ʷ;|ࡠv"4z?3sgjVjebn@vk|x1xQg4^_聨LUSǙ+0> Ap6,?V*/=F3u!߀ +S(yNT> +endobj +135 0 obj +<< +/Dest (,`OKbrL\) a9oaMZ?\(6@Jz =`.5 ) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +136 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R /F12 195 0 R +/F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +137 0 obj +<< /Length 1611 /Filter /FlateDecode >> +stream +T Je1 ++s?5ټ cJ3ja.$zZt&L$ >F(H=}s||G0È@8/DZXvSNdz|t)7$ {[Ƹp1U"ɀ:Ж.MⰟ2s1j垰D <0O?eF¤Lt9#: Y6.!9-xn=TSoA jӏ>2XooGXF%kws| @~Jߋ%MkV@AG'$B;s},> +endobj +139 0 obj +<< +/Dest (#Ȁ A\n'g_ vM\)0C|xJG- J ifsR&.) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +140 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +141 0 obj +<< /Length 1905 /Filter /FlateDecode >> +stream +n +{+w:i/R/෉t]8B\?,#sn܇%-p| +#φySO'KM5VXYi\ȋ7㉆+=ӳu! +׶͐ _6g^j危ދ +frD ?x@N hd]HmzW`@$IP| ϴ3К؜M[6+*ͿE:"T|2@vv(7~/-Q. +[ NѮ]y*7O&EhNՁ}5!~)GefHEgUخv!xbq!ҞYx̙)#TNߖ,̭:>gu;ڈPe3K3)r-= +rx(]CqdMɄoJC:!V)ve(MYNw&*Awќ߁ Tz+o$+4QQ\bErW7r +7(dmsxțe_Bɫ# +|#-w:C.'S}#f-w~o|RM~2HOdBزa:'.6(^Md* +]G^ ?.:6\?FA:չZ"xosz@#Վ. _]VYIz|xR=D-B +Y.'g|z[בpnVuBelq]CkrL,[?[4|ϘS7Fnf1W)cpQm}&&s(_dB6(@4yFނ +X +U8 GY'"@*LoI>' Sg&S?m,s7+?c֏N`n=Zk +ֆ_dQL/T{ߤiy>Cƚ<1K}!Ec}B4 d!"9HHkA6݋Q;gb]M7h")uyGaJ2zb G!> +endstream +endobj +142 0 obj +<< +/Type /Page +/Parent 1726 0 R +/Resources 144 0 R +/Contents 145 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 143 0 R ] +/B [ 1802 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +143 0 obj +<< +/Dest (q*m'L×e'D,9V%MG|;/^&9zƙvX) +/Type /Annot +/Subtype /Link +/Rect [ 99 101 184 111 ] +/Border [ 0 0 0 ] +>> +endobj +144 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +145 0 obj +<< /Length 1781 /Filter /FlateDecode >> +stream +"'ptP4Y&sڪ8x@gCю/pgz6 ΃^ޤ!FnhZg6S0&䌔f|{2@/:wc.>O'%f;ыT(Vds3u::iGvZ#=8<qܻ}/TR`d]ܺ}}f\WB~y*֞IѼf㯔{̩ft2dy#>i@hE68̨z~d Mpso +{TCHVVi=g?QvJYD} fa@[ +~jva@"0=Y&.U^ ;AAewz]di٠A"nKsE"ԝ2I%>>|2ec4)HkK\?qގ 0:Sg+4@{J(Wǧ!R+~.s*${}GJCztv=4C7HO2넇$zOaaRn'0Jʬ|ɜJ{_½2uƭ-%Q\>A0sz";!Ր5X0e@ͯbhκ2n- T0З{b Ap|Y,W4ߊC +#.eYJ6E5mvB8 ic=t-( +poTyӮX]Bn<}qp~2ZgDƗR^sX׉uN +9 "3\VzM+YcFXDV]!E54C8L6F 1'iPRwDep֋>M)|olH9 [bNp*s։(Geo&ax #`@M);͐tNt%v6Moyqlr`9$ D .|FÜCF1(i|][ݗtBe})&e~9ٚqMFdK]Ѯ?Po] ژ FqOuvۅ*K7Q`>ߟlk=B + +s/O=AMoJ+a!W> +endobj +147 0 obj +<< +/Dest (\\\(-BdghWOD$IOwf%=ؘ+}Է) +/Type /Annot +/Subtype /Link +/Rect [ 428 101 513 111 ] +/Border [ 0 0 0 ] +>> +endobj +148 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +149 0 obj +<< /Length 1248 /Filter /FlateDecode >> +stream +lYabk 8B!φp +| + + edԋAe(Aք$٢bKmKs +¡C_(F* R\ph,W+Jl-_b θk>C6mX وγLxH]cK@d. PI$aS*"%ձE!9˼HfIPZ=̺ Un5j`'nR+HnTN|)^&S_Mڕ,dcN@dǮQa1%,6!l›J4;`AD1 3naLbyc{Q(`==瓺jC mogH-˂rkRɩli{~oe3L,{d}fMBiv|oﾅ6,vؕYe;G!S%ǩeXE[9wU@K0=X$iz2e-D,o5Ofa(ӂ?5\=6DWjLa}quԾ ג`ŢV4| KG +7 "}۴]w!-mhAlcC.8{YkRv]?8~fx v+U +Cy > +pĪ~9EH"[UǢU:V +T~p(a,`ޕAN.1'~lfJ`͚c\"yB4x^MG +~U<ɝbh5,Tbk@ISw&\ݎC0:N#`?J5"ang@o3bYEry]P +I)7 _?q4#ğ (K@nSJ`Trяf"N/S&L9),X Y?5/'v{wc +xPo +#Tr +endstream +endobj +150 0 obj +<< +/Type /Page +/Parent 1726 0 R +/Resources 152 0 R +/Contents 153 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 151 0 R ] +/B [ 1800 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +151 0 obj +<< +/Dest ( 3+1/|yte׿3_VKsH,X;_XVyX) +/Type /Annot +/Subtype /Link +/Rect [ 99 101 184 111 ] +/Border [ 0 0 0 ] +>> +endobj +152 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +153 0 obj +<< /Length 788 /Filter /FlateDecode >> +stream +7:t^)Z(Q8䀷4ΖHI +s`yC0V}u 5\7?:%ۚ?\\~utWZ,YM + lm  +endstream +endobj +154 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 156 0 R +/Contents 157 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 155 0 R ] +/B [ 1799 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +155 0 obj +<< +/Dest (']!.\(ewnvҪ9HR0w hU]"TWΦ=+Zp5TJ.) +/Type /Annot +/Subtype /Link +/Rect [ 428 101 513 111 ] +/Border [ 0 0 0 ] +>> +endobj +156 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F1 198 0 R /F3 1838 0 R /F5 201 0 R /F7 191 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +157 0 obj +<< /Length 2276 /Filter /FlateDecode >> +stream +CCfGro֎4UO%ؑcSn=jQ/.#^ /YȈMl0~GzuL +i;plu5ei*D3c3(/]̜+AUJFtAK8>$@ r-OItBdXTBKEu{m +07ѐMq1hEMnCAcZ G"lO .h ۴w9w2QХ71GNa1h7t“X%33'@365cR"s+N+a}w8GUooː78nU?RඈRZ&A,ImRpAvǃRnز">( Q kRnϴnP:gsZt`/'Ӏz(PZt8zTy<݃zuj@ZwϽ#;>o~sj)x(M'ChUFQ^aMwZu1HGjH9W1fH*(xz[hfG[L]S<|*a{2 +IK1-rN,Mrj2/LsyqmbEq+X.(nd{AlE=M~wvކ$HL LBդg"t e:?%vt%&٪^8U +E 7d^!9>u3T>`SHӑl~vOWX +UCͮW]b*Z;-4N޺/:?Ok]ǖwUPĝ` R.wE2hgTҲXIA_8qh\a+ofڌ4&x$ jXEؤ˖+fcQP +njP&(ӔUĎ8Px]'_X)^ߓV,([&"|%V7\*죣暣~?rP v }X»CMH%/rՀ˭:!yc5v/{j|.鉑) U9K=W~ȁ+% >z&= y>uD'_$Ȟ&s<4t¹o:2Y) @/CFuσri;a֦! +endstream +endobj +158 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 160 0 R +/Contents 161 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 159 0 R ] +/B [ 1798 0 R 1797 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +159 0 obj +<< +/Dest ('vyIxZŧ뮹7hZ#\(”{C Ø*) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +160 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +161 0 obj +<< /Length 2555 /Filter /FlateDecode >> +stream +V,@8$eCPYILBГL~^g3hrZ"WO_ r2< e%Hَ)xItp&J] 0D  +# lLW@j BŪTBD2&#\HK3}ٷM\g> Zv]g%HZߕE&mjVL),LVYbrdD,="]]dk!]=߃{ڍEmş!m§}(JacbD_sEO`8O#5֮[Ҁ"e/@'x ^{RpTbW~h @q999F㰱 XWhs``2~階qWg"{&Ў)*;HbG)/ߒr:op?Ep<OSB <X1Z]*Us#F"knsZ7)'؟Ed9L ]99 aTȿ x+r:XsXPVꉀ4Y -SbQ89 ƶ {*!i ^ ³نnwOMKVX7jLB}gX<2z]G[CUʝ>&Pw+VY/CИ<6 37lBj?ꗢ. >ˡXf+BHE1 je7co;8U*<5mUjOfuu+H@hqjiA}P|߼"Cޖ)aQmUcHmŅn3EGJD+_ >7:]|08D7baVThii U`kQtT۞ ) k+Pt֏aKZ +tdᏱx@J74Q-EbbߚV/f#)[1ɥ +0p489WM҇ɚ]-Uy~P"::YݰUHVV͑g_a:H0,g͞E4=U@S ~8PbXO# +>Z1_]vM`g@Xo,Й`3U5F;{Ukhׯ6óT|W,zx‹ +!9OzÒ3Q2ErTܞܸ;X^+r)fq^-`'jEZ$43=/.v}0LvʨT|..j\s5dAi(yl {YeSz + +&("e}zZcxƍ#yɘk-aټlK0˒=TFE_EvT@~59к߄s8GfZv˜_niGT 5 +),riR$ʅ,*lC.(gV5TLm8ZѴH)/18l6} +:pXp|/]RL\& +wA  :ۤ8# +_`9sDgԿF<);bv׳uc? {\KSqW;δ_zWlVVR%HO\ jyO T +w م@> +endobj +163 0 obj +<< +/Dest (3 m&I;T6}BCإGZ9" ƞ}V HVòI?*t@g]) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +164 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +165 0 obj +<< /Length 3044 /Filter /FlateDecode >> +stream +>N3v1RM4r~1o}|8B1XG௵ї>v9lPwRgǚ7`Ο!AdJݑ +6 {ԡr 6oc\"OtGtrn[FN,p +ˆ!"f*8Q.J+s@}' j̱/q쫊/;@D;, +#+~T IXPij>4ZoLOfN +`,ŏ2K|b)ހ.; fqIwE>CTc.x: +]ɓ"+($F-3^R G=ekK0H͚_ȵ7 !&|w\ݦڰޮHލ>"$ƆjabN'vb*ne^ג=27R0Aа'@$z.oRaV [̗'w| +ڠ +Ɓ)y3a 9Ƅ5 +x x?ԡY,0]V],!ay"W>A"L8`@m.X}l_]йS̑P@Kn8f +v~mt&@;CMefHl2ׁ؈+my5bh;M)_fzd>6Rodֳ:ؘf83wjPꏅ4ՅWBNEq5|t,Elsgώ +~x(? Ax9F!tEK\*Bx\i{b PC[ؾHӸZՖ-i֕RDM;nBU> +Xf>d@ѡ>`[O#K8v%S +/T[fNlWr +U:'N}A"sQc4'6;{#ΡDg;j5t&=4zSM@fYΪcU56&6Dsjd<1u÷?+|` W k.):>D{q&u#ȟɎ&k9`ޭSzh%> Yw_ /*7Rb%r4iV%8ۢow]}"ҵq{D4+mMb RL}g!_9:i/ $Ne|`˼jk`rW=Z<yՈoH*BJU GFl n_wE̵BL.r<9T 4! +26btenKxRޟ7 e+$✴cV!8[+I7ڝ#&U'o1vd̂f5iɂn1-EVY^kIUx%yBEUjCDNX~zfnC*OB`^8tRKĻ.DLggj*tΰffEGU!;8Ϯ?ĉw{:f9ՄP<%}eBGA-,?7 OBsP>bG>2kBo*:Nޚ~,Ja)|5UF@B%p%`G?1Z4y] ˲ xpclnmToub0N'n\MKF@2`+N/#Y؀J6w+$*Y65 GoZ$θ BڅebOˍr?1/ĸov؉uE¾wi7Emۄ+j$ʙ9;v:KN;'ٚ'ǢPNǔlLo{4nA*Յ=,`WVv9!(jaGnhf(rzS"Y] +G$̨r.Prk+ +TAAT琔AJql=㸯&g|sf/&~8nq3_j \)urtt-)Er3c~(tp;;~ɽ`_td-:ƵaC~̿hgHJ2 hyyJJySpچq`r2!D;΍W`wFbOUfr(f9إ!+H)h\2/tQKu z|=5QQJkzpN¬G)ь/e{Qԑ2^%~!8mf뻟~#W-٭o@9$޸o)E>`QRsd +C{ iފ:ԸKFQL9Yh3}w +ټ` C&mm=q*qʴ0m:taNMKdgk/ӆjTak_d[)vhY +%8pw?G@Y{Z̴UGb^nKC`;jQsj JZ +m e|\,'"p2S5NiMfLX*]> +fxsFȢWen1#| +1h1YX=TWp;n]x=uAl%;?=]RhNGMG?K,1ko?kf&c?YRmK+Ht𶶒69ibJWnRxo蕄> w{]"otN +`.HqghH9j+rW8$x(rr>o 0訧>0? +<78ɥC%Y({3ӵ+}m,aF4z7 )e菉0*g/)ך.xR,@1@n( +,$\)vplM*|x?> Q$Y-c()Y"D|' +endstream +endobj +166 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 168 0 R +/Contents 169 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 167 0 R ] +/B [ 1795 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +167 0 obj +<< +/Dest (_; X̨kߠ?1va2\)f\)ƯHC[馹$h) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +168 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +169 0 obj +<< /Length 2505 /Filter /FlateDecode >> +stream +1e]ʹQ(]7/$|.IBbpBEh&3tA.Ӈ[;XlY7gfBσ~+^h7(Y+s+F +7?YC4> +#:CBJ-wOٯFq. +RVX$YTFVGϡ@#.o؇j{<3917eAowQ A2Aˠ1U1PE2ˠ˽1=grox1EX  +e +h;m;3MO2TD/ +:TXt qrw-x(\)fxDyҴ +Ê+gm-\|sc + 'rgw +{qE5d0921: EP0xD 71 Hq8IUN.MEHN6ra:6/?hCm=cUGc>+#<qEӀngGu)^hJ%شpڜE;_w"U+rGe+j0Bmkٶ^o+O +ף IF2SuiOKx>at|O|6agw~3#&oE/URr'5aI#sQ#Ůûȇ+Jx vDEɞ^J,@LmlD@xv0 Y +ď1F*$ʲof BNn Jg}BPFL. ѕtmX39]6)RwZ +Opwr0I5ؽx:p"I;jUx"E3ADV#b4Biv_;&fppj;8"YLC.静k0fӀm1Lb`5X'mȧ:վj{5(c{~:N/޹emf3QZڪrEK[B @#FB?&= aWPWQl;du*fZ]ӯq2tq!^Wm𺚊jϗKT:(#<LrqyҮ{9o%pڭm+e~%aH.b| 054Ԕ/р]%[WH7b>0,t8 +Ϗor3u)rcs btz|Ϯ4Rl!8Bz3s/dždk<ŭ%xu-б5hT_S!Mz+4>q  +3WQ?}PSIi +oԥb\@k㩦|JL!`C % r9덓:ve<œUذ bOzSt (x9 ,OKz9&C9Iin3(r|C@X-wEUJ!Y7jaa>qǸWֲL +LΛ*i<ϩsyH +YY)w9u9>[{C`N];Ic&ubo$d[dۡ +5j':̢r˜Y ʾA>i]V%!ZDQ f<,¸+%J` +=//likK([s{}Ti7Xdn<4a†fx R@O_쳣+Op U28 +bt&pmJ]ݐӧWuORs U[hX[#`HR!,ٵ8D=JjP5%Onp'Wҁ12-mnOB +!anK/'?U>4s1BQ +endstream +endobj +170 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 172 0 R +/Contents 173 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 171 0 R ] +/B [ 1794 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +171 0 obj +<< +/Dest (!pѓ^m\n^,e21kdCZVB\nYfqK<"I4x9) +/Type /Annot +/Subtype /Link +/Rect [ 99 101 184 111 ] +/Border [ 0 0 0 ] +>> +endobj +172 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +173 0 obj +<< /Length 2731 /Filter /FlateDecode >> +stream +ÑZjL84BJb=Z.->4O1GɹMY/|kz@A,>tl?VMy'{PkW̘3l<СDb[2Xm_ĵC&(|JBv6쁦7k'}ڣHFM24A4A7act)_~ɡ&*7&ΨЏJnfB\+UC!I^Ty^$'ۉ%zBr1m !K:N0\zb)u`94c m+Ƴ/{L;I1l ̦}XFס醋J,϶9Z0NZG2q.J<| +NEFz(aF}PQwi<6LgBҀQ>;g+FsbwH_%^ PALetLz,S̬;x0lRm^4!_'}ʳ~G0J? +|y}Jr$<'Ue/qZ[jK*K*" +(pu݅_#qMlL,)fԺ7sB*ѮjŃi,jF!PPK@jh!ҍ$}O{ǻDMc1_9u>h$! +u.U'@촉! $|eoQ>9-yt]γ\y7mz4pq{@?K:T/g>d{`!> J'B~"ȧxR |O?odcd5Gm(!xvįpɓ@*`ntv<\^\ˎ٭TN.=na{6=flSi=wXk̒v/A"$|pZPXF7Ǐa$jH +vȭ3*jy#N2v a:WM4$%N޾_@Z>Hݾ{ d9)Z)!N=jđjA~s +-Kԫu08j:pU,XJmbv|` +mcGbWIac8 `= NƯ1TTČ*d>Ѷ(HA1%b/b9q5f,L;H? ԃchD9b3 s*b]v**(A7r=n#sd`UecF1{{VXFYת٨J޳t>-5;{m7ǟG[|.P$)YԎ:>RQyk< lccHAtÌ"15[)ֺmJ{̌#'š;ʠӫ  +Se@At(# 8'%ai9 ~i:+EǭPqQ:`tZ%]n^7;O>ӈ@B +. +h/UpBz2I J ^y* +W54W8L ar p`Rp9 L[Xhrjt,-:oOSx2*^LY9%0DK,֮+҅Ɇ󼊾szT +jPAg,> +endstream +endobj +174 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 176 0 R +/Contents 177 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 175 0 R ] +/B [ 1793 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +175 0 obj +<< +/Dest (=7mG sv0 23^r#\\GnkCTڐ X KM_\n~Z) +/Type /Annot +/Subtype /Link +/Rect [ 428 101 513 111 ] +/Border [ 0 0 0 ] +>> +endobj +176 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +177 0 obj +<< /Length 1919 /Filter /FlateDecode >> +stream +jQ2|XLoSUьOH-UDorκeAթkөsiP+(tYNÑ<\^] /5Gڡ(}np_@/x<{9*{slSU_^[:Ni|PcLԶa,anȚxb@>,2g~E.̷2H Kl4{fHWo-* yw}\ +MLUf| ;!R",0'ǟ0afqsHL0FȦ +"{s (sӚ +Aq&I6q3, +%:rbuU{yq0(`J L後Œ9s 6Mx0Miy +/i8Q&SHBZKgsfu$IqD3L XDH+(Q'"ƮkLJLG;90Kח[G82aؼI N޵U[3HC>%@>%8 ]):PkΖ p)(G-B2gD +;1Lװ5Ka +Mj/ +u4sytz]w鍃@kcu/rɃD1>ٻg袪 Ij1%>O~XXn#9u6 d% +$e?J3 L޶%5'جPC5?B"cs#Ocߔ늲wQaD;MjKxK"]sP>,[rdZC#(QR䥛@ۘ9č>ng!T[V2鎬'c/WFB=s I_5W,I hj$S|#("mXzGi} +oS +TZҙ:*6lߥK5x8P#%J7{(j; +HkBT̹; +endstream +endobj +178 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 180 0 R +/Contents 181 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 179 0 R ] +/B [ 1792 0 R 1791 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +179 0 obj +<< +/Dest (Y9tWoJa#>_{VDUX_ꥉiPJu) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +180 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F2 1837 0 R /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F6 190 0 R /F7 191 0 R +/F9 192 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +181 0 obj +<< /Length 3882 /Filter /FlateDecode >> +stream +g>867?jX;cΠe\ +cϞL]qqf +0mG%~t~ex Y~I2\q̀}"Cn/C,|h&%(_@ XB]?X{x:9 qovmm?L.ɯH(H5,+){࿣RD&LDyM87Օщ`Gd9TA̔'"8W|2Z> ,a*rL?v;7L4khZȈ7/4muma"(5făzQ}ֈȆ`vSMH +1z~29qc4dQ9s~W̚Az;eo'6~Qv]i@,饛dߚ]AȈHd-  +S2a2ZؙAxCdbF]?'A2<mN`>Rak2> +{ +OFYV# '8(EkK^h\xnUƷuG^^$YntIJRչ68+Nwg $x{kw !V5&-K9%U߇):V$#qyy."@[Zz~ +Z`>p3.!Qw0;ͯuiA;>OH;2@|k:.]9'QGFGO7.mv~J"E +EƵs[i6zي$l»'鬬19a&K9zȥduٺ@vH4 + 71Ah]6;J_DhUjZޓ&y*F0x;#Iz1)=ꭑ0Z|^YmO-z?$ߕ[js\؊I*1*wF +B]'qpä0Ӛ^) `4_-QkHB3;{漇:0fwƓ3j +-w=p089JeoDZ[+C]szw*qzwExbr36 +1u;[̅׻C~czI[^#&).ww= +p*jP2#E`ckƒ _8m8^ݫ#NVu'Y" + +A:Ef+\ PĎutNúp֑Ama㩷lUYfK@ƐOULE4B`V:=2EZ̖[*Yc0f_|,J$nɿ^TY e-qBs[a];祏z4[ +ݦu07V?%=$(%)h 3]+CjH0[[Ȣ*W^zj + +x [yڤ[9[=5tT]n: PQ@E(D%)7m뻛o)5Lz Nqm1̷j!_O5yHL;)|D܁?٤A.1f 59qA7U}5)#ӊeK-rbdQ3}~ G֖ r2Uan&vX5F w!6Ԛ6R^ѹi{%Ni\5СmF"kfŽ5D]S4 `kf\RxJ#ܸ(/.'pA;ڐ[+)}~Q&7/NH(xDiŵSPCӯ6 İ:>d8fZ%_o=<b-:DgicVUuM?.y&ý8 YHZ-4s׬BXf }~7軱+3v@яbY:I'ǡ:'t' +P8o/gʔۙnKعٺ94Z+r.Nh0y6gq!(bl(8C̡j 7-m)mi^HGKo1A 61BR]-nqQgV˜<#Ui +d>}i mUnֲZҦL:;4hù@6>-|BGޢ)6&cQ?IQ\b79|z"?]? ;T7Ca<9l<8[(8^(@W|*EojI_e +=I_h6fOsub@L`P<0؃ ng@$]Chbae8@ukUH z 1f PDv=v-1q\F`d$ABn5zk\ZUhJOKHųY`$,8zfO}I9yEb=a):Ǻpj\d>FGZ;x46* +l&rAWўnp/Pwt]MˌǯvuD٬asȿ+fM[ 'ʠkք֠6kcm}ߙе]-\a<ށa%?/>5^gJYRj] +ypeǥ +xPEqyvF_?國=P] Dھ_6\+$tP0AfڧpĴ8}fڧmjSYh1z3˟18B7!HW%Ul?~Dx5b.eV.D0#xԻ 8[q0,-)6,dYW1#| P* kZS뀧@@#ؔ[f&8D)~pQsȩ>PhwP-E;styVW&/͂bɂsO4jT[v0Nl HWV +mb)E"k .)\cXUQdhb6{qg){Gh%ߊ/xCKhsz8;" +PoNN,)yȩ8-QrS:e.[=ba Ҹ>&>5PV5̲v gj߃)hB=sj}nd9֏ +];Vu *+\m + *,OLz +endstream +endobj +182 0 obj +<< +/Type /Page +/Parent 1727 0 R +/Resources 184 0 R +/Contents 185 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 183 0 R ] +/B [ 1790 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +183 0 obj +<< +/Dest (D<1߿ioB^+I^8{KJqLGy`E{_be8<=NP) +/Type /Annot +/Subtype /Link +/Rect [ 99 100 184 110 ] +/Border [ 0 0 0 ] +>> +endobj +184 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F9 192 0 R /F13 196 0 R +/F15 197 0 R >> +/ExtGState << /GS1 1845 0 R /GS2 194 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +185 0 obj +<< /Length 1455 /Filter /FlateDecode >> +stream +^҃GrCVdQ&Gܹ>,+ʚE"']!9k;n()'B&>o ݷ.F2MDﵴۻNހąwnUOJª]$ӌ#$FLڇj- +Q%d;x%2~  kEޱ7'ec3b;Вo +DܡdAt4_/C` 32a~[ +ý2il%=Оfo߮iF])xG2A,޲ +Z%ɪCjf|0] G.iz(8Yr1 +a SUd[굆3PMN탵9w ٢:oiە;ud"5/΢|3JDNYĔ6>{t.H-L,Of0ߘ9u7ׂȐbxM2PuPEBFrawX$ϯvNUO#-'"3 #B9 Q|]Wf(sM>v6kX`ZHD)ܝ9oEt1bfXV;-Pן4:}KWC2\Ĕ ? M(~ oB-T)ԛ}gۉ?lzdaKDt09NeK-"$ +ࣁ +lx +!56gS'v +FԐ9 +wUб;<>ns&m4kpܵ~w3/;MKij(vjFi/*6ƕ@;iWJk$(4[wD>v{_V5ڼm[PƠ,WhZm:6)2FҲe3gjNnI~4F Af!UϾZ;5wK/F!B1o 9$5ٞ̿y0_.IX=/YQXE&Ըj +GhA6}~LjG +Qy(d8UA%lQ8H04q9{M'6l~&~l7%JiG^wP3-luO"aV-q~DN2@}'4tzԉ`Y͌OtUd7[Iw3t +9 +#NSGCgns + {G 5q@EfAh埒kN0CP~W[_C}}@fG{6>5<1ҾǰHTaO1f=oRRBxwO->M,^yo\{qIt.^{:Hggm)L +endstream +endobj +186 0 obj +<< +/Type /Page +/Parent 1728 0 R +/Resources 188 0 R +/Contents 189 0 R +/CropBox [ 54 72 558 720 ] +/Annots [ 187 0 R ] +/B [ 1789 0 R ] +/MediaBox [ 0 0 612 792 ] +/Rotate 0 +>> +endobj +187 0 obj +<< +/Dest (c*y\)-IqR~\(tPA F`Il.\(gs*Nh\\6`9s^ھ/e) +/Type /Annot +/Subtype /Link +/Rect [ 428 100 513 110 ] +/Border [ 0 0 0 ] +>> +endobj +188 0 obj +<< +/ProcSet [ /PDF /Text ] +/Font << /F3 1838 0 R /F4 1841 0 R /F5 201 0 R /F7 191 0 R /F13 196 0 R >> +/ExtGState << /GS1 1845 0 R >> +/ColorSpace << /Cs5 1833 0 R >> +>> +endobj +189 0 obj +<< /Length 913 /Filter /FlateDecode >> +stream +a:3Oat|VH@Ls*GtۘQKtb=7S?rK/5/0TpEAt' $ՙϬC&KuoE꓿KSaYo 2&(T pa _z\)niaCJ[9 j]q#}@ahؽA낛 +Zk9 ~BȨ dJ(ry,L4Y֔Fm\bVHBU'{( z){nYt +sSFa +l˓3aj+`F|O,F1_EVHuJG) (z79!%-g޴~M[1]sQ 5IhOX2rO9rgYOo֔ P~Hsi@ +>UfP\A +bi]~!Fdy"hDl.*pYνe&1{ODc/ٯ[H/@D~VӰzcy$t |7ŧ c R+pߺN,rYoTP,Н(yNlؗTƉɁlc~ ^"n3dG*luG ٲjI4n +ky5k7~,Da0ZgvJ< +իey}PB2N`} +8RBu܏vo5_ Mc(r{OȴymEl䫝JI^ɡ6 +endstream +endobj +190 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Times-Roman +>> +endobj +191 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Times-Roman +>> +endobj +192 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Helvetica +>> +endobj +193 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding 199 0 R +/BaseFont /Symbol +/ToUnicode 200 0 R +>> +endobj +194 0 obj +<< +/Type /ExtGState +/SA true +/SM 0.02 +/TR /Identity +>> +endobj +195 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Times-Italic +>> +endobj +196 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Times-Bold +>> +endobj +197 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Helvetica-Bold +>> +endobj +198 0 obj +<< +/Type /Font +/Subtype /Type1 +/Encoding /WinAnsiEncoding +/BaseFont /Courier +>> +endobj +199 0 obj +<< +/Type /Encoding +/Differences [ 1 /Omega /one /zero /space ] +>> +endobj +200 0 obj +<< /Filter /FlateDecode /Length 234 >> +stream +@t8s܍MlH2]>ᤶ-2f?Rl\e!l+6 .( +^mV%x'kpUe@\"w;Rhr?l]ompǰIcW5':TVti`S|mXWrx]NfCxLI;rH n<~0]f\+S'):BW)gsJ6 +* +endstream +endobj +201 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 121 +/Widths [ 250 0 0 0 0 0 0 0 0 0 0 0 250 333 250 0 0 500 500 500 500 500 500 +500 0 0 0 0 0 0 0 0 0 556 556 556 611 0 0 0 0 0 0 0 500 0 0 0 0 +0 0 556 500 0 0 0 0 0 0 0 0 0 0 0 0 444 500 444 500 444 278 500 +500 222 222 444 222 778 500 500 500 0 333 444 278 500 444 667 0 +444 ] +/Encoding /WinAnsiEncoding +/BaseFont /GFGIOF+Helvetica-Condensed-Oblique +/FontDescriptor 202 0 R +>> +endobj +202 0 obj +<< +/Type /FontDescriptor +/Ascent 750 +/CapHeight 750 +/Descent -189 +/Flags 96 +/FontBBox [ -174 -250 1118 990 ] +/FontName /GFGIOF+Helvetica-Condensed-Oblique +/ItalicAngle -12 +/StemV 79 +/XHeight 556 +/CharSet (H^{ 3&ލnH2Ԛ';{%-"nbHP T0m͟_S!\ +vo"THiJ2j2\n;-vN #6%B$ InT) +/FontFile3 203 0 R +>> +endobj +203 0 obj +<< /Filter /FlateDecode /Length 2841 /Subtype /Type1C >> +stream +Onv7ɗг¸;>̼UL!qõzw2ĖI #GUC)kɻٽ^_i+Nmdysy3Fŭzw^zDzG2XĘ[DU +l&<6jX;z'AGS;?xpPr +04 ތ/x4ǂkb>R0ěd$a': ǃ+8zY.6™V(I2; Ax7=ǔgSb)mü@t +kA^SjFqcEޮ {&w_.k" O~$rM~9֕Ϗ3-c4yf @r4Dͥ +a)B&Ģ38855R.{>DE{ʀ$jfSIv%f~"EХ"d2r~f{kJ|"ekw8h?l3弲 +`uK<ЭQ%a9Nap}%ς?-`1GyCtMմd^ޱȲIXn<.>ԉtTm p[֮ٓۃE 9> $; i&2l:C7ICo{ā21Jt7bGYH8.>Z + +AcyפBR35շcm2/gu DQmv1;Hv4;CZ,k f3COq| ɄCw;dw^k(52i@d +όNRo<׻fe4q#rX^Q(M:=_\a;e9m +>·@6\]H9Ĺ%GE24H'HݢZʸbS>Ym(u[ QĂ*)oN O!;8& $0Ew25זЈ8J=D Y`+2#\Fzox$X8Ci7"DU)1c"GIМͲgsFr6l">Wfo+y>~:"H? ;6[\Ժ<X4 IKξ)ozSB^AGȂ)x?y6x9hN˷=,NcHsQi.ERݚ5mm*f-1wsP/M4)~QdU^jUdCeWJc*MF(.6)c(zrH$.vYW +8j g=5?0, +-s/dRqz oxg(Fl@]"6 7lDWf{[UϲJ`8I#/M>7(~~༏ilMmpƸ/P:a\ۢ c!L / +>~3Pr/O<PUi3l#)].xP&4րmf5 Þg@m7nЬzCn2i&dd1nX itwCǮR`?-ӎv]JY[r<,lj|Wtz1ok_":cS=0\ҽToL/`=crs_&6URBVI j2>`?؀8$tK|+gܒ0Oa'^Xrcb2J!^L|LfflN>ScJBI9 +)ߟ5o#H,u)wTz*\ؤ35[ʙPGk\C&H:ʻG~;"Wp;FtM5*rmXݣa Kĵ,=Fw<،Iql۬*H8x*ڗ?. }3,"S7akdglzïݞGC\#USn,=X~K16pɚ]ud-] +P1 +жYcWUL3b Dm?Q=M(9Fkᩂ瑈P)]>+Q'4ϓ;9V#{C@w}ފjnR:NiXtovV"B FXUIg]j>ʧ3:3`NTO8 k%Si(mXD_̦}wm5Z md Z +endstream +endobj +204 0 obj +[ +/CalRGB << /WhitePoint [ 0.9505 1 1.089 ] /Gamma [ 2.22221 2.22221 2.22221 ] +/Matrix [ 0.4124 0.2126 0.0193 0.3576 0.71519 0.1192 0.1805 0.0722 0.9505 ] >> + +] +endobj +205 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 116 +/Widths [ 250 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 556 0 0 0 0 0 0 0 0 500 0 0 0 0 0 0 556 0 0 0 0 0 0 0 0 0 +0 0 0 0 444 0 444 0 444 278 0 0 222 0 444 0 778 500 500 500 0 333 +444 278 ] +/Encoding /WinAnsiEncoding +/BaseFont /NHFIBB+Helvetica-Condensed-Oblique +/FontDescriptor 206 0 R +>> +endobj +206 0 obj +<< +/Type /FontDescriptor +/Ascent 750 +/CapHeight 750 +/Descent -189 +/Flags 96 +/FontBBox [ -174 -250 1118 990 ] +/FontName /NHFIBB+Helvetica-Condensed-Oblique +/ItalicAngle -12 +/StemV 79 +/XHeight 556 +/CharSet (SqɮUm mňy^;UoА~>z) +/FontFile3 207 0 R +>> +endobj +207 0 obj +<< /Filter /FlateDecode /Length 1407 /Subtype /Type1C >> +stream +gM +·̿&m3H8ӌ_Yow9us}r~Ta(1~H Ze҃{H#Buuxxb 3?)ߪ+>hA}И0  6ȏx+P"<7>֚OшDht|ݤTV{ْ.M/w\Ͻr]9CubFq< 5Y)Eη01to'5;eʵATT̀fyuxz^lm"TRPeᇋ|E$5~c੫쩶(( X3`P:T·'8Wfo8QdSIm1ߋy0ڮK[ +[GHu.\r3C<&ۋTF|e" S5+ʝlC/x@SHmh|]2.EM WRw\ъ驪K0yߍ{P4bB5C{gtK +%68fMQLF/Y!ac߱uxX. `kB]u%iu󅬟ȯU,%? >D\#. O6g`Qx ׋-Z vdŊ +{ʫ娨 F",_ +J% EF[!sj; +8wD ,ދ+#|DVPĀ99a-ysONlywX{ϼȠBWf[X +ID=)k 9$K?p +zz(T>w)5%|HF89r* +^zgCq2i9/GF[$H}V; +;QMAi;ئ'o'O"k<-hXF +N2VN̜Gz?.鐈09ةpwCfkyX#m/] nSn+͌_ZS.rxP훏wY7h:A&x=*Q$+B\+ 4ڔ),"ITs:A1كQC._O +endstream +endobj +208 0 obj +<< +/Type /Font +/Subtype /Type1 +/FirstChar 32 +/LastChar 119 +/Widths [ 250 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 556 0 556 611 0 500 611 0 278 0 0 500 0 0 0 556 0 611 556 500 +0 0 0 0 0 0 0 0 0 0 0 0 500 500 444 500 500 278 500 500 278 0 444 +278 778 500 500 500 0 333 444 278 0 0 667 ] +/Encoding /WinAnsiEncoding +/BaseFont /NHFHMH+Helvetica-Condensed-Bold +/FontDescriptor 209 0 R +>> +endobj +209 0 obj +<< +/Type /FontDescriptor +/Ascent 750 +/CapHeight 750 +/Descent -189 +/Flags 262176 +/FontBBox [ -169 -250 1091 991 ] +/FontName /NHFHMH+Helvetica-Condensed-Bold +/ItalicAngle 0 +/StemV 130 +/XHeight 564 +/CharSet (I2w:!\rs?gal\(uNS0g$k/ ¶VKUc) +/FontFile3 210 0 R +>> +endobj +210 0 obj +<< /Filter /FlateDecode /Length 2518 /Subtype /Type1C >> +stream +u t +o=t2 lߺЙp +=F.'[? yfjH8d3JthĨ\ěM@ƶRah +;>m.F4&"嵨KL%lu ,lm/jjW\/< +' h3%Px5rSp%s.!t#+NBswqGem~HvW^G8n8/nvx%ˠEO*m|WyZĴdngX0'4a2T`i +Jz3)0yXug+MGq4[}!L"Cw- %}8XI gO8}!6EGKU-3iȄA8gC~Zvoqw +t lfJK{.I˵&hzݶɬ16q2}Ɵpv.3 :q}jxbD'$O447#&2Qa.THi3rm|Ya_y^0+*$r'=ce}{I.?V/"_{IJ{!>6?;P)GD'6clـSW$8/F9שcFL#-d^õݩYcT\z{~ +k0Q46pwyr[_(.w#ɳ镚8W +Gq. rOx ㆽA% +xq +Ы*X 3)uj5LTiVl.EzF$}B` 6=eS$ۍ&.Р=/?+]a^ !)tXaqN +\7J8eξ˵ +C.0A +!(Lܴͣ-CXxqôV5"*A-,fm:?C`*2 +m1ALbJҺ0"c»Ze +PZm<.{\"RXo% LbŒpP1X{r3lKp?r$%KԒPp+GR,ytN!-J.F<@!U@ H>n&G+B%:qICU=2YEO?:ЍFbog0q"ū!}@B\`]>ՏG{ROWAf1:{gzúDDƒqV8weS"/j+QqOt+igzlhRJ,RPrᣧQ3hx"M+hgFC'|8_/եM{/t*c%^4H +D<KB) ROKFe6L"{: W ;',g'xi8D05UP\a\8 1gBEK!Հ3J>3Z kon31kM<S T΀!b-7롣Ďw&ENv)y4xnN6Ρ]b(d@5MڍDp8x)`8-iy;&q#8GB*dm[ 3@P9G*j{`?Mj+hӚeoMm|HКX3NB2B#cr0n)zaX A뚏6& +0M))4 kD䜲:GH%A9Mi@8ZG\JJ Ӵ5|#Nft p+TTsdB.ATD +ZZE|haH'cˍ +/nq4˕*F^}= ^34_,m1N0T4Ty L.4OP)S2Nͤig]=锨sZ'Q"8{tx(oF];, гΣnI >OɌ +*MBo5-gA4-.βB +endstream +endobj +211 0 obj +<< +/D [ 1735 0 R /XYZ null null null ] +>> +endobj +212 0 obj +<< +/D [ 1735 0 R /XYZ null null null ] +>> +endobj +213 0 obj +<< +/D [ 1735 0 R /XYZ 107 374 null ] +>> +endobj +214 0 obj +<< +/D [ 1735 0 R /XYZ 107 374 null ] +>> +endobj +215 0 obj +<< +/D [ 1735 0 R /XYZ 107 601 null ] +>> +endobj +216 0 obj +<< +/D [ 1735 0 R /XYZ 107 511 null ] +>> +endobj +217 0 obj +<< +/D [ 1735 0 R /XYZ 107 369 null ] +>> +endobj +218 0 obj +<< +/D [ 1735 0 R /XYZ 107 346 null ] +>> +endobj +219 0 obj +<< +/D [ 1735 0 R /XYZ 107 325 null ] +>> +endobj +220 0 obj +<< +/D [ 1735 0 R /XYZ 107 304 null ] +>> +endobj +221 0 obj +<< +/D [ 1735 0 R /XYZ 107 283 null ] +>> +endobj +222 0 obj +<< +/D [ 1735 0 R /XYZ 107 262 null ] +>> +endobj +223 0 obj +<< +/D [ 1735 0 R /XYZ 413 130 null ] +>> +endobj +224 0 obj +<< +/D [ 1735 0 R /XYZ 197 292 null ] +>> +endobj +225 0 obj +<< +/D [ 1735 0 R /XYZ 197 277 null ] +>> +endobj +226 0 obj +<< +/D [ 1735 0 R /XYZ 197 261 null ] +>> +endobj +227 0 obj +<< +/D [ 1735 0 R /XYZ 197 250 null ] +>> +endobj +228 0 obj +<< +/D [ 1 0 R /XYZ null null null ] +>> +endobj +229 0 obj +<< +/D [ 1 0 R /XYZ null null null ] +>> +endobj +230 0 obj +<< +/D [ 1 0 R /XYZ 107 110 null ] +>> +endobj +231 0 obj +<< +/D [ 1 0 R /XYZ 107 684 null ] +>> +endobj +232 0 obj +<< +/D [ 1 0 R /XYZ 107 623 null ] +>> +endobj +233 0 obj +<< +/D [ 1 0 R /XYZ 107 600 null ] +>> +endobj +234 0 obj +<< +/D [ 1 0 R /XYZ 107 572 null ] +>> +endobj +235 0 obj +<< +/D [ 1 0 R /XYZ 107 556 null ] +>> +endobj +236 0 obj +<< +/D [ 1 0 R /XYZ 107 540 null ] +>> +endobj +237 0 obj +<< +/D [ 1 0 R /XYZ 107 524 null ] +>> +endobj +238 0 obj +<< +/D [ 1 0 R /XYZ 107 508 null ] +>> +endobj +239 0 obj +<< +/D [ 1 0 R /XYZ 107 492 null ] +>> +endobj +240 0 obj +<< +/D [ 1 0 R /XYZ 107 476 null ] +>> +endobj +241 0 obj +<< +/D [ 1 0 R /XYZ 107 460 null ] +>> +endobj +242 0 obj +<< +/D [ 1 0 R /XYZ 107 444 null ] +>> +endobj +243 0 obj +<< +/D [ 1 0 R /XYZ 107 428 null ] +>> +endobj +244 0 obj +<< +/D [ 1 0 R /XYZ 107 412 null ] +>> +endobj +245 0 obj +<< +/D [ 1 0 R /XYZ 107 396 null ] +>> +endobj +246 0 obj +<< +/D [ 1 0 R /XYZ 107 380 null ] +>> +endobj +247 0 obj +<< +/D [ 1 0 R /XYZ 107 357 null ] +>> +endobj +248 0 obj +<< +/D [ 1 0 R /XYZ 107 324 null ] +>> +endobj +249 0 obj +<< +/D [ 1 0 R /XYZ 107 218 null ] +>> +endobj +250 0 obj +<< +/D [ 1 0 R /XYZ 107 196 null ] +>> +endobj +251 0 obj +<< +/D [ 1 0 R /XYZ 107 174 null ] +>> +endobj +252 0 obj +<< +/D [ 6 0 R /XYZ null null null ] +>> +endobj +253 0 obj +<< +/D [ 6 0 R /XYZ null null null ] +>> +endobj +254 0 obj +<< +/D [ 6 0 R /XYZ 107 110 null ] +>> +endobj +255 0 obj +<< +/D [ 6 0 R /XYZ 107 684 null ] +>> +endobj +256 0 obj +<< +/D [ 6 0 R /XYZ 107 620 null ] +>> +endobj +257 0 obj +<< +/D [ 1746 0 R /XYZ null null null ] +>> +endobj +258 0 obj +<< +/D [ 1746 0 R /XYZ null null null ] +>> +endobj +259 0 obj +<< +/D [ 1746 0 R /XYZ 98 695 null ] +>> +endobj +260 0 obj +<< +/D [ 1746 0 R /XYZ 98 110 null ] +>> +endobj +261 0 obj +<< +/D [ 10 0 R /XYZ null null null ] +>> +endobj +262 0 obj +<< +/D [ 10 0 R /XYZ 107 625 null ] +>> +endobj +263 0 obj +<< +/D [ 10 0 R /XYZ 143 608 null ] +>> +endobj +264 0 obj +<< +/D [ 10 0 R /XYZ 143 596 null ] +>> +endobj +265 0 obj +<< +/D [ 10 0 R /XYZ 107 572 null ] +>> +endobj +266 0 obj +<< +/D [ 10 0 R /XYZ 107 543 null ] +>> +endobj +267 0 obj +<< +/D [ 10 0 R /XYZ 107 526 null ] +>> +endobj +268 0 obj +<< +/D [ 10 0 R /XYZ 143 509 null ] +>> +endobj +269 0 obj +<< +/D [ 10 0 R /XYZ 143 497 null ] +>> +endobj +270 0 obj +<< +/D [ 10 0 R /XYZ 143 485 null ] +>> +endobj +271 0 obj +<< +/D [ 10 0 R /XYZ 143 473 null ] +>> +endobj +272 0 obj +<< +/D [ 10 0 R /XYZ 179 461 null ] +>> +endobj +273 0 obj +<< +/D [ 10 0 R /XYZ 179 449 null ] +>> +endobj +274 0 obj +<< +/D [ 10 0 R /XYZ 107 425 null ] +>> +endobj +275 0 obj +<< +/D [ 10 0 R /XYZ 107 408 null ] +>> +endobj +276 0 obj +<< +/D [ 10 0 R /XYZ 179 391 null ] +>> +endobj +277 0 obj +<< +/D [ 10 0 R /XYZ 179 379 null ] +>> +endobj +278 0 obj +<< +/D [ 10 0 R /XYZ 179 367 null ] +>> +endobj +279 0 obj +<< +/D [ 10 0 R /XYZ 179 355 null ] +>> +endobj +280 0 obj +<< +/D [ 10 0 R /XYZ 107 331 null ] +>> +endobj +281 0 obj +<< +/D [ 10 0 R /XYZ 107 314 null ] +>> +endobj +282 0 obj +<< +/D [ 10 0 R /XYZ 179 297 null ] +>> +endobj +283 0 obj +<< +/D [ 10 0 R /XYZ 107 273 null ] +>> +endobj +284 0 obj +<< +/D [ 10 0 R /XYZ 107 256 null ] +>> +endobj +285 0 obj +<< +/D [ 10 0 R /XYZ 107 227 null ] +>> +endobj +286 0 obj +<< +/D [ 10 0 R /XYZ 107 227 null ] +>> +endobj +287 0 obj +<< +/D [ 10 0 R /XYZ 107 210 null ] +>> +endobj +288 0 obj +<< +/D [ 10 0 R /XYZ 179 193 null ] +>> +endobj +289 0 obj +<< +/D [ 10 0 R /XYZ 179 181 null ] +>> +endobj +290 0 obj +<< +/D [ 10 0 R /XYZ 179 169 null ] +>> +endobj +291 0 obj +<< +/D [ 10 0 R /XYZ 107 110 null ] +>> +endobj +292 0 obj +<< +/D [ 10 0 R /XYZ 107 684 null ] +>> +endobj +293 0 obj +<< +/D [ 10 0 R /XYZ 107 621 null ] +>> +endobj +294 0 obj +<< +/D [ 10 0 R /XYZ 107 603 null ] +>> +endobj +295 0 obj +<< +/D [ 10 0 R /XYZ 107 591 null ] +>> +endobj +296 0 obj +<< +/D [ 10 0 R /XYZ 107 568 null ] +>> +endobj +297 0 obj +<< +/D [ 10 0 R /XYZ 107 539 null ] +>> +endobj +298 0 obj +<< +/D [ 10 0 R /XYZ 107 522 null ] +>> +endobj +299 0 obj +<< +/D [ 10 0 R /XYZ 107 504 null ] +>> +endobj +300 0 obj +<< +/D [ 10 0 R /XYZ 107 492 null ] +>> +endobj +301 0 obj +<< +/D [ 10 0 R /XYZ 107 480 null ] +>> +endobj +302 0 obj +<< +/D [ 10 0 R /XYZ 107 468 null ] +>> +endobj +303 0 obj +<< +/D [ 10 0 R /XYZ 107 456 null ] +>> +endobj +304 0 obj +<< +/D [ 10 0 R /XYZ 107 444 null ] +>> +endobj +305 0 obj +<< +/D [ 10 0 R /XYZ 107 421 null ] +>> +endobj +306 0 obj +<< +/D [ 10 0 R /XYZ 107 404 null ] +>> +endobj +307 0 obj +<< +/D [ 10 0 R /XYZ 107 386 null ] +>> +endobj +308 0 obj +<< +/D [ 10 0 R /XYZ 107 374 null ] +>> +endobj +309 0 obj +<< +/D [ 10 0 R /XYZ 107 362 null ] +>> +endobj +310 0 obj +<< +/D [ 10 0 R /XYZ 107 350 null ] +>> +endobj +311 0 obj +<< +/D [ 10 0 R /XYZ 107 327 null ] +>> +endobj +312 0 obj +<< +/D [ 10 0 R /XYZ 107 310 null ] +>> +endobj +313 0 obj +<< +/D [ 10 0 R /XYZ 107 292 null ] +>> +endobj +314 0 obj +<< +/D [ 10 0 R /XYZ 107 269 null ] +>> +endobj +315 0 obj +<< +/D [ 10 0 R /XYZ 107 252 null ] +>> +endobj +316 0 obj +<< +/D [ 10 0 R /XYZ 107 223 null ] +>> +endobj +317 0 obj +<< +/D [ 10 0 R /XYZ 107 206 null ] +>> +endobj +318 0 obj +<< +/D [ 10 0 R /XYZ 107 188 null ] +>> +endobj +319 0 obj +<< +/D [ 10 0 R /XYZ 107 176 null ] +>> +endobj +320 0 obj +<< +/D [ 10 0 R /XYZ 107 164 null ] +>> +endobj +321 0 obj +<< +/D [ 46 0 R /XYZ null null null ] +>> +endobj +322 0 obj +<< +/D [ 46 0 R /XYZ null null null ] +>> +endobj +323 0 obj +<< +/D [ 46 0 R /XYZ 134 468 null ] +>> +endobj +324 0 obj +<< +/D [ 46 0 R /XYZ 134 444 null ] +>> +endobj +325 0 obj +<< +/D [ 46 0 R /XYZ 134 432 null ] +>> +endobj +326 0 obj +<< +/D [ 46 0 R /XYZ 134 408 null ] +>> +endobj +327 0 obj +<< +/D [ 46 0 R /XYZ 134 384 null ] +>> +endobj +328 0 obj +<< +/D [ 46 0 R /XYZ 134 372 null ] +>> +endobj +329 0 obj +<< +/D [ 46 0 R /XYZ 134 331 null ] +>> +endobj +330 0 obj +<< +/D [ 46 0 R /XYZ 98 669 null ] +>> +endobj +331 0 obj +<< +/D [ 46 0 R /XYZ 134 307 null ] +>> +endobj +332 0 obj +<< +/D [ 46 0 R /XYZ 98 652 null ] +>> +endobj +333 0 obj +<< +/D [ 46 0 R /XYZ 134 283 null ] +>> +endobj +334 0 obj +<< +/D [ 46 0 R /XYZ 134 259 null ] +>> +endobj +335 0 obj +<< +/D [ 46 0 R /XYZ 134 247 null ] +>> +endobj +336 0 obj +<< +/D [ 46 0 R /XYZ 134 235 null ] +>> +endobj +337 0 obj +<< +/D [ 46 0 R /XYZ 134 211 null ] +>> +endobj +338 0 obj +<< +/D [ 46 0 R /XYZ 134 199 null ] +>> +endobj +339 0 obj +<< +/D [ 46 0 R /XYZ 98 623 null ] +>> +endobj +340 0 obj +<< +/D [ 46 0 R /XYZ 98 606 null ] +>> +endobj +341 0 obj +<< +/D [ 46 0 R /XYZ 98 577 null ] +>> +endobj +342 0 obj +<< +/D [ 46 0 R /XYZ 98 560 null ] +>> +endobj +343 0 obj +<< +/D [ 46 0 R /XYZ 98 531 null ] +>> +endobj +344 0 obj +<< +/D [ 46 0 R /XYZ 98 514 null ] +>> +endobj +345 0 obj +<< +/D [ 46 0 R /XYZ 134 468 null ] +>> +endobj +346 0 obj +<< +/D [ 46 0 R /XYZ 98 695 null ] +>> +endobj +347 0 obj +<< +/D [ 46 0 R /XYZ 98 110 null ] +>> +endobj +348 0 obj +<< +/D [ 46 0 R /XYZ 98 665 null ] +>> +endobj +349 0 obj +<< +/D [ 46 0 R /XYZ 98 648 null ] +>> +endobj +350 0 obj +<< +/D [ 46 0 R /XYZ 98 619 null ] +>> +endobj +351 0 obj +<< +/D [ 46 0 R /XYZ 98 602 null ] +>> +endobj +352 0 obj +<< +/D [ 46 0 R /XYZ 98 573 null ] +>> +endobj +353 0 obj +<< +/D [ 46 0 R /XYZ 98 556 null ] +>> +endobj +354 0 obj +<< +/D [ 46 0 R /XYZ 98 527 null ] +>> +endobj +355 0 obj +<< +/D [ 46 0 R /XYZ 98 510 null ] +>> +endobj +356 0 obj +<< +/D [ 46 0 R /XYZ 98 481 null ] +>> +endobj +357 0 obj +<< +/D [ 46 0 R /XYZ 98 462 null ] +>> +endobj +358 0 obj +<< +/D [ 46 0 R /XYZ 98 450 null ] +>> +endobj +359 0 obj +<< +/D [ 46 0 R /XYZ 98 438 null ] +>> +endobj +360 0 obj +<< +/D [ 46 0 R /XYZ 98 426 null ] +>> +endobj +361 0 obj +<< +/D [ 46 0 R /XYZ 98 414 null ] +>> +endobj +362 0 obj +<< +/D [ 46 0 R /XYZ 98 402 null ] +>> +endobj +363 0 obj +<< +/D [ 46 0 R /XYZ 98 390 null ] +>> +endobj +364 0 obj +<< +/D [ 46 0 R /XYZ 98 378 null ] +>> +endobj +365 0 obj +<< +/D [ 46 0 R /XYZ 98 366 null ] +>> +endobj +366 0 obj +<< +/D [ 46 0 R /XYZ 98 344 null ] +>> +endobj +367 0 obj +<< +/D [ 46 0 R /XYZ 98 325 null ] +>> +endobj +368 0 obj +<< +/D [ 46 0 R /XYZ 98 313 null ] +>> +endobj +369 0 obj +<< +/D [ 46 0 R /XYZ 98 301 null ] +>> +endobj +370 0 obj +<< +/D [ 46 0 R /XYZ 98 289 null ] +>> +endobj +371 0 obj +<< +/D [ 46 0 R /XYZ 98 277 null ] +>> +endobj +372 0 obj +<< +/D [ 46 0 R /XYZ 98 265 null ] +>> +endobj +373 0 obj +<< +/D [ 46 0 R /XYZ 98 253 null ] +>> +endobj +374 0 obj +<< +/D [ 46 0 R /XYZ 98 241 null ] +>> +endobj +375 0 obj +<< +/D [ 46 0 R /XYZ 98 229 null ] +>> +endobj +376 0 obj +<< +/D [ 46 0 R /XYZ 98 217 null ] +>> +endobj +377 0 obj +<< +/D [ 46 0 R /XYZ 98 205 null ] +>> +endobj +378 0 obj +<< +/D [ 46 0 R /XYZ 98 193 null ] +>> +endobj +379 0 obj +<< +/D [ 74 0 R /XYZ null null null ] +>> +endobj +380 0 obj +<< +/D [ 74 0 R /XYZ null null null ] +>> +endobj +381 0 obj +<< +/D [ 74 0 R /XYZ 513 701 null ] +>> +endobj +382 0 obj +<< +/D [ 74 0 R /XYZ 513 701 null ] +>> +endobj +383 0 obj +<< +/D [ 74 0 R /XYZ 107 110 null ] +>> +endobj +384 0 obj +<< +/D [ 74 0 R /XYZ 464 717 null ] +>> +endobj +385 0 obj +<< +/D [ 74 0 R /XYZ 107 640 null ] +>> +endobj +386 0 obj +<< +/D [ 74 0 R /XYZ 107 582 null ] +>> +endobj +387 0 obj +<< +/D [ 74 0 R /XYZ 107 549 null ] +>> +endobj +388 0 obj +<< +/D [ 74 0 R /XYZ 107 503 null ] +>> +endobj +389 0 obj +<< +/D [ 74 0 R /XYZ 107 409 null ] +>> +endobj +390 0 obj +<< +/D [ 74 0 R /XYZ 107 326 null ] +>> +endobj +391 0 obj +<< +/D [ 74 0 R /XYZ 107 293 null ] +>> +endobj +392 0 obj +<< +/D [ 78 0 R /XYZ null null null ] +>> +endobj +393 0 obj +<< +/D [ 78 0 R /XYZ 355 531 null ] +>> +endobj +394 0 obj +<< +/D [ 78 0 R /XYZ 98 695 null ] +>> +endobj +395 0 obj +<< +/D [ 78 0 R /XYZ 98 110 null ] +>> +endobj +396 0 obj +<< +/D [ 78 0 R /XYZ 98 666 null ] +>> +endobj +397 0 obj +<< +/D [ 78 0 R /XYZ 98 633 null ] +>> +endobj +398 0 obj +<< +/D [ 78 0 R /XYZ 98 525 null ] +>> +endobj +399 0 obj +<< +/D [ 78 0 R /XYZ 98 216 null ] +>> +endobj +400 0 obj +<< +/D [ 82 0 R /XYZ null null null ] +>> +endobj +401 0 obj +<< +/D [ 82 0 R /XYZ 107 695 null ] +>> +endobj +402 0 obj +<< +/D [ 82 0 R /XYZ 107 110 null ] +>> +endobj +403 0 obj +<< +/D [ 82 0 R /XYZ 107 666 null ] +>> +endobj +404 0 obj +<< +/D [ 82 0 R /XYZ 107 621 null ] +>> +endobj +405 0 obj +<< +/D [ 82 0 R /XYZ 107 600 null ] +>> +endobj +406 0 obj +<< +/D [ 82 0 R /XYZ 107 540 null ] +>> +endobj +407 0 obj +<< +/D [ 82 0 R /XYZ 107 519 null ] +>> +endobj +408 0 obj +<< +/D [ 82 0 R /XYZ 107 485 null ] +>> +endobj +409 0 obj +<< +/D [ 1786 0 R /XYZ null null null ] +>> +endobj +410 0 obj +<< +/D [ 1786 0 R /XYZ null null null ] +>> +endobj +411 0 obj +<< +/D [ 86 0 R /XYZ null null null ] +>> +endobj +412 0 obj +<< +/D [ 86 0 R /XYZ 513 701 null ] +>> +endobj +413 0 obj +<< +/D [ 86 0 R /XYZ 513 701 null ] +>> +endobj +414 0 obj +<< +/D [ 86 0 R /XYZ 107 641 null ] +>> +endobj +415 0 obj +<< +/D [ 86 0 R /XYZ 107 641 null ] +>> +endobj +416 0 obj +<< +/D [ 86 0 R /XYZ 107 110 null ] +>> +endobj +417 0 obj +<< +/D [ 86 0 R /XYZ 464 717 null ] +>> +endobj +418 0 obj +<< +/D [ 86 0 R /XYZ 107 640 null ] +>> +endobj +419 0 obj +<< +/D [ 86 0 R /XYZ 107 579 null ] +>> +endobj +420 0 obj +<< +/D [ 86 0 R /XYZ 107 531 null ] +>> +endobj +421 0 obj +<< +/D [ 86 0 R /XYZ 107 510 null ] +>> +endobj +422 0 obj +<< +/D [ 86 0 R /XYZ 107 470 null ] +>> +endobj +423 0 obj +<< +/D [ 86 0 R /XYZ 107 454 null ] +>> +endobj +424 0 obj +<< +/D [ 86 0 R /XYZ 107 438 null ] +>> +endobj +425 0 obj +<< +/D [ 86 0 R /XYZ 107 422 null ] +>> +endobj +426 0 obj +<< +/D [ 86 0 R /XYZ 107 400 null ] +>> +endobj +427 0 obj +<< +/D [ 86 0 R /XYZ 107 366 null ] +>> +endobj +428 0 obj +<< +/D [ 86 0 R /XYZ 107 318 null ] +>> +endobj +429 0 obj +<< +/D [ 86 0 R /XYZ 107 297 null ] +>> +endobj +430 0 obj +<< +/D [ 86 0 R /XYZ 107 245 null ] +>> +endobj +431 0 obj +<< +/D [ 86 0 R /XYZ 107 229 null ] +>> +endobj +432 0 obj +<< +/D [ 86 0 R /XYZ 107 213 null ] +>> +endobj +433 0 obj +<< +/D [ 86 0 R /XYZ 107 197 null ] +>> +endobj +434 0 obj +<< +/D [ 90 0 R /XYZ null null null ] +>> +endobj +435 0 obj +<< +/D [ 90 0 R /XYZ 98 695 null ] +>> +endobj +436 0 obj +<< +/D [ 90 0 R /XYZ 98 110 null ] +>> +endobj +437 0 obj +<< +/D [ 90 0 R /XYZ 98 665 null ] +>> +endobj +438 0 obj +<< +/D [ 90 0 R /XYZ 98 644 null ] +>> +endobj +439 0 obj +<< +/D [ 90 0 R /XYZ 98 604 null ] +>> +endobj +440 0 obj +<< +/D [ 90 0 R /XYZ 98 576 null ] +>> +endobj +441 0 obj +<< +/D [ 90 0 R /XYZ 98 554 null ] +>> +endobj +442 0 obj +<< +/D [ 90 0 R /XYZ 98 520 null ] +>> +endobj +443 0 obj +<< +/D [ 90 0 R /XYZ 98 412 null ] +>> +endobj +444 0 obj +<< +/D [ 90 0 R /XYZ 98 391 null ] +>> +endobj +445 0 obj +<< +/D [ 90 0 R /XYZ 98 345 null ] +>> +endobj +446 0 obj +<< +/D [ 94 0 R /XYZ null null null ] +>> +endobj +447 0 obj +<< +/D [ 94 0 R /XYZ 513 701 null ] +>> +endobj +448 0 obj +<< +/D [ 94 0 R /XYZ 513 701 null ] +>> +endobj +449 0 obj +<< +/D [ 94 0 R /XYZ 107 110 null ] +>> +endobj +450 0 obj +<< +/D [ 94 0 R /XYZ 464 717 null ] +>> +endobj +451 0 obj +<< +/D [ 94 0 R /XYZ 107 640 null ] +>> +endobj +452 0 obj +<< +/D [ 94 0 R /XYZ 107 579 null ] +>> +endobj +453 0 obj +<< +/D [ 94 0 R /XYZ 107 527 null ] +>> +endobj +454 0 obj +<< +/D [ 94 0 R /XYZ 107 511 null ] +>> +endobj +455 0 obj +<< +/D [ 94 0 R /XYZ 107 495 null ] +>> +endobj +456 0 obj +<< +/D [ 94 0 R /XYZ 107 471 null ] +>> +endobj +457 0 obj +<< +/D [ 94 0 R /XYZ 107 450 null ] +>> +endobj +458 0 obj +<< +/D [ 94 0 R /XYZ 107 404 null ] +>> +endobj +459 0 obj +<< +/D [ 94 0 R /XYZ 107 381 null ] +>> +endobj +460 0 obj +<< +/D [ 94 0 R /XYZ 107 368 null ] +>> +endobj +461 0 obj +<< +/D [ 94 0 R /XYZ 107 336 null ] +>> +endobj +462 0 obj +<< +/D [ 94 0 R /XYZ 208 336 null ] +>> +endobj +463 0 obj +<< +/D [ 94 0 R /XYZ 310 336 null ] +>> +endobj +464 0 obj +<< +/D [ 94 0 R /XYZ 411 348 null ] +>> +endobj +465 0 obj +<< +/D [ 94 0 R /XYZ 107 317 null ] +>> +endobj +466 0 obj +<< +/D [ 94 0 R /XYZ 208 317 null ] +>> +endobj +467 0 obj +<< +/D [ 94 0 R /XYZ 310 317 null ] +>> +endobj +468 0 obj +<< +/D [ 94 0 R /XYZ 411 317 null ] +>> +endobj +469 0 obj +<< +/D [ 94 0 R /XYZ 107 298 null ] +>> +endobj +470 0 obj +<< +/D [ 94 0 R /XYZ 208 298 null ] +>> +endobj +471 0 obj +<< +/D [ 94 0 R /XYZ 310 298 null ] +>> +endobj +472 0 obj +<< +/D [ 94 0 R /XYZ 411 298 null ] +>> +endobj +473 0 obj +<< +/D [ 94 0 R /XYZ 107 279 null ] +>> +endobj +474 0 obj +<< +/D [ 94 0 R /XYZ 208 279 null ] +>> +endobj +475 0 obj +<< +/D [ 94 0 R /XYZ 310 279 null ] +>> +endobj +476 0 obj +<< +/D [ 94 0 R /XYZ 411 279 null ] +>> +endobj +477 0 obj +<< +/D [ 98 0 R /XYZ 355 669 null ] +>> +endobj +478 0 obj +<< +/D [ 98 0 R /XYZ 98 695 null ] +>> +endobj +479 0 obj +<< +/D [ 98 0 R /XYZ 98 110 null ] +>> +endobj +480 0 obj +<< +/D [ 98 0 R /XYZ 98 663 null ] +>> +endobj +481 0 obj +<< +/D [ 98 0 R /XYZ 98 305 null ] +>> +endobj +482 0 obj +<< +/D [ 98 0 R /XYZ 98 285 null ] +>> +endobj +483 0 obj +<< +/D [ 102 0 R /XYZ 364 669 null ] +>> +endobj +484 0 obj +<< +/D [ 102 0 R /XYZ 107 695 null ] +>> +endobj +485 0 obj +<< +/D [ 102 0 R /XYZ 107 110 null ] +>> +endobj +486 0 obj +<< +/D [ 102 0 R /XYZ 107 663 null ] +>> +endobj +487 0 obj +<< +/D [ 102 0 R /XYZ 107 229 null ] +>> +endobj +488 0 obj +<< +/D [ 102 0 R /XYZ 107 208 null ] +>> +endobj +489 0 obj +<< +/D [ 1769 0 R /XYZ null null null ] +>> +endobj +490 0 obj +<< +/D [ 106 0 R /XYZ null null null ] +>> +endobj +491 0 obj +<< +/D [ 106 0 R /XYZ 513 701 null ] +>> +endobj +492 0 obj +<< +/D [ 106 0 R /XYZ 513 701 null ] +>> +endobj +493 0 obj +<< +/D [ 106 0 R /XYZ 107 110 null ] +>> +endobj +494 0 obj +<< +/D [ 106 0 R /XYZ 464 717 null ] +>> +endobj +495 0 obj +<< +/D [ 106 0 R /XYZ 107 640 null ] +>> +endobj +496 0 obj +<< +/D [ 106 0 R /XYZ 107 579 null ] +>> +endobj +497 0 obj +<< +/D [ 106 0 R /XYZ 107 553 null ] +>> +endobj +498 0 obj +<< +/D [ 106 0 R /XYZ 215 491 null ] +>> +endobj +499 0 obj +<< +/D [ 106 0 R /XYZ 215 485 null ] +>> +endobj +500 0 obj +<< +/D [ 106 0 R /XYZ 215 465 null ] +>> +endobj +501 0 obj +<< +/D [ 106 0 R /XYZ 364 465 null ] +>> +endobj +502 0 obj +<< +/D [ 106 0 R /XYZ 215 446 null ] +>> +endobj +503 0 obj +<< +/D [ 106 0 R /XYZ 364 446 null ] +>> +endobj +504 0 obj +<< +/D [ 106 0 R /XYZ 215 427 null ] +>> +endobj +505 0 obj +<< +/D [ 106 0 R /XYZ 364 427 null ] +>> +endobj +506 0 obj +<< +/D [ 106 0 R /XYZ 215 408 null ] +>> +endobj +507 0 obj +<< +/D [ 106 0 R /XYZ 364 408 null ] +>> +endobj +508 0 obj +<< +/D [ 106 0 R /XYZ 215 389 null ] +>> +endobj +509 0 obj +<< +/D [ 106 0 R /XYZ 364 389 null ] +>> +endobj +510 0 obj +<< +/D [ 106 0 R /XYZ 215 370 null ] +>> +endobj +511 0 obj +<< +/D [ 106 0 R /XYZ 364 370 null ] +>> +endobj +512 0 obj +<< +/D [ 106 0 R /XYZ 215 351 null ] +>> +endobj +513 0 obj +<< +/D [ 106 0 R /XYZ 364 351 null ] +>> +endobj +514 0 obj +<< +/D [ 106 0 R /XYZ 215 332 null ] +>> +endobj +515 0 obj +<< +/D [ 106 0 R /XYZ 364 332 null ] +>> +endobj +516 0 obj +<< +/D [ 106 0 R /XYZ 215 313 null ] +>> +endobj +517 0 obj +<< +/D [ 106 0 R /XYZ 364 313 null ] +>> +endobj +518 0 obj +<< +/D [ 106 0 R /XYZ 215 294 null ] +>> +endobj +519 0 obj +<< +/D [ 106 0 R /XYZ 364 294 null ] +>> +endobj +520 0 obj +<< +/D [ 106 0 R /XYZ 215 275 null ] +>> +endobj +521 0 obj +<< +/D [ 106 0 R /XYZ 364 275 null ] +>> +endobj +522 0 obj +<< +/D [ 106 0 R /XYZ 215 256 null ] +>> +endobj +523 0 obj +<< +/D [ 106 0 R /XYZ 364 256 null ] +>> +endobj +524 0 obj +<< +/D [ 106 0 R /XYZ 215 237 null ] +>> +endobj +525 0 obj +<< +/D [ 106 0 R /XYZ 364 237 null ] +>> +endobj +526 0 obj +<< +/D [ 106 0 R /XYZ 215 218 null ] +>> +endobj +527 0 obj +<< +/D [ 106 0 R /XYZ 364 218 null ] +>> +endobj +528 0 obj +<< +/D [ 106 0 R /XYZ 215 199 null ] +>> +endobj +529 0 obj +<< +/D [ 106 0 R /XYZ 364 199 null ] +>> +endobj +530 0 obj +<< +/D [ 106 0 R /XYZ 215 180 null ] +>> +endobj +531 0 obj +<< +/D [ 106 0 R /XYZ 364 180 null ] +>> +endobj +532 0 obj +<< +/D [ 106 0 R /XYZ 215 161 null ] +>> +endobj +533 0 obj +<< +/D [ 106 0 R /XYZ 364 161 null ] +>> +endobj +534 0 obj +<< +/D [ 110 0 R /XYZ null null null ] +>> +endobj +535 0 obj +<< +/D [ 110 0 R /XYZ 98 695 null ] +>> +endobj +536 0 obj +<< +/D [ 110 0 R /XYZ 98 110 null ] +>> +endobj +537 0 obj +<< +/D [ 110 0 R /XYZ 98 361 null ] +>> +endobj +538 0 obj +<< +/D [ 110 0 R /XYZ 206 616 null ] +>> +endobj +539 0 obj +<< +/D [ 110 0 R /XYZ 355 616 null ] +>> +endobj +540 0 obj +<< +/D [ 110 0 R /XYZ 206 597 null ] +>> +endobj +541 0 obj +<< +/D [ 110 0 R /XYZ 355 597 null ] +>> +endobj +542 0 obj +<< +/D [ 110 0 R /XYZ 206 578 null ] +>> +endobj +543 0 obj +<< +/D [ 110 0 R /XYZ 355 578 null ] +>> +endobj +544 0 obj +<< +/D [ 110 0 R /XYZ 206 559 null ] +>> +endobj +545 0 obj +<< +/D [ 110 0 R /XYZ 355 559 null ] +>> +endobj +546 0 obj +<< +/D [ 110 0 R /XYZ 206 540 null ] +>> +endobj +547 0 obj +<< +/D [ 110 0 R /XYZ 355 540 null ] +>> +endobj +548 0 obj +<< +/D [ 110 0 R /XYZ 206 521 null ] +>> +endobj +549 0 obj +<< +/D [ 110 0 R /XYZ 355 521 null ] +>> +endobj +550 0 obj +<< +/D [ 110 0 R /XYZ 206 502 null ] +>> +endobj +551 0 obj +<< +/D [ 110 0 R /XYZ 355 502 null ] +>> +endobj +552 0 obj +<< +/D [ 110 0 R /XYZ 206 483 null ] +>> +endobj +553 0 obj +<< +/D [ 110 0 R /XYZ 355 483 null ] +>> +endobj +554 0 obj +<< +/D [ 110 0 R /XYZ 206 464 null ] +>> +endobj +555 0 obj +<< +/D [ 110 0 R /XYZ 355 464 null ] +>> +endobj +556 0 obj +<< +/D [ 110 0 R /XYZ 206 445 null ] +>> +endobj +557 0 obj +<< +/D [ 110 0 R /XYZ 355 445 null ] +>> +endobj +558 0 obj +<< +/D [ 110 0 R /XYZ 206 426 null ] +>> +endobj +559 0 obj +<< +/D [ 110 0 R /XYZ 355 426 null ] +>> +endobj +560 0 obj +<< +/D [ 110 0 R /XYZ 206 407 null ] +>> +endobj +561 0 obj +<< +/D [ 110 0 R /XYZ 355 407 null ] +>> +endobj +562 0 obj +<< +/D [ 110 0 R /XYZ 206 388 null ] +>> +endobj +563 0 obj +<< +/D [ 110 0 R /XYZ 355 388 null ] +>> +endobj +564 0 obj +<< +/D [ 114 0 R /XYZ null null null ] +>> +endobj +565 0 obj +<< +/D [ 114 0 R /XYZ 513 701 null ] +>> +endobj +566 0 obj +<< +/D [ 114 0 R /XYZ 513 701 null ] +>> +endobj +567 0 obj +<< +/D [ 114 0 R /XYZ 364 506 null ] +>> +endobj +568 0 obj +<< +/D [ 114 0 R /XYZ 107 110 null ] +>> +endobj +569 0 obj +<< +/D [ 114 0 R /XYZ 464 717 null ] +>> +endobj +570 0 obj +<< +/D [ 114 0 R /XYZ 107 640 null ] +>> +endobj +571 0 obj +<< +/D [ 114 0 R /XYZ 107 581 null ] +>> +endobj +572 0 obj +<< +/D [ 114 0 R /XYZ 107 560 null ] +>> +endobj +573 0 obj +<< +/D [ 114 0 R /XYZ 107 500 null ] +>> +endobj +574 0 obj +<< +/D [ 114 0 R /XYZ 107 337 null ] +>> +endobj +575 0 obj +<< +/D [ 118 0 R /XYZ 265 632 null ] +>> +endobj +576 0 obj +<< +/D [ 118 0 R /XYZ 265 632 null ] +>> +endobj +577 0 obj +<< +/D [ 118 0 R /XYZ 98 695 null ] +>> +endobj +578 0 obj +<< +/D [ 118 0 R /XYZ 98 110 null ] +>> +endobj +579 0 obj +<< +/D [ 118 0 R /XYZ 98 665 null ] +>> +endobj +580 0 obj +<< +/D [ 118 0 R /XYZ 98 644 null ] +>> +endobj +581 0 obj +<< +/D [ 118 0 R /XYZ 98 632 null ] +>> +endobj +582 0 obj +<< +/D [ 118 0 R /XYZ 98 626 null ] +>> +endobj +583 0 obj +<< +/D [ 118 0 R /XYZ 98 594 null ] +>> +endobj +584 0 obj +<< +/D [ 118 0 R /XYZ 272 594 null ] +>> +endobj +585 0 obj +<< +/D [ 118 0 R /XYZ 330 606 null ] +>> +endobj +586 0 obj +<< +/D [ 118 0 R /XYZ 98 563 null ] +>> +endobj +587 0 obj +<< +/D [ 118 0 R /XYZ 156 575 null ] +>> +endobj +588 0 obj +<< +/D [ 118 0 R /XYZ 214 575 null ] +>> +endobj +589 0 obj +<< +/D [ 118 0 R /XYZ 272 563 null ] +>> +endobj +590 0 obj +<< +/D [ 118 0 R /XYZ 330 563 null ] +>> +endobj +591 0 obj +<< +/D [ 118 0 R /XYZ 387 575 null ] +>> +endobj +592 0 obj +<< +/D [ 118 0 R /XYZ 445 575 null ] +>> +endobj +593 0 obj +<< +/D [ 118 0 R /XYZ 98 532 null ] +>> +endobj +594 0 obj +<< +/D [ 118 0 R /XYZ 156 532 null ] +>> +endobj +595 0 obj +<< +/D [ 118 0 R /XYZ 214 532 null ] +>> +endobj +596 0 obj +<< +/D [ 118 0 R /XYZ 272 532 null ] +>> +endobj +597 0 obj +<< +/D [ 118 0 R /XYZ 330 532 null ] +>> +endobj +598 0 obj +<< +/D [ 118 0 R /XYZ 387 532 null ] +>> +endobj +599 0 obj +<< +/D [ 118 0 R /XYZ 445 532 null ] +>> +endobj +600 0 obj +<< +/D [ 118 0 R /XYZ 98 501 null ] +>> +endobj +601 0 obj +<< +/D [ 118 0 R /XYZ 156 501 null ] +>> +endobj +602 0 obj +<< +/D [ 118 0 R /XYZ 214 501 null ] +>> +endobj +603 0 obj +<< +/D [ 118 0 R /XYZ 272 501 null ] +>> +endobj +604 0 obj +<< +/D [ 118 0 R /XYZ 330 501 null ] +>> +endobj +605 0 obj +<< +/D [ 118 0 R /XYZ 387 501 null ] +>> +endobj +606 0 obj +<< +/D [ 118 0 R /XYZ 445 501 null ] +>> +endobj +607 0 obj +<< +/D [ 118 0 R /XYZ 98 470 null ] +>> +endobj +608 0 obj +<< +/D [ 118 0 R /XYZ 156 470 null ] +>> +endobj +609 0 obj +<< +/D [ 118 0 R /XYZ 214 470 null ] +>> +endobj +610 0 obj +<< +/D [ 118 0 R /XYZ 272 470 null ] +>> +endobj +611 0 obj +<< +/D [ 118 0 R /XYZ 330 470 null ] +>> +endobj +612 0 obj +<< +/D [ 118 0 R /XYZ 387 470 null ] +>> +endobj +613 0 obj +<< +/D [ 118 0 R /XYZ 445 470 null ] +>> +endobj +614 0 obj +<< +/D [ 118 0 R /XYZ 98 451 null ] +>> +endobj +615 0 obj +<< +/D [ 118 0 R /XYZ 156 451 null ] +>> +endobj +616 0 obj +<< +/D [ 118 0 R /XYZ 214 451 null ] +>> +endobj +617 0 obj +<< +/D [ 118 0 R /XYZ 272 451 null ] +>> +endobj +618 0 obj +<< +/D [ 118 0 R /XYZ 330 451 null ] +>> +endobj +619 0 obj +<< +/D [ 118 0 R /XYZ 387 451 null ] +>> +endobj +620 0 obj +<< +/D [ 118 0 R /XYZ 445 451 null ] +>> +endobj +621 0 obj +<< +/D [ 118 0 R /XYZ 98 432 null ] +>> +endobj +622 0 obj +<< +/D [ 118 0 R /XYZ 156 432 null ] +>> +endobj +623 0 obj +<< +/D [ 118 0 R /XYZ 214 432 null ] +>> +endobj +624 0 obj +<< +/D [ 118 0 R /XYZ 272 432 null ] +>> +endobj +625 0 obj +<< +/D [ 118 0 R /XYZ 330 432 null ] +>> +endobj +626 0 obj +<< +/D [ 118 0 R /XYZ 387 432 null ] +>> +endobj +627 0 obj +<< +/D [ 118 0 R /XYZ 445 432 null ] +>> +endobj +628 0 obj +<< +/D [ 118 0 R /XYZ 98 413 null ] +>> +endobj +629 0 obj +<< +/D [ 118 0 R /XYZ 156 413 null ] +>> +endobj +630 0 obj +<< +/D [ 118 0 R /XYZ 214 413 null ] +>> +endobj +631 0 obj +<< +/D [ 118 0 R /XYZ 272 413 null ] +>> +endobj +632 0 obj +<< +/D [ 118 0 R /XYZ 330 413 null ] +>> +endobj +633 0 obj +<< +/D [ 118 0 R /XYZ 387 413 null ] +>> +endobj +634 0 obj +<< +/D [ 118 0 R /XYZ 445 413 null ] +>> +endobj +635 0 obj +<< +/D [ 118 0 R /XYZ 98 394 null ] +>> +endobj +636 0 obj +<< +/D [ 118 0 R /XYZ 156 394 null ] +>> +endobj +637 0 obj +<< +/D [ 118 0 R /XYZ 214 394 null ] +>> +endobj +638 0 obj +<< +/D [ 118 0 R /XYZ 272 394 null ] +>> +endobj +639 0 obj +<< +/D [ 118 0 R /XYZ 330 394 null ] +>> +endobj +640 0 obj +<< +/D [ 118 0 R /XYZ 387 394 null ] +>> +endobj +641 0 obj +<< +/D [ 118 0 R /XYZ 445 394 null ] +>> +endobj +642 0 obj +<< +/D [ 118 0 R /XYZ 98 375 null ] +>> +endobj +643 0 obj +<< +/D [ 118 0 R /XYZ 156 375 null ] +>> +endobj +644 0 obj +<< +/D [ 118 0 R /XYZ 214 375 null ] +>> +endobj +645 0 obj +<< +/D [ 118 0 R /XYZ 272 375 null ] +>> +endobj +646 0 obj +<< +/D [ 118 0 R /XYZ 330 375 null ] +>> +endobj +647 0 obj +<< +/D [ 118 0 R /XYZ 387 375 null ] +>> +endobj +648 0 obj +<< +/D [ 118 0 R /XYZ 445 375 null ] +>> +endobj +649 0 obj +<< +/D [ 118 0 R /XYZ 98 356 null ] +>> +endobj +650 0 obj +<< +/D [ 118 0 R /XYZ 156 356 null ] +>> +endobj +651 0 obj +<< +/D [ 118 0 R /XYZ 214 356 null ] +>> +endobj +652 0 obj +<< +/D [ 118 0 R /XYZ 272 356 null ] +>> +endobj +653 0 obj +<< +/D [ 118 0 R /XYZ 330 356 null ] +>> +endobj +654 0 obj +<< +/D [ 118 0 R /XYZ 387 356 null ] +>> +endobj +655 0 obj +<< +/D [ 118 0 R /XYZ 445 356 null ] +>> +endobj +656 0 obj +<< +/D [ 118 0 R /XYZ 98 337 null ] +>> +endobj +657 0 obj +<< +/D [ 118 0 R /XYZ 156 337 null ] +>> +endobj +658 0 obj +<< +/D [ 118 0 R /XYZ 214 337 null ] +>> +endobj +659 0 obj +<< +/D [ 118 0 R /XYZ 272 337 null ] +>> +endobj +660 0 obj +<< +/D [ 118 0 R /XYZ 330 337 null ] +>> +endobj +661 0 obj +<< +/D [ 118 0 R /XYZ 387 337 null ] +>> +endobj +662 0 obj +<< +/D [ 118 0 R /XYZ 445 337 null ] +>> +endobj +663 0 obj +<< +/D [ 118 0 R /XYZ 98 318 null ] +>> +endobj +664 0 obj +<< +/D [ 118 0 R /XYZ 156 318 null ] +>> +endobj +665 0 obj +<< +/D [ 118 0 R /XYZ 214 318 null ] +>> +endobj +666 0 obj +<< +/D [ 118 0 R /XYZ 272 318 null ] +>> +endobj +667 0 obj +<< +/D [ 118 0 R /XYZ 330 318 null ] +>> +endobj +668 0 obj +<< +/D [ 118 0 R /XYZ 387 318 null ] +>> +endobj +669 0 obj +<< +/D [ 118 0 R /XYZ 445 318 null ] +>> +endobj +670 0 obj +<< +/D [ 118 0 R /XYZ 98 299 null ] +>> +endobj +671 0 obj +<< +/D [ 118 0 R /XYZ 156 299 null ] +>> +endobj +672 0 obj +<< +/D [ 118 0 R /XYZ 214 299 null ] +>> +endobj +673 0 obj +<< +/D [ 118 0 R /XYZ 272 299 null ] +>> +endobj +674 0 obj +<< +/D [ 118 0 R /XYZ 330 299 null ] +>> +endobj +675 0 obj +<< +/D [ 118 0 R /XYZ 387 299 null ] +>> +endobj +676 0 obj +<< +/D [ 118 0 R /XYZ 445 299 null ] +>> +endobj +677 0 obj +<< +/D [ 118 0 R /XYZ 98 280 null ] +>> +endobj +678 0 obj +<< +/D [ 118 0 R /XYZ 156 280 null ] +>> +endobj +679 0 obj +<< +/D [ 118 0 R /XYZ 214 280 null ] +>> +endobj +680 0 obj +<< +/D [ 118 0 R /XYZ 272 280 null ] +>> +endobj +681 0 obj +<< +/D [ 118 0 R /XYZ 330 280 null ] +>> +endobj +682 0 obj +<< +/D [ 118 0 R /XYZ 387 280 null ] +>> +endobj +683 0 obj +<< +/D [ 118 0 R /XYZ 445 280 null ] +>> +endobj +684 0 obj +<< +/D [ 118 0 R /XYZ 98 261 null ] +>> +endobj +685 0 obj +<< +/D [ 118 0 R /XYZ 156 261 null ] +>> +endobj +686 0 obj +<< +/D [ 118 0 R /XYZ 214 261 null ] +>> +endobj +687 0 obj +<< +/D [ 118 0 R /XYZ 272 261 null ] +>> +endobj +688 0 obj +<< +/D [ 118 0 R /XYZ 330 261 null ] +>> +endobj +689 0 obj +<< +/D [ 118 0 R /XYZ 387 261 null ] +>> +endobj +690 0 obj +<< +/D [ 118 0 R /XYZ 445 261 null ] +>> +endobj +691 0 obj +<< +/D [ 118 0 R /XYZ 98 242 null ] +>> +endobj +692 0 obj +<< +/D [ 118 0 R /XYZ 156 242 null ] +>> +endobj +693 0 obj +<< +/D [ 118 0 R /XYZ 214 242 null ] +>> +endobj +694 0 obj +<< +/D [ 118 0 R /XYZ 272 242 null ] +>> +endobj +695 0 obj +<< +/D [ 118 0 R /XYZ 330 242 null ] +>> +endobj +696 0 obj +<< +/D [ 118 0 R /XYZ 387 242 null ] +>> +endobj +697 0 obj +<< +/D [ 118 0 R /XYZ 445 242 null ] +>> +endobj +698 0 obj +<< +/D [ 118 0 R /XYZ 98 223 null ] +>> +endobj +699 0 obj +<< +/D [ 118 0 R /XYZ 156 223 null ] +>> +endobj +700 0 obj +<< +/D [ 118 0 R /XYZ 214 223 null ] +>> +endobj +701 0 obj +<< +/D [ 118 0 R /XYZ 272 223 null ] +>> +endobj +702 0 obj +<< +/D [ 118 0 R /XYZ 330 223 null ] +>> +endobj +703 0 obj +<< +/D [ 118 0 R /XYZ 387 223 null ] +>> +endobj +704 0 obj +<< +/D [ 118 0 R /XYZ 445 223 null ] +>> +endobj +705 0 obj +<< +/D [ 118 0 R /XYZ 98 204 null ] +>> +endobj +706 0 obj +<< +/D [ 118 0 R /XYZ 156 204 null ] +>> +endobj +707 0 obj +<< +/D [ 118 0 R /XYZ 214 204 null ] +>> +endobj +708 0 obj +<< +/D [ 118 0 R /XYZ 272 204 null ] +>> +endobj +709 0 obj +<< +/D [ 118 0 R /XYZ 330 204 null ] +>> +endobj +710 0 obj +<< +/D [ 118 0 R /XYZ 387 204 null ] +>> +endobj +711 0 obj +<< +/D [ 118 0 R /XYZ 445 204 null ] +>> +endobj +712 0 obj +<< +/D [ 118 0 R /XYZ 98 185 null ] +>> +endobj +713 0 obj +<< +/D [ 118 0 R /XYZ 156 185 null ] +>> +endobj +714 0 obj +<< +/D [ 118 0 R /XYZ 214 185 null ] +>> +endobj +715 0 obj +<< +/D [ 118 0 R /XYZ 272 185 null ] +>> +endobj +716 0 obj +<< +/D [ 118 0 R /XYZ 330 185 null ] +>> +endobj +717 0 obj +<< +/D [ 118 0 R /XYZ 387 185 null ] +>> +endobj +718 0 obj +<< +/D [ 118 0 R /XYZ 445 185 null ] +>> +endobj +719 0 obj +<< +/D [ 118 0 R /XYZ 98 166 null ] +>> +endobj +720 0 obj +<< +/D [ 118 0 R /XYZ 156 166 null ] +>> +endobj +721 0 obj +<< +/D [ 118 0 R /XYZ 214 166 null ] +>> +endobj +722 0 obj +<< +/D [ 118 0 R /XYZ 272 166 null ] +>> +endobj +723 0 obj +<< +/D [ 118 0 R /XYZ 330 166 null ] +>> +endobj +724 0 obj +<< +/D [ 118 0 R /XYZ 387 166 null ] +>> +endobj +725 0 obj +<< +/D [ 118 0 R /XYZ 445 166 null ] +>> +endobj +726 0 obj +<< +/D [ 118 0 R /XYZ 98 147 null ] +>> +endobj +727 0 obj +<< +/D [ 118 0 R /XYZ 156 147 null ] +>> +endobj +728 0 obj +<< +/D [ 118 0 R /XYZ 214 147 null ] +>> +endobj +729 0 obj +<< +/D [ 118 0 R /XYZ 272 147 null ] +>> +endobj +730 0 obj +<< +/D [ 118 0 R /XYZ 330 147 null ] +>> +endobj +731 0 obj +<< +/D [ 118 0 R /XYZ 387 147 null ] +>> +endobj +732 0 obj +<< +/D [ 118 0 R /XYZ 445 147 null ] +>> +endobj +733 0 obj +<< +/D [ 122 0 R /XYZ 107 695 null ] +>> +endobj +734 0 obj +<< +/D [ 122 0 R /XYZ 107 110 null ] +>> +endobj +735 0 obj +<< +/D [ 122 0 R /XYZ 107 398 null ] +>> +endobj +736 0 obj +<< +/D [ 122 0 R /XYZ 107 377 null ] +>> +endobj +737 0 obj +<< +/D [ 122 0 R /XYZ 107 279 null ] +>> +endobj +738 0 obj +<< +/D [ 122 0 R /XYZ 107 229 null ] +>> +endobj +739 0 obj +<< +/D [ 122 0 R /XYZ 107 561 null ] +>> +endobj +740 0 obj +<< +/D [ 122 0 R /XYZ 165 561 null ] +>> +endobj +741 0 obj +<< +/D [ 122 0 R /XYZ 223 561 null ] +>> +endobj +742 0 obj +<< +/D [ 122 0 R /XYZ 281 561 null ] +>> +endobj +743 0 obj +<< +/D [ 122 0 R /XYZ 339 561 null ] +>> +endobj +744 0 obj +<< +/D [ 122 0 R /XYZ 396 561 null ] +>> +endobj +745 0 obj +<< +/D [ 122 0 R /XYZ 454 561 null ] +>> +endobj +746 0 obj +<< +/D [ 122 0 R /XYZ 107 542 null ] +>> +endobj +747 0 obj +<< +/D [ 122 0 R /XYZ 165 542 null ] +>> +endobj +748 0 obj +<< +/D [ 122 0 R /XYZ 223 542 null ] +>> +endobj +749 0 obj +<< +/D [ 122 0 R /XYZ 281 542 null ] +>> +endobj +750 0 obj +<< +/D [ 122 0 R /XYZ 339 542 null ] +>> +endobj +751 0 obj +<< +/D [ 122 0 R /XYZ 396 542 null ] +>> +endobj +752 0 obj +<< +/D [ 122 0 R /XYZ 454 542 null ] +>> +endobj +753 0 obj +<< +/D [ 122 0 R /XYZ 107 523 null ] +>> +endobj +754 0 obj +<< +/D [ 122 0 R /XYZ 165 523 null ] +>> +endobj +755 0 obj +<< +/D [ 122 0 R /XYZ 223 523 null ] +>> +endobj +756 0 obj +<< +/D [ 122 0 R /XYZ 281 523 null ] +>> +endobj +757 0 obj +<< +/D [ 122 0 R /XYZ 339 523 null ] +>> +endobj +758 0 obj +<< +/D [ 122 0 R /XYZ 396 523 null ] +>> +endobj +759 0 obj +<< +/D [ 122 0 R /XYZ 454 523 null ] +>> +endobj +760 0 obj +<< +/D [ 122 0 R /XYZ 107 504 null ] +>> +endobj +761 0 obj +<< +/D [ 122 0 R /XYZ 165 504 null ] +>> +endobj +762 0 obj +<< +/D [ 122 0 R /XYZ 223 504 null ] +>> +endobj +763 0 obj +<< +/D [ 122 0 R /XYZ 281 504 null ] +>> +endobj +764 0 obj +<< +/D [ 122 0 R /XYZ 339 504 null ] +>> +endobj +765 0 obj +<< +/D [ 122 0 R /XYZ 396 504 null ] +>> +endobj +766 0 obj +<< +/D [ 122 0 R /XYZ 454 504 null ] +>> +endobj +767 0 obj +<< +/D [ 122 0 R /XYZ 107 485 null ] +>> +endobj +768 0 obj +<< +/D [ 122 0 R /XYZ 165 485 null ] +>> +endobj +769 0 obj +<< +/D [ 122 0 R /XYZ 223 485 null ] +>> +endobj +770 0 obj +<< +/D [ 122 0 R /XYZ 281 485 null ] +>> +endobj +771 0 obj +<< +/D [ 122 0 R /XYZ 339 485 null ] +>> +endobj +772 0 obj +<< +/D [ 122 0 R /XYZ 396 485 null ] +>> +endobj +773 0 obj +<< +/D [ 122 0 R /XYZ 454 485 null ] +>> +endobj +774 0 obj +<< +/D [ 122 0 R /XYZ 107 466 null ] +>> +endobj +775 0 obj +<< +/D [ 122 0 R /XYZ 165 466 null ] +>> +endobj +776 0 obj +<< +/D [ 122 0 R /XYZ 223 466 null ] +>> +endobj +777 0 obj +<< +/D [ 122 0 R /XYZ 281 466 null ] +>> +endobj +778 0 obj +<< +/D [ 122 0 R /XYZ 339 466 null ] +>> +endobj +779 0 obj +<< +/D [ 122 0 R /XYZ 396 466 null ] +>> +endobj +780 0 obj +<< +/D [ 122 0 R /XYZ 454 466 null ] +>> +endobj +781 0 obj +<< +/D [ 122 0 R /XYZ 107 435 null ] +>> +endobj +782 0 obj +<< +/D [ 122 0 R /XYZ 165 435 null ] +>> +endobj +783 0 obj +<< +/D [ 122 0 R /XYZ 223 435 null ] +>> +endobj +784 0 obj +<< +/D [ 122 0 R /XYZ 281 435 null ] +>> +endobj +785 0 obj +<< +/D [ 122 0 R /XYZ 339 435 null ] +>> +endobj +786 0 obj +<< +/D [ 122 0 R /XYZ 396 435 null ] +>> +endobj +787 0 obj +<< +/D [ 122 0 R /XYZ 454 435 null ] +>> +endobj +788 0 obj +<< +/D [ 1721 0 R /XYZ null null null ] +>> +endobj +789 0 obj +<< +/D [ 126 0 R /XYZ null null null ] +>> +endobj +790 0 obj +<< +/D [ 126 0 R /XYZ 107 110 null ] +>> +endobj +791 0 obj +<< +/D [ 126 0 R /XYZ 464 717 null ] +>> +endobj +792 0 obj +<< +/D [ 126 0 R /XYZ 107 640 null ] +>> +endobj +793 0 obj +<< +/D [ 126 0 R /XYZ 107 579 null ] +>> +endobj +794 0 obj +<< +/D [ 126 0 R /XYZ 107 495 null ] +>> +endobj +795 0 obj +<< +/D [ 126 0 R /XYZ 107 246 null ] +>> +endobj +796 0 obj +<< +/D [ 126 0 R /XYZ 107 200 null ] +>> +endobj +797 0 obj +<< +/D [ 126 0 R /XYZ 107 185 null ] +>> +endobj +798 0 obj +<< +/D [ 126 0 R /XYZ 215 485 null ] +>> +endobj +799 0 obj +<< +/D [ 126 0 R /XYZ 215 465 null ] +>> +endobj +800 0 obj +<< +/D [ 126 0 R /XYZ 314 465 null ] +>> +endobj +801 0 obj +<< +/D [ 126 0 R /XYZ 413 465 null ] +>> +endobj +802 0 obj +<< +/D [ 126 0 R /XYZ 215 446 null ] +>> +endobj +803 0 obj +<< +/D [ 126 0 R /XYZ 314 446 null ] +>> +endobj +804 0 obj +<< +/D [ 126 0 R /XYZ 413 446 null ] +>> +endobj +805 0 obj +<< +/D [ 126 0 R /XYZ 215 427 null ] +>> +endobj +806 0 obj +<< +/D [ 126 0 R /XYZ 314 427 null ] +>> +endobj +807 0 obj +<< +/D [ 126 0 R /XYZ 413 427 null ] +>> +endobj +808 0 obj +<< +/D [ 126 0 R /XYZ 215 408 null ] +>> +endobj +809 0 obj +<< +/D [ 126 0 R /XYZ 314 408 null ] +>> +endobj +810 0 obj +<< +/D [ 126 0 R /XYZ 413 408 null ] +>> +endobj +811 0 obj +<< +/D [ 126 0 R /XYZ 215 389 null ] +>> +endobj +812 0 obj +<< +/D [ 126 0 R /XYZ 314 389 null ] +>> +endobj +813 0 obj +<< +/D [ 126 0 R /XYZ 413 389 null ] +>> +endobj +814 0 obj +<< +/D [ 126 0 R /XYZ 215 370 null ] +>> +endobj +815 0 obj +<< +/D [ 126 0 R /XYZ 314 370 null ] +>> +endobj +816 0 obj +<< +/D [ 126 0 R /XYZ 413 370 null ] +>> +endobj +817 0 obj +<< +/D [ 126 0 R /XYZ 215 351 null ] +>> +endobj +818 0 obj +<< +/D [ 126 0 R /XYZ 314 351 null ] +>> +endobj +819 0 obj +<< +/D [ 126 0 R /XYZ 413 351 null ] +>> +endobj +820 0 obj +<< +/D [ 126 0 R /XYZ 215 332 null ] +>> +endobj +821 0 obj +<< +/D [ 126 0 R /XYZ 314 332 null ] +>> +endobj +822 0 obj +<< +/D [ 126 0 R /XYZ 413 332 null ] +>> +endobj +823 0 obj +<< +/D [ 126 0 R /XYZ 215 313 null ] +>> +endobj +824 0 obj +<< +/D [ 126 0 R /XYZ 314 313 null ] +>> +endobj +825 0 obj +<< +/D [ 126 0 R /XYZ 413 313 null ] +>> +endobj +826 0 obj +<< +/D [ 126 0 R /XYZ 215 294 null ] +>> +endobj +827 0 obj +<< +/D [ 126 0 R /XYZ 314 294 null ] +>> +endobj +828 0 obj +<< +/D [ 126 0 R /XYZ 413 294 null ] +>> +endobj +829 0 obj +<< +/D [ 126 0 R /XYZ 215 275 null ] +>> +endobj +830 0 obj +<< +/D [ 126 0 R /XYZ 314 275 null ] +>> +endobj +831 0 obj +<< +/D [ 126 0 R /XYZ 413 275 null ] +>> +endobj +832 0 obj +<< +/D [ null /XYZ null null null ] +>> +endobj +833 0 obj +<< +/D [ 130 0 R /XYZ null null null ] +>> +endobj +834 0 obj +<< +/D [ 130 0 R /XYZ 107 641 null ] +>> +endobj +835 0 obj +<< +/D [ 130 0 R /XYZ 107 641 null ] +>> +endobj +836 0 obj +<< +/D [ 130 0 R /XYZ 107 110 null ] +>> +endobj +837 0 obj +<< +/D [ 130 0 R /XYZ 464 717 null ] +>> +endobj +838 0 obj +<< +/D [ 130 0 R /XYZ 107 640 null ] +>> +endobj +839 0 obj +<< +/D [ 130 0 R /XYZ 107 579 null ] +>> +endobj +840 0 obj +<< +/D [ 130 0 R /XYZ 107 497 null ] +>> +endobj +841 0 obj +<< +/D [ 130 0 R /XYZ 107 457 null ] +>> +endobj +842 0 obj +<< +/D [ 130 0 R /XYZ 107 429 null ] +>> +endobj +843 0 obj +<< +/D [ 130 0 R /XYZ 107 413 null ] +>> +endobj +844 0 obj +<< +/D [ 130 0 R /XYZ 107 397 null ] +>> +endobj +845 0 obj +<< +/D [ 134 0 R /XYZ 98 695 null ] +>> +endobj +846 0 obj +<< +/D [ 134 0 R /XYZ 98 110 null ] +>> +endobj +847 0 obj +<< +/D [ 134 0 R /XYZ 98 665 null ] +>> +endobj +848 0 obj +<< +/D [ 134 0 R /XYZ 98 628 null ] +>> +endobj +849 0 obj +<< +/D [ 134 0 R /XYZ 98 612 null ] +>> +endobj +850 0 obj +<< +/D [ 134 0 R /XYZ 98 590 null ] +>> +endobj +851 0 obj +<< +/D [ 134 0 R /XYZ 98 574 null ] +>> +endobj +852 0 obj +<< +/D [ 134 0 R /XYZ 98 539 null ] +>> +endobj +853 0 obj +<< +/D [ 134 0 R /XYZ 98 516 null ] +>> +endobj +854 0 obj +<< +/D [ 134 0 R /XYZ 98 331 null ] +>> +endobj +855 0 obj +<< +/D [ 134 0 R /XYZ 98 315 null ] +>> +endobj +856 0 obj +<< +/D [ 134 0 R /XYZ 98 299 null ] +>> +endobj +857 0 obj +<< +/D [ 134 0 R /XYZ 98 283 null ] +>> +endobj +858 0 obj +<< +/D [ 134 0 R /XYZ 98 267 null ] +>> +endobj +859 0 obj +<< +/D [ 134 0 R /XYZ 134 489 null ] +>> +endobj +860 0 obj +<< +/D [ 134 0 R /XYZ 242 489 null ] +>> +endobj +861 0 obj +<< +/D [ 134 0 R /XYZ 350 489 null ] +>> +endobj +862 0 obj +<< +/D [ 134 0 R /XYZ 134 467 null ] +>> +endobj +863 0 obj +<< +/D [ 134 0 R /XYZ 242 467 null ] +>> +endobj +864 0 obj +<< +/D [ 134 0 R /XYZ 350 467 null ] +>> +endobj +865 0 obj +<< +/D [ 134 0 R /XYZ 134 397 null ] +>> +endobj +866 0 obj +<< +/D [ 134 0 R /XYZ 242 397 null ] +>> +endobj +867 0 obj +<< +/D [ 134 0 R /XYZ 350 397 null ] +>> +endobj +868 0 obj +<< +/D [ 138 0 R /XYZ 107 695 null ] +>> +endobj +869 0 obj +<< +/D [ 138 0 R /XYZ 107 110 null ] +>> +endobj +870 0 obj +<< +/D [ 138 0 R /XYZ 107 665 null ] +>> +endobj +871 0 obj +<< +/D [ 138 0 R /XYZ 107 628 null ] +>> +endobj +872 0 obj +<< +/D [ 138 0 R /XYZ 107 612 null ] +>> +endobj +873 0 obj +<< +/D [ 138 0 R /XYZ 107 579 null ] +>> +endobj +874 0 obj +<< +/D [ 138 0 R /XYZ 107 563 null ] +>> +endobj +875 0 obj +<< +/D [ 138 0 R /XYZ 107 540 null ] +>> +endobj +876 0 obj +<< +/D [ 138 0 R /XYZ 107 524 null ] +>> +endobj +877 0 obj +<< +/D [ 138 0 R /XYZ 107 259 null ] +>> +endobj +878 0 obj +<< +/D [ 138 0 R /XYZ 107 243 null ] +>> +endobj +879 0 obj +<< +/D [ 138 0 R /XYZ 107 227 null ] +>> +endobj +880 0 obj +<< +/D [ 138 0 R /XYZ 107 211 null ] +>> +endobj +881 0 obj +<< +/D [ 138 0 R /XYZ 107 195 null ] +>> +endobj +882 0 obj +<< +/D [ 138 0 R /XYZ 143 497 null ] +>> +endobj +883 0 obj +<< +/D [ 138 0 R /XYZ 251 497 null ] +>> +endobj +884 0 obj +<< +/D [ 138 0 R /XYZ 359 497 null ] +>> +endobj +885 0 obj +<< +/D [ 138 0 R /XYZ 143 475 null ] +>> +endobj +886 0 obj +<< +/D [ 138 0 R /XYZ 251 475 null ] +>> +endobj +887 0 obj +<< +/D [ 138 0 R /XYZ 359 475 null ] +>> +endobj +888 0 obj +<< +/D [ 138 0 R /XYZ 143 441 null ] +>> +endobj +889 0 obj +<< +/D [ 138 0 R /XYZ 251 441 null ] +>> +endobj +890 0 obj +<< +/D [ 138 0 R /XYZ 359 441 null ] +>> +endobj +891 0 obj +<< +/D [ 138 0 R /XYZ 143 383 null ] +>> +endobj +892 0 obj +<< +/D [ 138 0 R /XYZ 251 383 null ] +>> +endobj +893 0 obj +<< +/D [ 138 0 R /XYZ 359 383 null ] +>> +endobj +894 0 obj +<< +/D [ 138 0 R /XYZ 143 301 null ] +>> +endobj +895 0 obj +<< +/D [ 138 0 R /XYZ 251 301 null ] +>> +endobj +896 0 obj +<< +/D [ 138 0 R /XYZ 359 301 null ] +>> +endobj +897 0 obj +<< +/D [ 142 0 R /XYZ 98 665 null ] +>> +endobj +898 0 obj +<< +/D [ 142 0 R /XYZ 98 628 null ] +>> +endobj +899 0 obj +<< +/D [ 142 0 R /XYZ 98 612 null ] +>> +endobj +900 0 obj +<< +/D [ 142 0 R /XYZ 98 579 null ] +>> +endobj +901 0 obj +<< +/D [ 142 0 R /XYZ 98 563 null ] +>> +endobj +902 0 obj +<< +/D [ 142 0 R /XYZ 98 540 null ] +>> +endobj +903 0 obj +<< +/D [ 142 0 R /XYZ 98 524 null ] +>> +endobj +904 0 obj +<< +/D [ 142 0 R /XYZ 98 283 null ] +>> +endobj +905 0 obj +<< +/D [ 142 0 R /XYZ 98 267 null ] +>> +endobj +906 0 obj +<< +/D [ 142 0 R /XYZ 98 251 null ] +>> +endobj +907 0 obj +<< +/D [ 142 0 R /XYZ 98 235 null ] +>> +endobj +908 0 obj +<< +/D [ 142 0 R /XYZ 98 219 null ] +>> +endobj +909 0 obj +<< +/D [ 142 0 R /XYZ 134 497 null ] +>> +endobj +910 0 obj +<< +/D [ 142 0 R /XYZ 242 497 null ] +>> +endobj +911 0 obj +<< +/D [ 142 0 R /XYZ 350 497 null ] +>> +endobj +912 0 obj +<< +/D [ 142 0 R /XYZ 134 475 null ] +>> +endobj +913 0 obj +<< +/D [ 142 0 R /XYZ 242 475 null ] +>> +endobj +914 0 obj +<< +/D [ 142 0 R /XYZ 350 475 null ] +>> +endobj +915 0 obj +<< +/D [ 142 0 R /XYZ 134 441 null ] +>> +endobj +916 0 obj +<< +/D [ 142 0 R /XYZ 242 441 null ] +>> +endobj +917 0 obj +<< +/D [ 142 0 R /XYZ 350 441 null ] +>> +endobj +918 0 obj +<< +/D [ 142 0 R /XYZ 134 407 null ] +>> +endobj +919 0 obj +<< +/D [ 142 0 R /XYZ 242 407 null ] +>> +endobj +920 0 obj +<< +/D [ 142 0 R /XYZ 350 407 null ] +>> +endobj +921 0 obj +<< +/D [ 142 0 R /XYZ 134 325 null ] +>> +endobj +922 0 obj +<< +/D [ 142 0 R /XYZ 242 325 null ] +>> +endobj +923 0 obj +<< +/D [ 142 0 R /XYZ 350 325 null ] +>> +endobj +924 0 obj +<< +/D [ 146 0 R /XYZ null null null ] +>> +endobj +925 0 obj +<< +/D [ 146 0 R /XYZ 107 665 null ] +>> +endobj +926 0 obj +<< +/D [ 146 0 R /XYZ 107 628 null ] +>> +endobj +927 0 obj +<< +/D [ 146 0 R /XYZ 107 612 null ] +>> +endobj +928 0 obj +<< +/D [ 146 0 R /XYZ 107 590 null ] +>> +endobj +929 0 obj +<< +/D [ 146 0 R /XYZ 107 574 null ] +>> +endobj +930 0 obj +<< +/D [ 146 0 R /XYZ 107 539 null ] +>> +endobj +931 0 obj +<< +/D [ 146 0 R /XYZ 107 523 null ] +>> +endobj +932 0 obj +<< +/D [ 146 0 R /XYZ 107 420 null ] +>> +endobj +933 0 obj +<< +/D [ 146 0 R /XYZ 107 404 null ] +>> +endobj +934 0 obj +<< +/D [ 146 0 R /XYZ 107 388 null ] +>> +endobj +935 0 obj +<< +/D [ 146 0 R /XYZ 107 372 null ] +>> +endobj +936 0 obj +<< +/D [ 146 0 R /XYZ 107 356 null ] +>> +endobj +937 0 obj +<< +/D [ 146 0 R /XYZ 143 496 null ] +>> +endobj +938 0 obj +<< +/D [ 146 0 R /XYZ 251 496 null ] +>> +endobj +939 0 obj +<< +/D [ 146 0 R /XYZ 359 496 null ] +>> +endobj +940 0 obj +<< +/D [ 146 0 R /XYZ 143 474 null ] +>> +endobj +941 0 obj +<< +/D [ 146 0 R /XYZ 251 474 null ] +>> +endobj +942 0 obj +<< +/D [ 146 0 R /XYZ 359 474 null ] +>> +endobj +943 0 obj +<< +/D [ 150 0 R /XYZ null null null ] +>> +endobj +944 0 obj +<< +/D [ 150 0 R /XYZ 98 666 null ] +>> +endobj +945 0 obj +<< +/D [ 150 0 R /XYZ 98 633 null ] +>> +endobj +946 0 obj +<< +/D [ 150 0 R /XYZ 98 621 null ] +>> +endobj +947 0 obj +<< +/D [ 150 0 R /XYZ 98 610 null ] +>> +endobj +948 0 obj +<< +/D [ 150 0 R /XYZ 98 599 null ] +>> +endobj +949 0 obj +<< +/D [ 150 0 R /XYZ 98 588 null ] +>> +endobj +950 0 obj +<< +/D [ 150 0 R /XYZ 98 577 null ] +>> +endobj +951 0 obj +<< +/D [ 150 0 R /XYZ 98 566 null ] +>> +endobj +952 0 obj +<< +/D [ 150 0 R /XYZ 98 555 null ] +>> +endobj +953 0 obj +<< +/D [ 150 0 R /XYZ 98 544 null ] +>> +endobj +954 0 obj +<< +/D [ 150 0 R /XYZ 98 533 null ] +>> +endobj +955 0 obj +<< +/D [ 150 0 R /XYZ 98 522 null ] +>> +endobj +956 0 obj +<< +/D [ 150 0 R /XYZ 98 511 null ] +>> +endobj +957 0 obj +<< +/D [ 150 0 R /XYZ 98 500 null ] +>> +endobj +958 0 obj +<< +/D [ 150 0 R /XYZ 98 489 null ] +>> +endobj +959 0 obj +<< +/D [ 150 0 R /XYZ 98 478 null ] +>> +endobj +960 0 obj +<< +/D [ 150 0 R /XYZ 98 467 null ] +>> +endobj +961 0 obj +<< +/D [ 150 0 R /XYZ 98 456 null ] +>> +endobj +962 0 obj +<< +/D [ 150 0 R /XYZ 98 445 null ] +>> +endobj +963 0 obj +<< +/D [ 150 0 R /XYZ 98 434 null ] +>> +endobj +964 0 obj +<< +/D [ 150 0 R /XYZ 98 423 null ] +>> +endobj +965 0 obj +<< +/D [ 150 0 R /XYZ 98 412 null ] +>> +endobj +966 0 obj +<< +/D [ 150 0 R /XYZ 98 401 null ] +>> +endobj +967 0 obj +<< +/D [ 150 0 R /XYZ 98 390 null ] +>> +endobj +968 0 obj +<< +/D [ 150 0 R /XYZ 98 379 null ] +>> +endobj +969 0 obj +<< +/D [ 150 0 R /XYZ 98 368 null ] +>> +endobj +970 0 obj +<< +/D [ 150 0 R /XYZ 98 357 null ] +>> +endobj +971 0 obj +<< +/D [ 150 0 R /XYZ 98 346 null ] +>> +endobj +972 0 obj +<< +/D [ 150 0 R /XYZ 98 335 null ] +>> +endobj +973 0 obj +<< +/D [ 150 0 R /XYZ 98 324 null ] +>> +endobj +974 0 obj +<< +/D [ 150 0 R /XYZ 98 313 null ] +>> +endobj +975 0 obj +<< +/D [ 150 0 R /XYZ 98 302 null ] +>> +endobj +976 0 obj +<< +/D [ 150 0 R /XYZ 98 291 null ] +>> +endobj +977 0 obj +<< +/D [ 150 0 R /XYZ 98 280 null ] +>> +endobj +978 0 obj +<< +/D [ 150 0 R /XYZ 98 269 null ] +>> +endobj +979 0 obj +<< +/D [ 150 0 R /XYZ 98 258 null ] +>> +endobj +980 0 obj +<< +/D [ 150 0 R /XYZ 98 247 null ] +>> +endobj +981 0 obj +<< +/D [ 154 0 R /XYZ null null null ] +>> +endobj +982 0 obj +<< +/D [ 154 0 R /XYZ 107 663 null ] +>> +endobj +983 0 obj +<< +/D [ null /XYZ null null null ] +>> +endobj +984 0 obj +<< +/D [ null /XYZ null null null ] +>> +endobj +985 0 obj +<< +/D [ 158 0 R /XYZ null null null ] +>> +endobj +986 0 obj +<< +/D [ 158 0 R /XYZ 107 110 null ] +>> +endobj +987 0 obj +<< +/D [ 158 0 R /XYZ 464 717 null ] +>> +endobj +988 0 obj +<< +/D [ 158 0 R /XYZ 107 640 null ] +>> +endobj +989 0 obj +<< +/D [ 158 0 R /XYZ 107 551 null ] +>> +endobj +990 0 obj +<< +/D [ 158 0 R /XYZ 107 541 null ] +>> +endobj +991 0 obj +<< +/D [ 158 0 R /XYZ 107 521 null ] +>> +endobj +992 0 obj +<< +/D [ 158 0 R /XYZ 107 490 null ] +>> +endobj +993 0 obj +<< +/D [ 158 0 R /XYZ 165 502 null ] +>> +endobj +994 0 obj +<< +/D [ 158 0 R /XYZ 223 502 null ] +>> +endobj +995 0 obj +<< +/D [ 158 0 R /XYZ 281 502 null ] +>> +endobj +996 0 obj +<< +/D [ 158 0 R /XYZ 339 490 null ] +>> +endobj +997 0 obj +<< +/D [ 158 0 R /XYZ 396 490 null ] +>> +endobj +998 0 obj +<< +/D [ 158 0 R /XYZ 454 502 null ] +>> +endobj +999 0 obj +<< +/D [ 158 0 R /XYZ 107 471 null ] +>> +endobj +1000 0 obj +<< +/D [ 158 0 R /XYZ 165 471 null ] +>> +endobj +1001 0 obj +<< +/D [ 158 0 R /XYZ 223 471 null ] +>> +endobj +1002 0 obj +<< +/D [ 158 0 R /XYZ 281 471 null ] +>> +endobj +1003 0 obj +<< +/D [ 158 0 R /XYZ 339 471 null ] +>> +endobj +1004 0 obj +<< +/D [ 158 0 R /XYZ 396 471 null ] +>> +endobj +1005 0 obj +<< +/D [ 158 0 R /XYZ 454 471 null ] +>> +endobj +1006 0 obj +<< +/D [ 158 0 R /XYZ 107 452 null ] +>> +endobj +1007 0 obj +<< +/D [ 158 0 R /XYZ 165 452 null ] +>> +endobj +1008 0 obj +<< +/D [ 158 0 R /XYZ 223 452 null ] +>> +endobj +1009 0 obj +<< +/D [ 158 0 R /XYZ 281 452 null ] +>> +endobj +1010 0 obj +<< +/D [ 158 0 R /XYZ 339 452 null ] +>> +endobj +1011 0 obj +<< +/D [ 158 0 R /XYZ 396 452 null ] +>> +endobj +1012 0 obj +<< +/D [ 158 0 R /XYZ 454 452 null ] +>> +endobj +1013 0 obj +<< +/D [ 158 0 R /XYZ 107 433 null ] +>> +endobj +1014 0 obj +<< +/D [ 158 0 R /XYZ 165 433 null ] +>> +endobj +1015 0 obj +<< +/D [ 158 0 R /XYZ 223 433 null ] +>> +endobj +1016 0 obj +<< +/D [ 158 0 R /XYZ 281 433 null ] +>> +endobj +1017 0 obj +<< +/D [ 158 0 R /XYZ 339 433 null ] +>> +endobj +1018 0 obj +<< +/D [ 158 0 R /XYZ 396 433 null ] +>> +endobj +1019 0 obj +<< +/D [ 158 0 R /XYZ 454 433 null ] +>> +endobj +1020 0 obj +<< +/D [ 158 0 R /XYZ 107 414 null ] +>> +endobj +1021 0 obj +<< +/D [ 158 0 R /XYZ 165 414 null ] +>> +endobj +1022 0 obj +<< +/D [ 158 0 R /XYZ 223 414 null ] +>> +endobj +1023 0 obj +<< +/D [ 158 0 R /XYZ 281 414 null ] +>> +endobj +1024 0 obj +<< +/D [ 158 0 R /XYZ 339 414 null ] +>> +endobj +1025 0 obj +<< +/D [ 158 0 R /XYZ 396 414 null ] +>> +endobj +1026 0 obj +<< +/D [ 158 0 R /XYZ 454 414 null ] +>> +endobj +1027 0 obj +<< +/D [ 158 0 R /XYZ 107 395 null ] +>> +endobj +1028 0 obj +<< +/D [ 158 0 R /XYZ 165 395 null ] +>> +endobj +1029 0 obj +<< +/D [ 158 0 R /XYZ 223 395 null ] +>> +endobj +1030 0 obj +<< +/D [ 158 0 R /XYZ 281 395 null ] +>> +endobj +1031 0 obj +<< +/D [ 158 0 R /XYZ 339 395 null ] +>> +endobj +1032 0 obj +<< +/D [ 158 0 R /XYZ 396 395 null ] +>> +endobj +1033 0 obj +<< +/D [ 158 0 R /XYZ 454 395 null ] +>> +endobj +1034 0 obj +<< +/D [ 158 0 R /XYZ 107 376 null ] +>> +endobj +1035 0 obj +<< +/D [ 158 0 R /XYZ 165 376 null ] +>> +endobj +1036 0 obj +<< +/D [ 158 0 R /XYZ 223 376 null ] +>> +endobj +1037 0 obj +<< +/D [ 158 0 R /XYZ 281 376 null ] +>> +endobj +1038 0 obj +<< +/D [ 158 0 R /XYZ 339 376 null ] +>> +endobj +1039 0 obj +<< +/D [ 158 0 R /XYZ 396 376 null ] +>> +endobj +1040 0 obj +<< +/D [ 158 0 R /XYZ 454 376 null ] +>> +endobj +1041 0 obj +<< +/D [ 158 0 R /XYZ 107 357 null ] +>> +endobj +1042 0 obj +<< +/D [ 158 0 R /XYZ 165 357 null ] +>> +endobj +1043 0 obj +<< +/D [ 158 0 R /XYZ 223 357 null ] +>> +endobj +1044 0 obj +<< +/D [ 158 0 R /XYZ 281 357 null ] +>> +endobj +1045 0 obj +<< +/D [ 158 0 R /XYZ 339 357 null ] +>> +endobj +1046 0 obj +<< +/D [ 158 0 R /XYZ 396 357 null ] +>> +endobj +1047 0 obj +<< +/D [ 158 0 R /XYZ 454 357 null ] +>> +endobj +1048 0 obj +<< +/D [ 158 0 R /XYZ 107 338 null ] +>> +endobj +1049 0 obj +<< +/D [ 158 0 R /XYZ 165 338 null ] +>> +endobj +1050 0 obj +<< +/D [ 158 0 R /XYZ 223 338 null ] +>> +endobj +1051 0 obj +<< +/D [ 158 0 R /XYZ 281 338 null ] +>> +endobj +1052 0 obj +<< +/D [ 158 0 R /XYZ 339 338 null ] +>> +endobj +1053 0 obj +<< +/D [ 158 0 R /XYZ 396 338 null ] +>> +endobj +1054 0 obj +<< +/D [ 158 0 R /XYZ 454 338 null ] +>> +endobj +1055 0 obj +<< +/D [ 158 0 R /XYZ 107 319 null ] +>> +endobj +1056 0 obj +<< +/D [ 158 0 R /XYZ 165 319 null ] +>> +endobj +1057 0 obj +<< +/D [ 158 0 R /XYZ 223 319 null ] +>> +endobj +1058 0 obj +<< +/D [ 158 0 R /XYZ 281 319 null ] +>> +endobj +1059 0 obj +<< +/D [ 158 0 R /XYZ 339 319 null ] +>> +endobj +1060 0 obj +<< +/D [ 158 0 R /XYZ 396 319 null ] +>> +endobj +1061 0 obj +<< +/D [ 158 0 R /XYZ 454 319 null ] +>> +endobj +1062 0 obj +<< +/D [ 158 0 R /XYZ 107 300 null ] +>> +endobj +1063 0 obj +<< +/D [ 158 0 R /XYZ 165 300 null ] +>> +endobj +1064 0 obj +<< +/D [ 158 0 R /XYZ 223 300 null ] +>> +endobj +1065 0 obj +<< +/D [ 158 0 R /XYZ 281 300 null ] +>> +endobj +1066 0 obj +<< +/D [ 158 0 R /XYZ 339 300 null ] +>> +endobj +1067 0 obj +<< +/D [ 158 0 R /XYZ 396 300 null ] +>> +endobj +1068 0 obj +<< +/D [ 158 0 R /XYZ 454 300 null ] +>> +endobj +1069 0 obj +<< +/D [ 158 0 R /XYZ 107 281 null ] +>> +endobj +1070 0 obj +<< +/D [ 158 0 R /XYZ 165 281 null ] +>> +endobj +1071 0 obj +<< +/D [ 158 0 R /XYZ 223 281 null ] +>> +endobj +1072 0 obj +<< +/D [ 158 0 R /XYZ 281 281 null ] +>> +endobj +1073 0 obj +<< +/D [ 158 0 R /XYZ 339 281 null ] +>> +endobj +1074 0 obj +<< +/D [ 158 0 R /XYZ 396 281 null ] +>> +endobj +1075 0 obj +<< +/D [ 158 0 R /XYZ 454 281 null ] +>> +endobj +1076 0 obj +<< +/D [ 158 0 R /XYZ 107 262 null ] +>> +endobj +1077 0 obj +<< +/D [ 158 0 R /XYZ 165 262 null ] +>> +endobj +1078 0 obj +<< +/D [ 158 0 R /XYZ 223 262 null ] +>> +endobj +1079 0 obj +<< +/D [ 158 0 R /XYZ 281 262 null ] +>> +endobj +1080 0 obj +<< +/D [ 158 0 R /XYZ 339 262 null ] +>> +endobj +1081 0 obj +<< +/D [ 158 0 R /XYZ 396 262 null ] +>> +endobj +1082 0 obj +<< +/D [ 158 0 R /XYZ 454 262 null ] +>> +endobj +1083 0 obj +<< +/D [ 158 0 R /XYZ 107 243 null ] +>> +endobj +1084 0 obj +<< +/D [ 158 0 R /XYZ 165 243 null ] +>> +endobj +1085 0 obj +<< +/D [ 158 0 R /XYZ 223 243 null ] +>> +endobj +1086 0 obj +<< +/D [ 158 0 R /XYZ 281 243 null ] +>> +endobj +1087 0 obj +<< +/D [ 158 0 R /XYZ 339 243 null ] +>> +endobj +1088 0 obj +<< +/D [ 158 0 R /XYZ 396 243 null ] +>> +endobj +1089 0 obj +<< +/D [ 158 0 R /XYZ 454 243 null ] +>> +endobj +1090 0 obj +<< +/D [ 158 0 R /XYZ 107 224 null ] +>> +endobj +1091 0 obj +<< +/D [ 158 0 R /XYZ 165 224 null ] +>> +endobj +1092 0 obj +<< +/D [ 158 0 R /XYZ 223 224 null ] +>> +endobj +1093 0 obj +<< +/D [ 158 0 R /XYZ 281 224 null ] +>> +endobj +1094 0 obj +<< +/D [ 158 0 R /XYZ 339 224 null ] +>> +endobj +1095 0 obj +<< +/D [ 158 0 R /XYZ 396 224 null ] +>> +endobj +1096 0 obj +<< +/D [ 158 0 R /XYZ 454 224 null ] +>> +endobj +1097 0 obj +<< +/D [ 158 0 R /XYZ 107 205 null ] +>> +endobj +1098 0 obj +<< +/D [ 158 0 R /XYZ 165 205 null ] +>> +endobj +1099 0 obj +<< +/D [ 158 0 R /XYZ 223 205 null ] +>> +endobj +1100 0 obj +<< +/D [ 158 0 R /XYZ 281 205 null ] +>> +endobj +1101 0 obj +<< +/D [ 158 0 R /XYZ 339 205 null ] +>> +endobj +1102 0 obj +<< +/D [ 158 0 R /XYZ 396 205 null ] +>> +endobj +1103 0 obj +<< +/D [ 158 0 R /XYZ 454 205 null ] +>> +endobj +1104 0 obj +<< +/D [ 158 0 R /XYZ 107 186 null ] +>> +endobj +1105 0 obj +<< +/D [ 158 0 R /XYZ 165 186 null ] +>> +endobj +1106 0 obj +<< +/D [ 158 0 R /XYZ 223 186 null ] +>> +endobj +1107 0 obj +<< +/D [ 158 0 R /XYZ 281 186 null ] +>> +endobj +1108 0 obj +<< +/D [ 158 0 R /XYZ 339 186 null ] +>> +endobj +1109 0 obj +<< +/D [ 158 0 R /XYZ 396 186 null ] +>> +endobj +1110 0 obj +<< +/D [ 158 0 R /XYZ 454 186 null ] +>> +endobj +1111 0 obj +<< +/D [ 158 0 R /XYZ 107 167 null ] +>> +endobj +1112 0 obj +<< +/D [ 158 0 R /XYZ 165 167 null ] +>> +endobj +1113 0 obj +<< +/D [ 158 0 R /XYZ 223 167 null ] +>> +endobj +1114 0 obj +<< +/D [ 158 0 R /XYZ 281 167 null ] +>> +endobj +1115 0 obj +<< +/D [ 158 0 R /XYZ 339 167 null ] +>> +endobj +1116 0 obj +<< +/D [ 158 0 R /XYZ 396 167 null ] +>> +endobj +1117 0 obj +<< +/D [ 158 0 R /XYZ 454 167 null ] +>> +endobj +1118 0 obj +<< +/D [ 158 0 R /XYZ 107 148 null ] +>> +endobj +1119 0 obj +<< +/D [ 158 0 R /XYZ 165 148 null ] +>> +endobj +1120 0 obj +<< +/D [ 158 0 R /XYZ 223 148 null ] +>> +endobj +1121 0 obj +<< +/D [ 158 0 R /XYZ 281 148 null ] +>> +endobj +1122 0 obj +<< +/D [ 158 0 R /XYZ 339 148 null ] +>> +endobj +1123 0 obj +<< +/D [ 158 0 R /XYZ 396 148 null ] +>> +endobj +1124 0 obj +<< +/D [ 158 0 R /XYZ 454 148 null ] +>> +endobj +1125 0 obj +<< +/D [ 162 0 R /XYZ 98 695 null ] +>> +endobj +1126 0 obj +<< +/D [ 162 0 R /XYZ 98 110 null ] +>> +endobj +1127 0 obj +<< +/D [ 162 0 R /XYZ 98 454 null ] +>> +endobj +1128 0 obj +<< +/D [ 162 0 R /XYZ 98 593 null ] +>> +endobj +1129 0 obj +<< +/D [ 162 0 R /XYZ 156 593 null ] +>> +endobj +1130 0 obj +<< +/D [ 162 0 R /XYZ 214 593 null ] +>> +endobj +1131 0 obj +<< +/D [ 162 0 R /XYZ 272 593 null ] +>> +endobj +1132 0 obj +<< +/D [ 162 0 R /XYZ 330 593 null ] +>> +endobj +1133 0 obj +<< +/D [ 162 0 R /XYZ 387 593 null ] +>> +endobj +1134 0 obj +<< +/D [ 162 0 R /XYZ 445 593 null ] +>> +endobj +1135 0 obj +<< +/D [ 162 0 R /XYZ 98 574 null ] +>> +endobj +1136 0 obj +<< +/D [ 162 0 R /XYZ 156 574 null ] +>> +endobj +1137 0 obj +<< +/D [ 162 0 R /XYZ 214 574 null ] +>> +endobj +1138 0 obj +<< +/D [ 162 0 R /XYZ 272 574 null ] +>> +endobj +1139 0 obj +<< +/D [ 162 0 R /XYZ 330 574 null ] +>> +endobj +1140 0 obj +<< +/D [ 162 0 R /XYZ 387 574 null ] +>> +endobj +1141 0 obj +<< +/D [ 162 0 R /XYZ 445 574 null ] +>> +endobj +1142 0 obj +<< +/D [ 162 0 R /XYZ 98 555 null ] +>> +endobj +1143 0 obj +<< +/D [ 162 0 R /XYZ 156 555 null ] +>> +endobj +1144 0 obj +<< +/D [ 162 0 R /XYZ 214 555 null ] +>> +endobj +1145 0 obj +<< +/D [ 162 0 R /XYZ 272 555 null ] +>> +endobj +1146 0 obj +<< +/D [ 162 0 R /XYZ 330 555 null ] +>> +endobj +1147 0 obj +<< +/D [ 162 0 R /XYZ 387 555 null ] +>> +endobj +1148 0 obj +<< +/D [ 162 0 R /XYZ 445 555 null ] +>> +endobj +1149 0 obj +<< +/D [ 162 0 R /XYZ 98 536 null ] +>> +endobj +1150 0 obj +<< +/D [ 162 0 R /XYZ 156 536 null ] +>> +endobj +1151 0 obj +<< +/D [ 162 0 R /XYZ 214 536 null ] +>> +endobj +1152 0 obj +<< +/D [ 162 0 R /XYZ 272 536 null ] +>> +endobj +1153 0 obj +<< +/D [ 162 0 R /XYZ 330 536 null ] +>> +endobj +1154 0 obj +<< +/D [ 162 0 R /XYZ 387 536 null ] +>> +endobj +1155 0 obj +<< +/D [ 162 0 R /XYZ 445 536 null ] +>> +endobj +1156 0 obj +<< +/D [ 162 0 R /XYZ 98 517 null ] +>> +endobj +1157 0 obj +<< +/D [ 162 0 R /XYZ 156 517 null ] +>> +endobj +1158 0 obj +<< +/D [ 162 0 R /XYZ 214 517 null ] +>> +endobj +1159 0 obj +<< +/D [ 162 0 R /XYZ 272 517 null ] +>> +endobj +1160 0 obj +<< +/D [ 162 0 R /XYZ 330 517 null ] +>> +endobj +1161 0 obj +<< +/D [ 162 0 R /XYZ 387 517 null ] +>> +endobj +1162 0 obj +<< +/D [ 162 0 R /XYZ 445 517 null ] +>> +endobj +1163 0 obj +<< +/D [ 162 0 R /XYZ 98 498 null ] +>> +endobj +1164 0 obj +<< +/D [ 162 0 R /XYZ 156 498 null ] +>> +endobj +1165 0 obj +<< +/D [ 162 0 R /XYZ 214 498 null ] +>> +endobj +1166 0 obj +<< +/D [ 162 0 R /XYZ 272 498 null ] +>> +endobj +1167 0 obj +<< +/D [ 162 0 R /XYZ 330 498 null ] +>> +endobj +1168 0 obj +<< +/D [ 162 0 R /XYZ 387 498 null ] +>> +endobj +1169 0 obj +<< +/D [ 162 0 R /XYZ 445 498 null ] +>> +endobj +1170 0 obj +<< +/D [ 162 0 R /XYZ 98 479 null ] +>> +endobj +1171 0 obj +<< +/D [ 162 0 R /XYZ 118 444 null ] +>> +endobj +1172 0 obj +<< +/D [ 162 0 R /XYZ 118 424 null ] +>> +endobj +1173 0 obj +<< +/D [ 162 0 R /XYZ 118 405 null ] +>> +endobj +1174 0 obj +<< +/D [ 162 0 R /XYZ 176 405 null ] +>> +endobj +1175 0 obj +<< +/D [ 162 0 R /XYZ 233 405 null ] +>> +endobj +1176 0 obj +<< +/D [ 162 0 R /XYZ 304 405 null ] +>> +endobj +1177 0 obj +<< +/D [ 162 0 R /XYZ 371 405 null ] +>> +endobj +1178 0 obj +<< +/D [ 162 0 R /XYZ 437 405 null ] +>> +endobj +1179 0 obj +<< +/D [ 162 0 R /XYZ 118 386 null ] +>> +endobj +1180 0 obj +<< +/D [ 162 0 R /XYZ 176 386 null ] +>> +endobj +1181 0 obj +<< +/D [ 162 0 R /XYZ 233 386 null ] +>> +endobj +1182 0 obj +<< +/D [ 162 0 R /XYZ 304 386 null ] +>> +endobj +1183 0 obj +<< +/D [ 162 0 R /XYZ 371 386 null ] +>> +endobj +1184 0 obj +<< +/D [ 162 0 R /XYZ 437 386 null ] +>> +endobj +1185 0 obj +<< +/D [ 162 0 R /XYZ 118 367 null ] +>> +endobj +1186 0 obj +<< +/D [ 162 0 R /XYZ 176 367 null ] +>> +endobj +1187 0 obj +<< +/D [ 162 0 R /XYZ 233 367 null ] +>> +endobj +1188 0 obj +<< +/D [ 162 0 R /XYZ 304 367 null ] +>> +endobj +1189 0 obj +<< +/D [ 162 0 R /XYZ 371 367 null ] +>> +endobj +1190 0 obj +<< +/D [ 162 0 R /XYZ 437 367 null ] +>> +endobj +1191 0 obj +<< +/D [ 162 0 R /XYZ 118 348 null ] +>> +endobj +1192 0 obj +<< +/D [ 162 0 R /XYZ 176 348 null ] +>> +endobj +1193 0 obj +<< +/D [ 162 0 R /XYZ 233 348 null ] +>> +endobj +1194 0 obj +<< +/D [ 162 0 R /XYZ 304 348 null ] +>> +endobj +1195 0 obj +<< +/D [ 162 0 R /XYZ 371 348 null ] +>> +endobj +1196 0 obj +<< +/D [ 162 0 R /XYZ 437 348 null ] +>> +endobj +1197 0 obj +<< +/D [ 162 0 R /XYZ 118 329 null ] +>> +endobj +1198 0 obj +<< +/D [ 162 0 R /XYZ 176 329 null ] +>> +endobj +1199 0 obj +<< +/D [ 162 0 R /XYZ 233 329 null ] +>> +endobj +1200 0 obj +<< +/D [ 162 0 R /XYZ 304 329 null ] +>> +endobj +1201 0 obj +<< +/D [ 162 0 R /XYZ 371 329 null ] +>> +endobj +1202 0 obj +<< +/D [ 162 0 R /XYZ 437 329 null ] +>> +endobj +1203 0 obj +<< +/D [ 162 0 R /XYZ 118 310 null ] +>> +endobj +1204 0 obj +<< +/D [ 162 0 R /XYZ 176 310 null ] +>> +endobj +1205 0 obj +<< +/D [ 162 0 R /XYZ 233 310 null ] +>> +endobj +1206 0 obj +<< +/D [ 162 0 R /XYZ 304 310 null ] +>> +endobj +1207 0 obj +<< +/D [ 162 0 R /XYZ 371 310 null ] +>> +endobj +1208 0 obj +<< +/D [ 162 0 R /XYZ 437 310 null ] +>> +endobj +1209 0 obj +<< +/D [ 162 0 R /XYZ 118 291 null ] +>> +endobj +1210 0 obj +<< +/D [ 162 0 R /XYZ 176 291 null ] +>> +endobj +1211 0 obj +<< +/D [ 162 0 R /XYZ 233 291 null ] +>> +endobj +1212 0 obj +<< +/D [ 162 0 R /XYZ 304 291 null ] +>> +endobj +1213 0 obj +<< +/D [ 162 0 R /XYZ 371 291 null ] +>> +endobj +1214 0 obj +<< +/D [ 162 0 R /XYZ 437 291 null ] +>> +endobj +1215 0 obj +<< +/D [ 162 0 R /XYZ 118 272 null ] +>> +endobj +1216 0 obj +<< +/D [ 162 0 R /XYZ 176 272 null ] +>> +endobj +1217 0 obj +<< +/D [ 162 0 R /XYZ 233 272 null ] +>> +endobj +1218 0 obj +<< +/D [ 162 0 R /XYZ 304 272 null ] +>> +endobj +1219 0 obj +<< +/D [ 162 0 R /XYZ 371 272 null ] +>> +endobj +1220 0 obj +<< +/D [ 162 0 R /XYZ 437 272 null ] +>> +endobj +1221 0 obj +<< +/D [ 162 0 R /XYZ 118 253 null ] +>> +endobj +1222 0 obj +<< +/D [ 162 0 R /XYZ 176 253 null ] +>> +endobj +1223 0 obj +<< +/D [ 162 0 R /XYZ 233 253 null ] +>> +endobj +1224 0 obj +<< +/D [ 162 0 R /XYZ 304 253 null ] +>> +endobj +1225 0 obj +<< +/D [ 162 0 R /XYZ 371 253 null ] +>> +endobj +1226 0 obj +<< +/D [ 162 0 R /XYZ 437 253 null ] +>> +endobj +1227 0 obj +<< +/D [ 162 0 R /XYZ 118 234 null ] +>> +endobj +1228 0 obj +<< +/D [ 162 0 R /XYZ 176 234 null ] +>> +endobj +1229 0 obj +<< +/D [ 162 0 R /XYZ 233 234 null ] +>> +endobj +1230 0 obj +<< +/D [ 162 0 R /XYZ 304 234 null ] +>> +endobj +1231 0 obj +<< +/D [ 162 0 R /XYZ 371 234 null ] +>> +endobj +1232 0 obj +<< +/D [ 162 0 R /XYZ 437 234 null ] +>> +endobj +1233 0 obj +<< +/D [ 162 0 R /XYZ 118 215 null ] +>> +endobj +1234 0 obj +<< +/D [ 162 0 R /XYZ 176 215 null ] +>> +endobj +1235 0 obj +<< +/D [ 162 0 R /XYZ 233 215 null ] +>> +endobj +1236 0 obj +<< +/D [ 162 0 R /XYZ 304 215 null ] +>> +endobj +1237 0 obj +<< +/D [ 162 0 R /XYZ 371 215 null ] +>> +endobj +1238 0 obj +<< +/D [ 162 0 R /XYZ 437 215 null ] +>> +endobj +1239 0 obj +<< +/D [ 162 0 R /XYZ 118 196 null ] +>> +endobj +1240 0 obj +<< +/D [ 162 0 R /XYZ 176 196 null ] +>> +endobj +1241 0 obj +<< +/D [ 162 0 R /XYZ 233 196 null ] +>> +endobj +1242 0 obj +<< +/D [ 162 0 R /XYZ 304 196 null ] +>> +endobj +1243 0 obj +<< +/D [ 162 0 R /XYZ 371 196 null ] +>> +endobj +1244 0 obj +<< +/D [ 162 0 R /XYZ 437 196 null ] +>> +endobj +1245 0 obj +<< +/D [ 162 0 R /XYZ 118 177 null ] +>> +endobj +1246 0 obj +<< +/D [ 162 0 R /XYZ 176 177 null ] +>> +endobj +1247 0 obj +<< +/D [ 162 0 R /XYZ 233 177 null ] +>> +endobj +1248 0 obj +<< +/D [ 162 0 R /XYZ 304 177 null ] +>> +endobj +1249 0 obj +<< +/D [ 162 0 R /XYZ 371 177 null ] +>> +endobj +1250 0 obj +<< +/D [ 162 0 R /XYZ 437 177 null ] +>> +endobj +1251 0 obj +<< +/D [ 162 0 R /XYZ 118 158 null ] +>> +endobj +1252 0 obj +<< +/D [ 162 0 R /XYZ 176 158 null ] +>> +endobj +1253 0 obj +<< +/D [ 162 0 R /XYZ 233 158 null ] +>> +endobj +1254 0 obj +<< +/D [ 162 0 R /XYZ 304 158 null ] +>> +endobj +1255 0 obj +<< +/D [ 162 0 R /XYZ 371 158 null ] +>> +endobj +1256 0 obj +<< +/D [ 162 0 R /XYZ 437 158 null ] +>> +endobj +1257 0 obj +<< +/D [ 166 0 R /XYZ 107 695 null ] +>> +endobj +1258 0 obj +<< +/D [ 166 0 R /XYZ 107 110 null ] +>> +endobj +1259 0 obj +<< +/D [ 166 0 R /XYZ 127 605 null ] +>> +endobj +1260 0 obj +<< +/D [ 166 0 R /XYZ 185 605 null ] +>> +endobj +1261 0 obj +<< +/D [ 166 0 R /XYZ 242 605 null ] +>> +endobj +1262 0 obj +<< +/D [ 166 0 R /XYZ 313 605 null ] +>> +endobj +1263 0 obj +<< +/D [ 166 0 R /XYZ 380 605 null ] +>> +endobj +1264 0 obj +<< +/D [ 166 0 R /XYZ 446 605 null ] +>> +endobj +1265 0 obj +<< +/D [ 166 0 R /XYZ 127 586 null ] +>> +endobj +1266 0 obj +<< +/D [ 166 0 R /XYZ 185 586 null ] +>> +endobj +1267 0 obj +<< +/D [ 166 0 R /XYZ 242 586 null ] +>> +endobj +1268 0 obj +<< +/D [ 166 0 R /XYZ 313 586 null ] +>> +endobj +1269 0 obj +<< +/D [ 166 0 R /XYZ 380 586 null ] +>> +endobj +1270 0 obj +<< +/D [ 166 0 R /XYZ 446 586 null ] +>> +endobj +1271 0 obj +<< +/D [ 166 0 R /XYZ 127 567 null ] +>> +endobj +1272 0 obj +<< +/D [ 166 0 R /XYZ 185 567 null ] +>> +endobj +1273 0 obj +<< +/D [ 166 0 R /XYZ 242 567 null ] +>> +endobj +1274 0 obj +<< +/D [ 166 0 R /XYZ 313 567 null ] +>> +endobj +1275 0 obj +<< +/D [ 166 0 R /XYZ 380 567 null ] +>> +endobj +1276 0 obj +<< +/D [ 166 0 R /XYZ 446 567 null ] +>> +endobj +1277 0 obj +<< +/D [ 166 0 R /XYZ 127 548 null ] +>> +endobj +1278 0 obj +<< +/D [ 166 0 R /XYZ 185 548 null ] +>> +endobj +1279 0 obj +<< +/D [ 166 0 R /XYZ 242 548 null ] +>> +endobj +1280 0 obj +<< +/D [ 166 0 R /XYZ 313 548 null ] +>> +endobj +1281 0 obj +<< +/D [ 166 0 R /XYZ 380 548 null ] +>> +endobj +1282 0 obj +<< +/D [ 166 0 R /XYZ 446 548 null ] +>> +endobj +1283 0 obj +<< +/D [ 166 0 R /XYZ 127 529 null ] +>> +endobj +1284 0 obj +<< +/D [ 166 0 R /XYZ 185 529 null ] +>> +endobj +1285 0 obj +<< +/D [ 166 0 R /XYZ 242 529 null ] +>> +endobj +1286 0 obj +<< +/D [ 166 0 R /XYZ 313 529 null ] +>> +endobj +1287 0 obj +<< +/D [ 166 0 R /XYZ 380 529 null ] +>> +endobj +1288 0 obj +<< +/D [ 166 0 R /XYZ 446 529 null ] +>> +endobj +1289 0 obj +<< +/D [ 166 0 R /XYZ 127 510 null ] +>> +endobj +1290 0 obj +<< +/D [ 166 0 R /XYZ 185 510 null ] +>> +endobj +1291 0 obj +<< +/D [ 166 0 R /XYZ 242 510 null ] +>> +endobj +1292 0 obj +<< +/D [ 166 0 R /XYZ 313 510 null ] +>> +endobj +1293 0 obj +<< +/D [ 166 0 R /XYZ 380 510 null ] +>> +endobj +1294 0 obj +<< +/D [ 166 0 R /XYZ 446 510 null ] +>> +endobj +1295 0 obj +<< +/D [ 166 0 R /XYZ 127 491 null ] +>> +endobj +1296 0 obj +<< +/D [ 166 0 R /XYZ 185 491 null ] +>> +endobj +1297 0 obj +<< +/D [ 166 0 R /XYZ 242 491 null ] +>> +endobj +1298 0 obj +<< +/D [ 166 0 R /XYZ 313 491 null ] +>> +endobj +1299 0 obj +<< +/D [ 166 0 R /XYZ 380 491 null ] +>> +endobj +1300 0 obj +<< +/D [ 166 0 R /XYZ 446 491 null ] +>> +endobj +1301 0 obj +<< +/D [ 166 0 R /XYZ 127 472 null ] +>> +endobj +1302 0 obj +<< +/D [ 166 0 R /XYZ 185 472 null ] +>> +endobj +1303 0 obj +<< +/D [ 166 0 R /XYZ 242 472 null ] +>> +endobj +1304 0 obj +<< +/D [ 166 0 R /XYZ 313 472 null ] +>> +endobj +1305 0 obj +<< +/D [ 166 0 R /XYZ 380 472 null ] +>> +endobj +1306 0 obj +<< +/D [ 166 0 R /XYZ 446 472 null ] +>> +endobj +1307 0 obj +<< +/D [ 166 0 R /XYZ 127 453 null ] +>> +endobj +1308 0 obj +<< +/D [ 166 0 R /XYZ 185 453 null ] +>> +endobj +1309 0 obj +<< +/D [ 166 0 R /XYZ 242 453 null ] +>> +endobj +1310 0 obj +<< +/D [ 166 0 R /XYZ 313 453 null ] +>> +endobj +1311 0 obj +<< +/D [ 166 0 R /XYZ 380 453 null ] +>> +endobj +1312 0 obj +<< +/D [ 166 0 R /XYZ 446 453 null ] +>> +endobj +1313 0 obj +<< +/D [ 166 0 R /XYZ 127 434 null ] +>> +endobj +1314 0 obj +<< +/D [ 166 0 R /XYZ 185 434 null ] +>> +endobj +1315 0 obj +<< +/D [ 166 0 R /XYZ 242 434 null ] +>> +endobj +1316 0 obj +<< +/D [ 166 0 R /XYZ 313 434 null ] +>> +endobj +1317 0 obj +<< +/D [ 166 0 R /XYZ 380 434 null ] +>> +endobj +1318 0 obj +<< +/D [ 166 0 R /XYZ 446 434 null ] +>> +endobj +1319 0 obj +<< +/D [ 166 0 R /XYZ 127 415 null ] +>> +endobj +1320 0 obj +<< +/D [ 166 0 R /XYZ 185 415 null ] +>> +endobj +1321 0 obj +<< +/D [ 166 0 R /XYZ 242 415 null ] +>> +endobj +1322 0 obj +<< +/D [ 166 0 R /XYZ 313 415 null ] +>> +endobj +1323 0 obj +<< +/D [ 166 0 R /XYZ 380 415 null ] +>> +endobj +1324 0 obj +<< +/D [ 166 0 R /XYZ 446 415 null ] +>> +endobj +1325 0 obj +<< +/D [ 166 0 R /XYZ 127 396 null ] +>> +endobj +1326 0 obj +<< +/D [ 166 0 R /XYZ 185 396 null ] +>> +endobj +1327 0 obj +<< +/D [ 166 0 R /XYZ 242 396 null ] +>> +endobj +1328 0 obj +<< +/D [ 166 0 R /XYZ 313 396 null ] +>> +endobj +1329 0 obj +<< +/D [ 166 0 R /XYZ 380 396 null ] +>> +endobj +1330 0 obj +<< +/D [ 166 0 R /XYZ 446 396 null ] +>> +endobj +1331 0 obj +<< +/D [ 166 0 R /XYZ 127 377 null ] +>> +endobj +1332 0 obj +<< +/D [ 166 0 R /XYZ 185 377 null ] +>> +endobj +1333 0 obj +<< +/D [ 166 0 R /XYZ 242 377 null ] +>> +endobj +1334 0 obj +<< +/D [ 166 0 R /XYZ 313 377 null ] +>> +endobj +1335 0 obj +<< +/D [ 166 0 R /XYZ 380 377 null ] +>> +endobj +1336 0 obj +<< +/D [ 166 0 R /XYZ 446 377 null ] +>> +endobj +1337 0 obj +<< +/D [ 166 0 R /XYZ 127 358 null ] +>> +endobj +1338 0 obj +<< +/D [ 166 0 R /XYZ 185 358 null ] +>> +endobj +1339 0 obj +<< +/D [ 166 0 R /XYZ 242 358 null ] +>> +endobj +1340 0 obj +<< +/D [ 166 0 R /XYZ 313 358 null ] +>> +endobj +1341 0 obj +<< +/D [ 166 0 R /XYZ 380 358 null ] +>> +endobj +1342 0 obj +<< +/D [ 166 0 R /XYZ 446 358 null ] +>> +endobj +1343 0 obj +<< +/D [ 166 0 R /XYZ 127 339 null ] +>> +endobj +1344 0 obj +<< +/D [ 166 0 R /XYZ 185 339 null ] +>> +endobj +1345 0 obj +<< +/D [ 166 0 R /XYZ 242 339 null ] +>> +endobj +1346 0 obj +<< +/D [ 166 0 R /XYZ 313 339 null ] +>> +endobj +1347 0 obj +<< +/D [ 166 0 R /XYZ 380 339 null ] +>> +endobj +1348 0 obj +<< +/D [ 166 0 R /XYZ 446 339 null ] +>> +endobj +1349 0 obj +<< +/D [ 166 0 R /XYZ 127 320 null ] +>> +endobj +1350 0 obj +<< +/D [ 166 0 R /XYZ 185 320 null ] +>> +endobj +1351 0 obj +<< +/D [ 166 0 R /XYZ 242 320 null ] +>> +endobj +1352 0 obj +<< +/D [ 166 0 R /XYZ 313 320 null ] +>> +endobj +1353 0 obj +<< +/D [ 166 0 R /XYZ 380 320 null ] +>> +endobj +1354 0 obj +<< +/D [ 166 0 R /XYZ 446 320 null ] +>> +endobj +1355 0 obj +<< +/D [ 166 0 R /XYZ 127 301 null ] +>> +endobj +1356 0 obj +<< +/D [ 166 0 R /XYZ 185 301 null ] +>> +endobj +1357 0 obj +<< +/D [ 166 0 R /XYZ 242 301 null ] +>> +endobj +1358 0 obj +<< +/D [ 166 0 R /XYZ 313 301 null ] +>> +endobj +1359 0 obj +<< +/D [ 166 0 R /XYZ 380 301 null ] +>> +endobj +1360 0 obj +<< +/D [ 166 0 R /XYZ 446 301 null ] +>> +endobj +1361 0 obj +<< +/D [ 166 0 R /XYZ 127 282 null ] +>> +endobj +1362 0 obj +<< +/D [ 166 0 R /XYZ 185 282 null ] +>> +endobj +1363 0 obj +<< +/D [ 166 0 R /XYZ 242 282 null ] +>> +endobj +1364 0 obj +<< +/D [ 166 0 R /XYZ 313 282 null ] +>> +endobj +1365 0 obj +<< +/D [ 166 0 R /XYZ 380 282 null ] +>> +endobj +1366 0 obj +<< +/D [ 166 0 R /XYZ 446 282 null ] +>> +endobj +1367 0 obj +<< +/D [ 166 0 R /XYZ 127 263 null ] +>> +endobj +1368 0 obj +<< +/D [ 166 0 R /XYZ 185 263 null ] +>> +endobj +1369 0 obj +<< +/D [ 166 0 R /XYZ 242 263 null ] +>> +endobj +1370 0 obj +<< +/D [ 166 0 R /XYZ 313 263 null ] +>> +endobj +1371 0 obj +<< +/D [ 166 0 R /XYZ 380 263 null ] +>> +endobj +1372 0 obj +<< +/D [ 166 0 R /XYZ 446 263 null ] +>> +endobj +1373 0 obj +<< +/D [ 166 0 R /XYZ 127 244 null ] +>> +endobj +1374 0 obj +<< +/D [ 166 0 R /XYZ 185 244 null ] +>> +endobj +1375 0 obj +<< +/D [ 166 0 R /XYZ 242 244 null ] +>> +endobj +1376 0 obj +<< +/D [ 166 0 R /XYZ 313 244 null ] +>> +endobj +1377 0 obj +<< +/D [ 166 0 R /XYZ 380 244 null ] +>> +endobj +1378 0 obj +<< +/D [ 166 0 R /XYZ 446 244 null ] +>> +endobj +1379 0 obj +<< +/D [ 166 0 R /XYZ 127 225 null ] +>> +endobj +1380 0 obj +<< +/D [ 166 0 R /XYZ 185 225 null ] +>> +endobj +1381 0 obj +<< +/D [ 166 0 R /XYZ 242 225 null ] +>> +endobj +1382 0 obj +<< +/D [ 166 0 R /XYZ 313 225 null ] +>> +endobj +1383 0 obj +<< +/D [ 166 0 R /XYZ 380 225 null ] +>> +endobj +1384 0 obj +<< +/D [ 166 0 R /XYZ 446 225 null ] +>> +endobj +1385 0 obj +<< +/D [ 166 0 R /XYZ 127 206 null ] +>> +endobj +1386 0 obj +<< +/D [ 166 0 R /XYZ 185 206 null ] +>> +endobj +1387 0 obj +<< +/D [ 166 0 R /XYZ 242 206 null ] +>> +endobj +1388 0 obj +<< +/D [ 166 0 R /XYZ 313 206 null ] +>> +endobj +1389 0 obj +<< +/D [ 166 0 R /XYZ 380 206 null ] +>> +endobj +1390 0 obj +<< +/D [ 166 0 R /XYZ 446 206 null ] +>> +endobj +1391 0 obj +<< +/D [ 166 0 R /XYZ 127 187 null ] +>> +endobj +1392 0 obj +<< +/D [ 166 0 R /XYZ 185 187 null ] +>> +endobj +1393 0 obj +<< +/D [ 166 0 R /XYZ 242 187 null ] +>> +endobj +1394 0 obj +<< +/D [ 166 0 R /XYZ 313 187 null ] +>> +endobj +1395 0 obj +<< +/D [ 166 0 R /XYZ 380 187 null ] +>> +endobj +1396 0 obj +<< +/D [ 166 0 R /XYZ 446 187 null ] +>> +endobj +1397 0 obj +<< +/D [ 166 0 R /XYZ 127 168 null ] +>> +endobj +1398 0 obj +<< +/D [ 166 0 R /XYZ 185 168 null ] +>> +endobj +1399 0 obj +<< +/D [ 166 0 R /XYZ 242 168 null ] +>> +endobj +1400 0 obj +<< +/D [ 166 0 R /XYZ 313 168 null ] +>> +endobj +1401 0 obj +<< +/D [ 166 0 R /XYZ 380 168 null ] +>> +endobj +1402 0 obj +<< +/D [ 166 0 R /XYZ 446 168 null ] +>> +endobj +1403 0 obj +<< +/D [ 166 0 R /XYZ 127 149 null ] +>> +endobj +1404 0 obj +<< +/D [ 166 0 R /XYZ 185 149 null ] +>> +endobj +1405 0 obj +<< +/D [ 166 0 R /XYZ 242 149 null ] +>> +endobj +1406 0 obj +<< +/D [ 166 0 R /XYZ 313 149 null ] +>> +endobj +1407 0 obj +<< +/D [ 166 0 R /XYZ 380 149 null ] +>> +endobj +1408 0 obj +<< +/D [ 166 0 R /XYZ 446 149 null ] +>> +endobj +1409 0 obj +<< +/D [ 170 0 R /XYZ 98 407 null ] +>> +endobj +1410 0 obj +<< +/D [ 170 0 R /XYZ 118 605 null ] +>> +endobj +1411 0 obj +<< +/D [ 170 0 R /XYZ 176 605 null ] +>> +endobj +1412 0 obj +<< +/D [ 170 0 R /XYZ 233 605 null ] +>> +endobj +1413 0 obj +<< +/D [ 170 0 R /XYZ 304 605 null ] +>> +endobj +1414 0 obj +<< +/D [ 170 0 R /XYZ 371 605 null ] +>> +endobj +1415 0 obj +<< +/D [ 170 0 R /XYZ 437 605 null ] +>> +endobj +1416 0 obj +<< +/D [ 170 0 R /XYZ 118 586 null ] +>> +endobj +1417 0 obj +<< +/D [ 170 0 R /XYZ 176 586 null ] +>> +endobj +1418 0 obj +<< +/D [ 170 0 R /XYZ 233 586 null ] +>> +endobj +1419 0 obj +<< +/D [ 170 0 R /XYZ 304 586 null ] +>> +endobj +1420 0 obj +<< +/D [ 170 0 R /XYZ 371 586 null ] +>> +endobj +1421 0 obj +<< +/D [ 170 0 R /XYZ 437 586 null ] +>> +endobj +1422 0 obj +<< +/D [ 170 0 R /XYZ 118 567 null ] +>> +endobj +1423 0 obj +<< +/D [ 170 0 R /XYZ 176 567 null ] +>> +endobj +1424 0 obj +<< +/D [ 170 0 R /XYZ 233 567 null ] +>> +endobj +1425 0 obj +<< +/D [ 170 0 R /XYZ 304 567 null ] +>> +endobj +1426 0 obj +<< +/D [ 170 0 R /XYZ 371 567 null ] +>> +endobj +1427 0 obj +<< +/D [ 170 0 R /XYZ 437 567 null ] +>> +endobj +1428 0 obj +<< +/D [ 170 0 R /XYZ 118 548 null ] +>> +endobj +1429 0 obj +<< +/D [ 170 0 R /XYZ 176 548 null ] +>> +endobj +1430 0 obj +<< +/D [ 170 0 R /XYZ 233 548 null ] +>> +endobj +1431 0 obj +<< +/D [ 170 0 R /XYZ 304 548 null ] +>> +endobj +1432 0 obj +<< +/D [ 170 0 R /XYZ 371 548 null ] +>> +endobj +1433 0 obj +<< +/D [ 170 0 R /XYZ 437 548 null ] +>> +endobj +1434 0 obj +<< +/D [ 170 0 R /XYZ 118 529 null ] +>> +endobj +1435 0 obj +<< +/D [ 170 0 R /XYZ 176 529 null ] +>> +endobj +1436 0 obj +<< +/D [ 170 0 R /XYZ 233 529 null ] +>> +endobj +1437 0 obj +<< +/D [ 170 0 R /XYZ 304 529 null ] +>> +endobj +1438 0 obj +<< +/D [ 170 0 R /XYZ 371 529 null ] +>> +endobj +1439 0 obj +<< +/D [ 170 0 R /XYZ 437 529 null ] +>> +endobj +1440 0 obj +<< +/D [ 170 0 R /XYZ 118 510 null ] +>> +endobj +1441 0 obj +<< +/D [ 170 0 R /XYZ 176 510 null ] +>> +endobj +1442 0 obj +<< +/D [ 170 0 R /XYZ 233 510 null ] +>> +endobj +1443 0 obj +<< +/D [ 170 0 R /XYZ 304 510 null ] +>> +endobj +1444 0 obj +<< +/D [ 170 0 R /XYZ 371 510 null ] +>> +endobj +1445 0 obj +<< +/D [ 170 0 R /XYZ 437 510 null ] +>> +endobj +1446 0 obj +<< +/D [ 170 0 R /XYZ 118 491 null ] +>> +endobj +1447 0 obj +<< +/D [ 170 0 R /XYZ 176 491 null ] +>> +endobj +1448 0 obj +<< +/D [ 170 0 R /XYZ 233 491 null ] +>> +endobj +1449 0 obj +<< +/D [ 170 0 R /XYZ 304 491 null ] +>> +endobj +1450 0 obj +<< +/D [ 170 0 R /XYZ 371 491 null ] +>> +endobj +1451 0 obj +<< +/D [ 170 0 R /XYZ 437 491 null ] +>> +endobj +1452 0 obj +<< +/D [ 170 0 R /XYZ 118 472 null ] +>> +endobj +1453 0 obj +<< +/D [ 170 0 R /XYZ 176 472 null ] +>> +endobj +1454 0 obj +<< +/D [ 170 0 R /XYZ 233 472 null ] +>> +endobj +1455 0 obj +<< +/D [ 170 0 R /XYZ 304 472 null ] +>> +endobj +1456 0 obj +<< +/D [ 170 0 R /XYZ 371 472 null ] +>> +endobj +1457 0 obj +<< +/D [ 170 0 R /XYZ 437 472 null ] +>> +endobj +1458 0 obj +<< +/D [ 170 0 R /XYZ 118 453 null ] +>> +endobj +1459 0 obj +<< +/D [ 170 0 R /XYZ 176 453 null ] +>> +endobj +1460 0 obj +<< +/D [ 170 0 R /XYZ 233 453 null ] +>> +endobj +1461 0 obj +<< +/D [ 170 0 R /XYZ 304 453 null ] +>> +endobj +1462 0 obj +<< +/D [ 170 0 R /XYZ 371 453 null ] +>> +endobj +1463 0 obj +<< +/D [ 170 0 R /XYZ 437 453 null ] +>> +endobj +1464 0 obj +<< +/D [ 170 0 R /XYZ 118 434 null ] +>> +endobj +1465 0 obj +<< +/D [ 170 0 R /XYZ 176 434 null ] +>> +endobj +1466 0 obj +<< +/D [ 170 0 R /XYZ 233 434 null ] +>> +endobj +1467 0 obj +<< +/D [ 170 0 R /XYZ 304 434 null ] +>> +endobj +1468 0 obj +<< +/D [ 170 0 R /XYZ 371 434 null ] +>> +endobj +1469 0 obj +<< +/D [ 170 0 R /XYZ 437 434 null ] +>> +endobj +1470 0 obj +<< +/D [ 170 0 R /XYZ 206 397 null ] +>> +endobj +1471 0 obj +<< +/D [ 170 0 R /XYZ 206 376 null ] +>> +endobj +1472 0 obj +<< +/D [ 170 0 R /XYZ 206 357 null ] +>> +endobj +1473 0 obj +<< +/D [ 170 0 R /XYZ 275 357 null ] +>> +endobj +1474 0 obj +<< +/D [ 170 0 R /XYZ 344 357 null ] +>> +endobj +1475 0 obj +<< +/D [ 170 0 R /XYZ 365 357 null ] +>> +endobj +1476 0 obj +<< +/D [ 170 0 R /XYZ 434 357 null ] +>> +endobj +1477 0 obj +<< +/D [ 170 0 R /XYZ 206 338 null ] +>> +endobj +1478 0 obj +<< +/D [ 170 0 R /XYZ 275 338 null ] +>> +endobj +1479 0 obj +<< +/D [ 170 0 R /XYZ 344 338 null ] +>> +endobj +1480 0 obj +<< +/D [ 170 0 R /XYZ 365 338 null ] +>> +endobj +1481 0 obj +<< +/D [ 170 0 R /XYZ 434 338 null ] +>> +endobj +1482 0 obj +<< +/D [ 170 0 R /XYZ 206 319 null ] +>> +endobj +1483 0 obj +<< +/D [ 170 0 R /XYZ 275 319 null ] +>> +endobj +1484 0 obj +<< +/D [ 170 0 R /XYZ 344 319 null ] +>> +endobj +1485 0 obj +<< +/D [ 170 0 R /XYZ 365 319 null ] +>> +endobj +1486 0 obj +<< +/D [ 170 0 R /XYZ 434 319 null ] +>> +endobj +1487 0 obj +<< +/D [ 170 0 R /XYZ 206 300 null ] +>> +endobj +1488 0 obj +<< +/D [ 170 0 R /XYZ 275 300 null ] +>> +endobj +1489 0 obj +<< +/D [ 170 0 R /XYZ 344 300 null ] +>> +endobj +1490 0 obj +<< +/D [ 170 0 R /XYZ 365 300 null ] +>> +endobj +1491 0 obj +<< +/D [ 170 0 R /XYZ 434 300 null ] +>> +endobj +1492 0 obj +<< +/D [ 170 0 R /XYZ 206 281 null ] +>> +endobj +1493 0 obj +<< +/D [ 170 0 R /XYZ 275 281 null ] +>> +endobj +1494 0 obj +<< +/D [ 170 0 R /XYZ 344 281 null ] +>> +endobj +1495 0 obj +<< +/D [ 170 0 R /XYZ 365 281 null ] +>> +endobj +1496 0 obj +<< +/D [ 170 0 R /XYZ 434 281 null ] +>> +endobj +1497 0 obj +<< +/D [ 170 0 R /XYZ 206 262 null ] +>> +endobj +1498 0 obj +<< +/D [ 170 0 R /XYZ 275 262 null ] +>> +endobj +1499 0 obj +<< +/D [ 170 0 R /XYZ 344 262 null ] +>> +endobj +1500 0 obj +<< +/D [ 170 0 R /XYZ 365 262 null ] +>> +endobj +1501 0 obj +<< +/D [ 170 0 R /XYZ 434 262 null ] +>> +endobj +1502 0 obj +<< +/D [ 170 0 R /XYZ 206 243 null ] +>> +endobj +1503 0 obj +<< +/D [ 170 0 R /XYZ 275 243 null ] +>> +endobj +1504 0 obj +<< +/D [ 170 0 R /XYZ 344 243 null ] +>> +endobj +1505 0 obj +<< +/D [ 170 0 R /XYZ 365 243 null ] +>> +endobj +1506 0 obj +<< +/D [ 170 0 R /XYZ 434 243 null ] +>> +endobj +1507 0 obj +<< +/D [ 170 0 R /XYZ 206 224 null ] +>> +endobj +1508 0 obj +<< +/D [ 170 0 R /XYZ 275 224 null ] +>> +endobj +1509 0 obj +<< +/D [ 170 0 R /XYZ 344 224 null ] +>> +endobj +1510 0 obj +<< +/D [ 170 0 R /XYZ 365 224 null ] +>> +endobj +1511 0 obj +<< +/D [ 170 0 R /XYZ 434 224 null ] +>> +endobj +1512 0 obj +<< +/D [ 170 0 R /XYZ 206 205 null ] +>> +endobj +1513 0 obj +<< +/D [ 170 0 R /XYZ 275 205 null ] +>> +endobj +1514 0 obj +<< +/D [ 170 0 R /XYZ 344 205 null ] +>> +endobj +1515 0 obj +<< +/D [ 170 0 R /XYZ 365 205 null ] +>> +endobj +1516 0 obj +<< +/D [ 170 0 R /XYZ 434 205 null ] +>> +endobj +1517 0 obj +<< +/D [ 170 0 R /XYZ 206 186 null ] +>> +endobj +1518 0 obj +<< +/D [ 170 0 R /XYZ 275 186 null ] +>> +endobj +1519 0 obj +<< +/D [ 170 0 R /XYZ 344 186 null ] +>> +endobj +1520 0 obj +<< +/D [ 170 0 R /XYZ 365 186 null ] +>> +endobj +1521 0 obj +<< +/D [ 170 0 R /XYZ 434 186 null ] +>> +endobj +1522 0 obj +<< +/D [ 170 0 R /XYZ 206 167 null ] +>> +endobj +1523 0 obj +<< +/D [ 170 0 R /XYZ 275 167 null ] +>> +endobj +1524 0 obj +<< +/D [ 170 0 R /XYZ 344 167 null ] +>> +endobj +1525 0 obj +<< +/D [ 170 0 R /XYZ 365 167 null ] +>> +endobj +1526 0 obj +<< +/D [ 170 0 R /XYZ 434 167 null ] +>> +endobj +1527 0 obj +<< +/D [ 170 0 R /XYZ 206 148 null ] +>> +endobj +1528 0 obj +<< +/D [ 170 0 R /XYZ 275 148 null ] +>> +endobj +1529 0 obj +<< +/D [ 170 0 R /XYZ 344 148 null ] +>> +endobj +1530 0 obj +<< +/D [ 170 0 R /XYZ 365 148 null ] +>> +endobj +1531 0 obj +<< +/D [ 170 0 R /XYZ 434 148 null ] +>> +endobj +1532 0 obj +<< +/D [ 174 0 R /XYZ 107 197 null ] +>> +endobj +1533 0 obj +<< +/D [ 174 0 R /XYZ 215 604 null ] +>> +endobj +1534 0 obj +<< +/D [ 174 0 R /XYZ 284 604 null ] +>> +endobj +1535 0 obj +<< +/D [ 174 0 R /XYZ 353 604 null ] +>> +endobj +1536 0 obj +<< +/D [ 174 0 R /XYZ 374 604 null ] +>> +endobj +1537 0 obj +<< +/D [ 174 0 R /XYZ 443 604 null ] +>> +endobj +1538 0 obj +<< +/D [ 174 0 R /XYZ 215 585 null ] +>> +endobj +1539 0 obj +<< +/D [ 174 0 R /XYZ 284 585 null ] +>> +endobj +1540 0 obj +<< +/D [ 174 0 R /XYZ 353 585 null ] +>> +endobj +1541 0 obj +<< +/D [ 174 0 R /XYZ 374 585 null ] +>> +endobj +1542 0 obj +<< +/D [ 174 0 R /XYZ 443 585 null ] +>> +endobj +1543 0 obj +<< +/D [ 174 0 R /XYZ 215 566 null ] +>> +endobj +1544 0 obj +<< +/D [ 174 0 R /XYZ 284 566 null ] +>> +endobj +1545 0 obj +<< +/D [ 174 0 R /XYZ 353 566 null ] +>> +endobj +1546 0 obj +<< +/D [ 174 0 R /XYZ 374 566 null ] +>> +endobj +1547 0 obj +<< +/D [ 174 0 R /XYZ 443 566 null ] +>> +endobj +1548 0 obj +<< +/D [ 174 0 R /XYZ 215 547 null ] +>> +endobj +1549 0 obj +<< +/D [ 174 0 R /XYZ 284 547 null ] +>> +endobj +1550 0 obj +<< +/D [ 174 0 R /XYZ 353 547 null ] +>> +endobj +1551 0 obj +<< +/D [ 174 0 R /XYZ 374 547 null ] +>> +endobj +1552 0 obj +<< +/D [ 174 0 R /XYZ 443 547 null ] +>> +endobj +1553 0 obj +<< +/D [ 174 0 R /XYZ 215 528 null ] +>> +endobj +1554 0 obj +<< +/D [ 174 0 R /XYZ 284 528 null ] +>> +endobj +1555 0 obj +<< +/D [ 174 0 R /XYZ 353 528 null ] +>> +endobj +1556 0 obj +<< +/D [ 174 0 R /XYZ 374 528 null ] +>> +endobj +1557 0 obj +<< +/D [ 174 0 R /XYZ 443 528 null ] +>> +endobj +1558 0 obj +<< +/D [ 174 0 R /XYZ 215 509 null ] +>> +endobj +1559 0 obj +<< +/D [ 174 0 R /XYZ 284 509 null ] +>> +endobj +1560 0 obj +<< +/D [ 174 0 R /XYZ 353 509 null ] +>> +endobj +1561 0 obj +<< +/D [ 174 0 R /XYZ 374 509 null ] +>> +endobj +1562 0 obj +<< +/D [ 174 0 R /XYZ 443 509 null ] +>> +endobj +1563 0 obj +<< +/D [ 174 0 R /XYZ 215 490 null ] +>> +endobj +1564 0 obj +<< +/D [ 174 0 R /XYZ 284 490 null ] +>> +endobj +1565 0 obj +<< +/D [ 174 0 R /XYZ 353 490 null ] +>> +endobj +1566 0 obj +<< +/D [ 174 0 R /XYZ 374 490 null ] +>> +endobj +1567 0 obj +<< +/D [ 174 0 R /XYZ 443 490 null ] +>> +endobj +1568 0 obj +<< +/D [ 174 0 R /XYZ 215 471 null ] +>> +endobj +1569 0 obj +<< +/D [ 174 0 R /XYZ 284 471 null ] +>> +endobj +1570 0 obj +<< +/D [ 174 0 R /XYZ 353 471 null ] +>> +endobj +1571 0 obj +<< +/D [ 174 0 R /XYZ 374 471 null ] +>> +endobj +1572 0 obj +<< +/D [ 174 0 R /XYZ 443 471 null ] +>> +endobj +1573 0 obj +<< +/D [ 174 0 R /XYZ 215 452 null ] +>> +endobj +1574 0 obj +<< +/D [ 174 0 R /XYZ 284 452 null ] +>> +endobj +1575 0 obj +<< +/D [ 174 0 R /XYZ 353 452 null ] +>> +endobj +1576 0 obj +<< +/D [ 174 0 R /XYZ 374 452 null ] +>> +endobj +1577 0 obj +<< +/D [ 174 0 R /XYZ 443 452 null ] +>> +endobj +1578 0 obj +<< +/D [ 174 0 R /XYZ 215 433 null ] +>> +endobj +1579 0 obj +<< +/D [ 174 0 R /XYZ 284 433 null ] +>> +endobj +1580 0 obj +<< +/D [ 174 0 R /XYZ 353 433 null ] +>> +endobj +1581 0 obj +<< +/D [ 174 0 R /XYZ 374 433 null ] +>> +endobj +1582 0 obj +<< +/D [ 174 0 R /XYZ 443 433 null ] +>> +endobj +1583 0 obj +<< +/D [ 174 0 R /XYZ 215 414 null ] +>> +endobj +1584 0 obj +<< +/D [ 174 0 R /XYZ 284 414 null ] +>> +endobj +1585 0 obj +<< +/D [ 174 0 R /XYZ 353 414 null ] +>> +endobj +1586 0 obj +<< +/D [ 174 0 R /XYZ 374 414 null ] +>> +endobj +1587 0 obj +<< +/D [ 174 0 R /XYZ 443 414 null ] +>> +endobj +1588 0 obj +<< +/D [ 174 0 R /XYZ 215 395 null ] +>> +endobj +1589 0 obj +<< +/D [ 174 0 R /XYZ 284 395 null ] +>> +endobj +1590 0 obj +<< +/D [ 174 0 R /XYZ 353 395 null ] +>> +endobj +1591 0 obj +<< +/D [ 174 0 R /XYZ 374 395 null ] +>> +endobj +1592 0 obj +<< +/D [ 174 0 R /XYZ 443 395 null ] +>> +endobj +1593 0 obj +<< +/D [ 174 0 R /XYZ 215 376 null ] +>> +endobj +1594 0 obj +<< +/D [ 174 0 R /XYZ 284 376 null ] +>> +endobj +1595 0 obj +<< +/D [ 174 0 R /XYZ 353 376 null ] +>> +endobj +1596 0 obj +<< +/D [ 174 0 R /XYZ 374 376 null ] +>> +endobj +1597 0 obj +<< +/D [ 174 0 R /XYZ 443 376 null ] +>> +endobj +1598 0 obj +<< +/D [ 174 0 R /XYZ 215 357 null ] +>> +endobj +1599 0 obj +<< +/D [ 174 0 R /XYZ 284 357 null ] +>> +endobj +1600 0 obj +<< +/D [ 174 0 R /XYZ 353 357 null ] +>> +endobj +1601 0 obj +<< +/D [ 174 0 R /XYZ 374 357 null ] +>> +endobj +1602 0 obj +<< +/D [ 174 0 R /XYZ 443 357 null ] +>> +endobj +1603 0 obj +<< +/D [ 174 0 R /XYZ 215 338 null ] +>> +endobj +1604 0 obj +<< +/D [ 174 0 R /XYZ 284 338 null ] +>> +endobj +1605 0 obj +<< +/D [ 174 0 R /XYZ 353 338 null ] +>> +endobj +1606 0 obj +<< +/D [ 174 0 R /XYZ 374 338 null ] +>> +endobj +1607 0 obj +<< +/D [ 174 0 R /XYZ 443 338 null ] +>> +endobj +1608 0 obj +<< +/D [ 174 0 R /XYZ 215 319 null ] +>> +endobj +1609 0 obj +<< +/D [ 174 0 R /XYZ 284 319 null ] +>> +endobj +1610 0 obj +<< +/D [ 174 0 R /XYZ 353 319 null ] +>> +endobj +1611 0 obj +<< +/D [ 174 0 R /XYZ 374 319 null ] +>> +endobj +1612 0 obj +<< +/D [ 174 0 R /XYZ 443 319 null ] +>> +endobj +1613 0 obj +<< +/D [ 174 0 R /XYZ 215 300 null ] +>> +endobj +1614 0 obj +<< +/D [ 174 0 R /XYZ 284 300 null ] +>> +endobj +1615 0 obj +<< +/D [ 174 0 R /XYZ 353 300 null ] +>> +endobj +1616 0 obj +<< +/D [ 174 0 R /XYZ 374 300 null ] +>> +endobj +1617 0 obj +<< +/D [ 174 0 R /XYZ 443 300 null ] +>> +endobj +1618 0 obj +<< +/D [ 174 0 R /XYZ 215 281 null ] +>> +endobj +1619 0 obj +<< +/D [ 174 0 R /XYZ 284 281 null ] +>> +endobj +1620 0 obj +<< +/D [ 174 0 R /XYZ 353 281 null ] +>> +endobj +1621 0 obj +<< +/D [ 174 0 R /XYZ 374 281 null ] +>> +endobj +1622 0 obj +<< +/D [ 174 0 R /XYZ 443 281 null ] +>> +endobj +1623 0 obj +<< +/D [ 174 0 R /XYZ 215 262 null ] +>> +endobj +1624 0 obj +<< +/D [ 174 0 R /XYZ 284 262 null ] +>> +endobj +1625 0 obj +<< +/D [ 174 0 R /XYZ 353 262 null ] +>> +endobj +1626 0 obj +<< +/D [ 174 0 R /XYZ 374 262 null ] +>> +endobj +1627 0 obj +<< +/D [ 174 0 R /XYZ 443 262 null ] +>> +endobj +1628 0 obj +<< +/D [ 174 0 R /XYZ 215 243 null ] +>> +endobj +1629 0 obj +<< +/D [ 174 0 R /XYZ 284 243 null ] +>> +endobj +1630 0 obj +<< +/D [ 174 0 R /XYZ 353 243 null ] +>> +endobj +1631 0 obj +<< +/D [ 174 0 R /XYZ 374 243 null ] +>> +endobj +1632 0 obj +<< +/D [ 174 0 R /XYZ 443 243 null ] +>> +endobj +1633 0 obj +<< +/D [ 174 0 R /XYZ 215 224 null ] +>> +endobj +1634 0 obj +<< +/D [ 174 0 R /XYZ 284 224 null ] +>> +endobj +1635 0 obj +<< +/D [ 174 0 R /XYZ 353 224 null ] +>> +endobj +1636 0 obj +<< +/D [ 174 0 R /XYZ 374 224 null ] +>> +endobj +1637 0 obj +<< +/D [ 174 0 R /XYZ 443 224 null ] +>> +endobj +1638 0 obj +<< +/D [ null /XYZ null null null ] +>> +endobj +1639 0 obj +<< +/D [ 178 0 R /XYZ null null null ] +>> +endobj +1640 0 obj +<< +/D [ 178 0 R /XYZ 107 110 null ] +>> +endobj +1641 0 obj +<< +/D [ 178 0 R /XYZ 464 717 null ] +>> +endobj +1642 0 obj +<< +/D [ 178 0 R /XYZ 107 640 null ] +>> +endobj +1643 0 obj +<< +/D [ 178 0 R /XYZ 107 551 null ] +>> +endobj +1644 0 obj +<< +/D [ 178 0 R /XYZ 107 527 null ] +>> +endobj +1645 0 obj +<< +/D [ 178 0 R /XYZ 107 410 null ] +>> +endobj +1646 0 obj +<< +/D [ 178 0 R /XYZ 107 387 null ] +>> +endobj +1647 0 obj +<< +/D [ 178 0 R /XYZ 107 366 null ] +>> +endobj +1648 0 obj +<< +/D [ 178 0 R /XYZ 107 318 null ] +>> +endobj +1649 0 obj +<< +/D [ 178 0 R /XYZ 107 297 null ] +>> +endobj +1650 0 obj +<< +/D [ 178 0 R /XYZ 107 257 null ] +>> +endobj +1651 0 obj +<< +/D [ 178 0 R /XYZ 107 205 null ] +>> +endobj +1652 0 obj +<< +/D [ 182 0 R /XYZ 98 695 null ] +>> +endobj +1653 0 obj +<< +/D [ 182 0 R /XYZ 98 110 null ] +>> +endobj +1654 0 obj +<< +/D [ 182 0 R /XYZ 98 663 null ] +>> +endobj +1655 0 obj +<< +/D [ 182 0 R /XYZ 98 545 null ] +>> +endobj +1656 0 obj +<< +/D [ 182 0 R /XYZ 98 502 null ] +>> +endobj +1657 0 obj +<< +/D [ 182 0 R /XYZ 98 466 null ] +>> +endobj +1658 0 obj +<< +/D [ 182 0 R /XYZ 98 445 null ] +>> +endobj +1659 0 obj +<< +/D [ 182 0 R /XYZ 98 314 null ] +>> +endobj +1660 0 obj +<< +/D [ 182 0 R /XYZ 206 653 null ] +>> +endobj +1661 0 obj +<< +/D [ 182 0 R /XYZ 206 633 null ] +>> +endobj +1662 0 obj +<< +/D [ 182 0 R /XYZ 296 633 null ] +>> +endobj +1663 0 obj +<< +/D [ 182 0 R /XYZ 386 633 null ] +>> +endobj +1664 0 obj +<< +/D [ 182 0 R /XYZ 206 614 null ] +>> +endobj +1665 0 obj +<< +/D [ 182 0 R /XYZ 296 614 null ] +>> +endobj +1666 0 obj +<< +/D [ 182 0 R /XYZ 386 614 null ] +>> +endobj +1667 0 obj +<< +/D [ 182 0 R /XYZ 206 583 null ] +>> +endobj +1668 0 obj +<< +/D [ 182 0 R /XYZ 296 583 null ] +>> +endobj +1669 0 obj +<< +/D [ 182 0 R /XYZ 386 583 null ] +>> +endobj +1670 0 obj +<< +/D [ 186 0 R /XYZ 107 695 null ] +>> +endobj +1671 0 obj +<< +/D [ 186 0 R /XYZ 107 110 null ] +>> +endobj +1672 0 obj +<< +/D [ 186 0 R /XYZ 107 665 null ] +>> +endobj +1673 0 obj +<< +/D [ 186 0 R /XYZ 107 644 null ] +>> +endobj +1674 0 obj +<< +/D [ 186 0 R /XYZ 107 632 null ] +>> +endobj +1675 0 obj +<< +/D [ 186 0 R /XYZ 107 478 null ] +>> +endobj +1676 0 obj +<< +/D [ 186 0 R /XYZ 133 622 null ] +>> +endobj +1677 0 obj +<< +/D [ 186 0 R /XYZ 133 602 null ] +>> +endobj +1678 0 obj +<< +/D [ 186 0 R /XYZ 274 602 null ] +>> +endobj +1679 0 obj +<< +/D [ 186 0 R /XYZ 407 602 null ] +>> +endobj +1680 0 obj +<< +/D [ 186 0 R /XYZ 133 583 null ] +>> +endobj +1681 0 obj +<< +/D [ 186 0 R /XYZ 274 583 null ] +>> +endobj +1682 0 obj +<< +/D [ 186 0 R /XYZ 407 583 null ] +>> +endobj +1683 0 obj +<< +/D [ 186 0 R /XYZ 133 564 null ] +>> +endobj +1684 0 obj +<< +/D [ 186 0 R /XYZ 274 564 null ] +>> +endobj +1685 0 obj +<< +/D [ 186 0 R /XYZ 407 564 null ] +>> +endobj +1686 0 obj +<< +/D [ 186 0 R /XYZ 133 545 null ] +>> +endobj +1687 0 obj +<< +/D [ 186 0 R /XYZ 274 545 null ] +>> +endobj +1688 0 obj +<< +/D [ 186 0 R /XYZ 407 545 null ] +>> +endobj +1689 0 obj +<< +/D [ 186 0 R /XYZ 133 526 null ] +>> +endobj +1690 0 obj +<< +/D [ 186 0 R /XYZ 274 526 null ] +>> +endobj +1691 0 obj +<< +/D [ 186 0 R /XYZ 407 526 null ] +>> +endobj +1692 0 obj +<< +/D [ 186 0 R /XYZ 133 507 null ] +>> +endobj +1693 0 obj +<< +/D [ 186 0 R /XYZ 274 507 null ] +>> +endobj +1694 0 obj +<< +/D [ 186 0 R /XYZ 407 507 null ] +>> +endobj +1695 0 obj +<< +/D [ null /XYZ null null null ] +>> +endobj +1696 0 obj +<< +/Limits [ (on)(nnTz##)] +/Names [ (on)212 0 R (onT)833 0 R (onU)985 0 R (onV)1639 0 R (om)253 0 R (ol) +261 0 R (ok)380 0 R (oj)411 0 R (oi)446 0 R (oh)490 0 R (og)564 0 R +(of)789 0 R (nnJz)218 0 R (nnJz)219 0 R (nnJz)220 0 R (nnJz) +221 0 R (nnJ)224 0 R (nnJ)225 0 R (nnJ)226 0 R (nnJ) +227 0 R (nnJ)215 0 R (nnJ)216 0 R (nnJ)217 0 R (nnJ) +222 0 R (nnJ~)230 0 R (nnJ})223 0 R (nnJ})232 0 R (nnJ}) +233 0 R (nnJ})234 0 R (nnJ})235 0 R (nnJ})236 0 R (nnJ}) +237 0 R (nnJ})238 0 R (nnJ})239 0 R (nnJ})240 0 R (nnJ}) +241 0 R (nnJ})242 0 R (nnJ})243 0 R (nnJ})244 0 R (nnJ}) +245 0 R (nnJ})246 0 R (nnJ})247 0 R (nnJ})248 0 R (nnJ}) +249 0 R (nnJ})250 0 R (nnJ})251 0 R (nnJ})231 0 R (nnTz"/) +839 0 R (nnTz".)840 0 R (nnTz+.)841 0 R (nnTz* )842 0 R +(nnTz*/)843 0 R (nnTz*.)844 0 R (nnTz\(&)847 0 R (nnTz\(/) +848 0 R (nnTz/%)852 0 R (nnTz# )853 0 R (nnTz"$)854 0 R +(nnTz+')855 0 R (nnTz+&)856 0 R (nnTz+")857 0 R (nnTz+.) +858 0 R (nnTz#')851 0 R (nnTz##)849 0 R ] +>> +endobj +1697 0 obj +<< +/Limits [ (Mׅ)(Mׅ)] +/Names [ (Mׅ)850 0 R (Mׅ)870 0 R (Mׅ)871 0 R (Mׅ) +872 0 R (Mׅ)873 0 R (Mׅ)874 0 R (Mׅ)875 0 R +(Mׅ)876 0 R (Mׅ)878 0 R (Mׅ)879 0 R (Mׅ) +880 0 R (Mׅ)881 0 R (Mׅ)897 0 R (Mׅ)898 0 R +(Mׅ)899 0 R (Mׅ)900 0 R (Mׅ)901 0 R (Mׅ) +902 0 R (Mׅ)903 0 R (Mׅ)925 0 R (Mׅ)905 0 R +(Mׅ)906 0 R (Mׅ)907 0 R (Mׅ)908 0 R (Mׅ) +926 0 R (Mׅ)927 0 R (Mׅ)928 0 R (Mׅ)929 0 R +(Mׅ)930 0 R (Mׅ)931 0 R (Mׅ)944 0 R (Mׅ) +933 0 R (Mׅ)934 0 R (Mׅ)935 0 R (Mׅ)936 0 R +(Mׅ)982 0 R (Mׅ)945 0 R (Mׅ)952 0 R (Mׅ) +953 0 R (Mׅ)954 0 R (Mׅ)955 0 R (Mׅ)956 0 R +(Mׅ)957 0 R (Mׅ)958 0 R (Mׅ)959 0 R (Mׅ) +960 0 R (Mׅ)961 0 R (Mׅ)962 0 R (Mׅ)963 0 R +(Mׅ)964 0 R (Mׅ)965 0 R (Mׅ)966 0 R (Mׅ) +967 0 R (Mׅ)968 0 R (Mׅ)969 0 R (Mׅ)970 0 R +(Mׅ)971 0 R (Mׅ)976 0 R (Mׅ)977 0 R (Mׅ) +978 0 R (Mׅ)980 0 R (Mׅ)979 0 R (Mׅ)975 0 R +(Mׅ)972 0 R ] +>> +endobj +1698 0 obj +<< +/Limits [ (fcs)(fcs)] +/Names [ (fcs)973 0 R (fcs)974 0 R (fcr)949 0 R (fcr) +950 0 R (fcr)951 0 R (fcr)946 0 R (fcr)947 0 R +(fcr)948 0 R (fcv)837 0 R (fcv)838 0 R (fc{) +845 0 R (fc{)846 0 R (fcs)868 0 R (fcs)869 0 R +(fcw)836 0 R (fct)859 0 R (fct)860 0 R (fct) +861 0 R (fct)862 0 R (fct)863 0 R (fc{)864 0 R +(fc{)865 0 R (fc{)866 0 R (fc{)867 0 R (fcz) +882 0 R (fcz)883 0 R (fcz)884 0 R (fcz)885 0 R +(fcz)886 0 R (fcs)887 0 R (fcs)888 0 R (fcs) +889 0 R (fcs)890 0 R (fcr)909 0 R (fcr)910 0 R +(fcr)911 0 R (fcr)912 0 R (fcq)913 0 R (fcq) +914 0 R (fcq)915 0 R (fcq)916 0 R (fcq)917 0 R +(fcp)937 0 R (fcp)938 0 R (fcw)939 0 R (fcw) +940 0 R (fcw)941 0 R (fcw)942 0 R (fcu)894 0 R +(fcu)895 0 R (fcu)896 0 R (fcu)891 0 R (fcu) +892 0 R (fct)893 0 R (fcs)877 0 R (fc{)921 0 R +(fc{)922 0 R (fc{)923 0 R (fcz)918 0 R (fcz) +919 0 R (fcz)920 0 R (fcw)904 0 R (fc{)932 0 R +(fcs)987 0 R ] +>> +endobj +1699 0 obj +<< +/Limits [ (I*L)(I*J)] +/Names [ (I*L)988 0 R (I*I)991 0 R (I*H)999 0 R (I*J) +1000 0 R (I*D)1001 0 R (I*L)1002 0 R (I*N)1003 0 R +(I*H)1004 0 R (I*J)1005 0 R (I*D)1006 0 R (I*L) +1007 0 R (I*N)1008 0 R (I*H)1009 0 R (I*J)1010 0 R +(I*D)1011 0 R (I*L)1012 0 R (I*N)1013 0 R (I*H) +1014 0 R (I*J)1015 0 R (I*D)1016 0 R (I*L)1017 0 R +(I*N)1018 0 R (I*H)1019 0 R (I*J)1020 0 R (I*D) +1021 0 R (I*L)1022 0 R (I*N)1023 0 R (I*H)1024 0 R +(I*J)1025 0 R (I*D)1026 0 R (I*L)1027 0 R (I*N) +1028 0 R (I*H)1029 0 R (I*J)1030 0 R (I*D)1031 0 R +(I*L)1032 0 R (I*N)1033 0 R (I*H)1034 0 R (I*J) +1035 0 R (I*D)1036 0 R (I*L)1037 0 R (I*N)1038 0 R +(I*H)1039 0 R (I*J)1040 0 R (I*D)1041 0 R (I*L) +1042 0 R (I*N)1043 0 R (I*H)1044 0 R (I*J)1045 0 R +(I*D)1046 0 R (I*L)1047 0 R (I*N)1048 0 R (I*H) +1049 0 R (I*J)1050 0 R (I*D)1051 0 R (I*L)1052 0 R +(I*N)1053 0 R (I*H)1054 0 R (I*J)1055 0 R (I*D) +1056 0 R (I*L)1057 0 R (I*N)1058 0 R (I*H)1059 0 R +(I*J)1060 0 R ] +>> +endobj +1700 0 obj +<< +/Limits [ (|=h )(|=h\r)] +/Names [ (|=h )1061 0 R (|=h )1062 0 R (|=h )1063 0 R (|=h ) +1064 0 R (|=h )1065 0 R (|=h )1066 0 R (|=h )1067 0 R +(|=h )1068 0 R (|=h )1069 0 R (|=h )1070 0 R (|=h ) +1071 0 R (|=h )1072 0 R (|=h )1073 0 R (|=h )1074 0 R +(|=h )1075 0 R (|=h )1076 0 R (|=h )1077 0 R (|=h ) +1078 0 R (|=h )1079 0 R (|=h )1080 0 R (|=h )1081 0 R +(|=h )1082 0 R (|=h )1083 0 R (|=h )1084 0 R (|=h ) +1085 0 R (|=h )1086 0 R (|=h )1087 0 R (|=h )1088 0 R +(|=h )1089 0 R (|=h )1090 0 R (|=h )1091 0 R (|=h ) +1092 0 R (|=h )1093 0 R (|=h )1094 0 R (|=h )1095 0 R +(|=h )1096 0 R (|=h )1097 0 R (|=h )1098 0 R (|=h ) +1099 0 R (|=h )1100 0 R (|=h )1101 0 R (|=h )1102 0 R +(|=h )1103 0 R (|=h )1104 0 R (|=h )1105 0 R (|=h ) +1106 0 R (|=h\r)1107 0 R (|=h\r)1108 0 R (|=h\r)1109 0 R +(|=h\r)1110 0 R (|=h\r)1111 0 R (|=h\r)1112 0 R (|=h\r) +1113 0 R (|=h\r)1114 0 R (|=h\r)1115 0 R (|=h\r)1116 0 R +(|=h\r)1117 0 R (|=h\r)1118 0 R (|=h\r)1119 0 R (|=h\r) +1120 0 R (|=h\r)1121 0 R (|=h\r)1122 0 R (|=h\r)1123 0 R +(|=h\r)1124 0 R ] +>> +endobj +1701 0 obj +<< +/Limits [ (1ˍ)(1‰)] +/Names [ (1ˍ)1128 0 R (1ˍ)1129 0 R (1ˊ)1130 0 R (1ˊ) +1131 0 R (1ˊ)1132 0 R (1ˊ)1133 0 R (1ˊ)1134 0 R +(1ˋ)1135 0 R (1ˋ)1136 0 R (1ˋ)1137 0 R (1ˋ) +1138 0 R (1ˋ)1139 0 R (1ˈ)1140 0 R (1ˈ)1141 0 R +(1ˈ)1142 0 R (1ˈ)1143 0 R (1ˈ)1144 0 R (1ˉ) +1145 0 R (1ˉ)1146 0 R (1ˉ)1147 0 R (1ˉ)1148 0 R +(1ˉ)1149 0 R (1ˆ)1150 0 R (1ˆ)1151 0 R (1ˆ) +1152 0 R (1ˆ)1153 0 R (1ˆ)1154 0 R (1ˇ)1155 0 R +(1ˇ)1156 0 R (1ˇ)1157 0 R (1ˇ)1158 0 R (1ˇ) +1159 0 R (1Ž)1160 0 R (1Ž)1161 0 R (1Ž)1162 0 R +(1Ž)1163 0 R (1Ž)1164 0 R (1)1165 0 R (1) +1166 0 R (1)1167 0 R (1)1168 0 R (1)1169 0 R +(1Œ)989 0 R (1Œ)1172 0 R (1)1173 0 R (1) +1174 0 R (1)1175 0 R (1Š)1176 0 R (1Š)1177 0 R +(1Š)1178 0 R (1Š)1179 0 R (1Š)1180 0 R (1‹) +1181 0 R (1‹)1182 0 R (1‹)1183 0 R (1‹)1184 0 R +(1‹)1185 0 R (1ˆ)1186 0 R (1ˆ)1187 0 R (1ˆ) +1188 0 R (1ˆ)1189 0 R (1ˆ)1190 0 R (1‰)1191 0 R +(1‰)1192 0 R ] +>> +endobj +1702 0 obj +<< +/Limits [ (zEey)(zEe~)] +/Names [ (zEey)1193 0 R (zEey)1194 0 R (zEey)1195 0 R (zEev) +1196 0 R (zEev)1197 0 R (zEev)1198 0 R (zEev)1199 0 R +(zEev)1200 0 R (zEew)1201 0 R (zEew)1202 0 R (zEew) +1203 0 R (zEew)1204 0 R (zEew)1205 0 R (zEe~)1206 0 R +(zEe~)1207 0 R (zEe~)1208 0 R (zEe~)1209 0 R (zEe~) +1210 0 R (zEe)1211 0 R (zEe)1212 0 R (zEe)1213 0 R +(zEe)1214 0 R (zEe)1215 0 R (zEe|)1216 0 R (zEe|) +1217 0 R (zEe|)1218 0 R (zEe|)1219 0 R (zEe|)1220 0 R +(zEe})1221 0 R (zEe})1222 0 R (zEe})1223 0 R (zEe}) +1224 0 R (zEe})1225 0 R (zEez)1226 0 R (zEez)1227 0 R +(zEez)1228 0 R (zEez)1229 0 R (zEez)1230 0 R (zEe{) +1231 0 R (zEe{)1232 0 R (zEe{)1233 0 R (zEe{)1234 0 R +(zEe{)1235 0 R (zEex)1236 0 R (zEex)1237 0 R (zEex) +1238 0 R (zEex)1239 0 R (zEex)1240 0 R (zEey)1241 0 R +(zEey)1242 0 R (zEey)1243 0 R (zEey)1244 0 R (zEey) +1245 0 R (zEev)1246 0 R (zEev)1247 0 R (zEev)1248 0 R +(zEev)1249 0 R (zEev)1250 0 R (zEew)1251 0 R (zEew) +1252 0 R (zEew)1253 0 R (zEew)1254 0 R (zEew)1255 0 R +(zEe~)1256 0 R ] +>> +endobj +1703 0 obj +<< +/Limits [ (`=G`)(`=Gb )] +/Names [ (`=G`)1259 0 R (`=G`)1260 0 R (`=G`)1261 0 R (`=G` ) +1262 0 R (`=Ga)1263 0 R (`=Ga)1264 0 R (`=Ga)1265 0 R +(`=Ga)1266 0 R (`=Ga )1267 0 R (`=Gb)1268 0 R (`=Gb) +1269 0 R (`=Gb)1270 0 R (`=Gb)1271 0 R (`=Gb )1272 0 R +(`=Gc)1273 0 R (`=Gc)1274 0 R (`=Gc)1275 0 R (`=Gc) +1276 0 R (`=Gc )1277 0 R (`=Gd)1278 0 R (`=Gd)1279 0 R +(`=Gd)1280 0 R (`=Gd)1281 0 R (`=Gd )1282 0 R (`=Ge) +1283 0 R (`=Ge)1284 0 R (`=Ge)1285 0 R (`=Ge)1286 0 R +(`=Ge )1287 0 R (`=Gf)1288 0 R (`=Gf)1289 0 R (`=Gf) +1290 0 R (`=Gf)1291 0 R (`=Gf )1292 0 R (`=Gg)1293 0 R +(`=Gg)1294 0 R (`=Gg)1295 0 R (`=Gg)1296 0 R (`=Gg ) +1297 0 R (`=Gh)1298 0 R (`=Gh)1299 0 R (`=Gh)1300 0 R +(`=Gh)1301 0 R (`=Gh )1302 0 R (`=Gi)1303 0 R (`=Gi) +1304 0 R (`=Gi)1305 0 R (`=Gi)1306 0 R (`=Gi )1307 0 R +(`=G`)1308 0 R (`=G`)1309 0 R (`=G`)1310 0 R (`=G`) +1311 0 R (`=G` )1312 0 R (`=Ga)1313 0 R (`=Ga)1314 0 R +(`=Ga)1315 0 R (`=Ga)1316 0 R (`=Ga )1317 0 R (`=Gb) +1318 0 R (`=Gb)1319 0 R (`=Gb)1320 0 R (`=Gb)1321 0 R +(`=Gb )1322 0 R ] +>> +endobj +1704 0 obj +<< +/Limits [ (qQ%8Y\r)(qQ%8^)] +/Names [ (qQ%8Y\r)1323 0 R (qQ%8Y)1324 0 R (qQ%8Y )1325 0 R (qQ%8Y) +1326 0 R (qQ%8Y\r)1327 0 R (qQ%8Y)1328 0 R (qQ%8Y )1329 0 R +(qQ%8Y )1330 0 R (qQ%8Y)1331 0 R (qQ%8Y\r)1332 0 R (qQ%8Y) +1333 0 R (qQ%8Y )1334 0 R (qQ%8Y )1335 0 R (qQ%8Y)1336 0 R +(qQ%8Y\r)1337 0 R (qQ%8Y)1338 0 R (qQ%8Y )1339 0 R (qQ%8Y ) +1340 0 R (qQ%8Y)1341 0 R (qQ%8Y\r)1342 0 R (qQ%8Y)1343 0 R +(qQ%8Y )1344 0 R (qQ%8Y )1345 0 R (qQ%8Y)1346 0 R (qQ%8Y\r) +1347 0 R (qQ%8Y)1348 0 R (qQ%8Y )1349 0 R (qQ%8Y )1350 0 R +(qQ%8Y)1351 0 R (qQ%8^\r)1352 0 R (qQ%8^)1353 0 R (qQ%8^ ) +1354 0 R (qQ%8^ )1355 0 R (qQ%8^)1356 0 R (qQ%8^\r)1357 0 R +(qQ%8^)1358 0 R (qQ%8^ )1359 0 R (qQ%8^ )1360 0 R (qQ%8^) +1361 0 R (qQ%8^\r)1362 0 R (qQ%8^)1363 0 R (qQ%8^ )1364 0 R +(qQ%8^ )1365 0 R (qQ%8^)1366 0 R (qQ%8^\r)1367 0 R (qQ%8^) +1368 0 R (qQ%8^ )1369 0 R (qQ%8^ )1370 0 R (qQ%8^)1371 0 R +(qQ%8^\r)1372 0 R (qQ%8^)1373 0 R (qQ%8^ )1374 0 R (qQ%8^ ) +1375 0 R (qQ%8^)1376 0 R (qQ%8^\r)1377 0 R (qQ%8^)1378 0 R +(qQ%8^ )1379 0 R (qQ%8^ )1380 0 R (qQ%8^)1381 0 R (qQ%8^\r) +1382 0 R (qQ%8^)1383 0 R (qQ%8^ )1384 0 R (qQ%8^ )1385 0 R +(qQ%8^)1386 0 R ] +>> +endobj +1705 0 obj +<< +/Limits [ (M2`|3)(M2`r5)] +/Names [ (M2`|3)1387 0 R (M2`|1)1388 0 R (M2`|7)1389 0 R (M2`|5) +1390 0 R (M2`|;)1391 0 R (M2`s3)1392 0 R (M2`s1)1393 0 R +(M2`s7)1394 0 R (M2`s5)1395 0 R (M2`s;)1396 0 R (M2`r3) +1397 0 R (M2`r1)1398 0 R (M2`r7)1399 0 R (M2`r5)1400 0 R +(M2`r;)1401 0 R (M2`{3)1402 0 R (M2`{1)1403 0 R (M2`{7) +1404 0 R (M2`{5)1405 0 R (M2`{;)1406 0 R (M2`z3)1407 0 R +(M2`z1)1408 0 R (M2`z7)1410 0 R (M2`z5)1411 0 R (M2`z;) +1412 0 R (M2`y3)1413 0 R (M2`y1)1414 0 R (M2`y7)1415 0 R +(M2`y5)1416 0 R (M2`y;)1417 0 R (M2`x3)1418 0 R (M2`x1) +1419 0 R (M2`x7)1420 0 R (M2`x5)1421 0 R (M2`x;)1422 0 R +(M2`3)1423 0 R (M2`1)1424 0 R (M2`7)1425 0 R (M2`5) +1426 0 R (M2`;)1427 0 R (M2`~3)1428 0 R (M2`~1)1429 0 R +(M2`~7)1430 0 R (M2`~5)1431 0 R (M2`~;)1432 0 R (M2`}3) +1433 0 R (M2`}1)1434 0 R (M2`}7)1435 0 R (M2`}5)1436 0 R +(M2`};)1437 0 R (M2`|3)1438 0 R (M2`|1)1439 0 R (M2`|7) +1440 0 R (M2`|5)1441 0 R (M2`|;)1442 0 R (M2`s3)1443 0 R +(M2`s1)1444 0 R (M2`s7)1445 0 R (M2`s5)1446 0 R (M2`s;) +1447 0 R (M2`r3)1448 0 R (M2`r1)1449 0 R (M2`r7)1450 0 R +(M2`r5)1451 0 R ] +>> +endobj +1706 0 obj +<< +/Limits [ (c륹)(c騱)] +/Names [ (c륹)1452 0 R (c謱)1453 0 R (c謳)1454 0 R (c謵) +1455 0 R (c謷)1456 0 R (c謹)1457 0 R (c譱)1458 0 R +(c譳)1459 0 R (c譵)1460 0 R (c護)1461 0 R (c譹) +1462 0 R (c讱)1463 0 R (c讳)1464 0 R (c讵)1465 0 R +(c讷)1466 0 R (c讹)1467 0 R (c诱)1468 0 R (c诳) +1469 0 R (c说)1127 0 R (c请)1470 0 R (c訷)1471 0 R +(c詷)1472 0 R (c詹)1473 0 R (c誱)1474 0 R (c誳) +1475 0 R (c誵)1476 0 R (c誷)1477 0 R (c誹)1478 0 R +(c諱)1479 0 R (c諳)1480 0 R (c諵)1481 0 R (c諷) +1482 0 R (c諹)1483 0 R (c褱)1484 0 R (c褳)1485 0 R +(c褵)1486 0 R (c褷)1487 0 R (c褹)1488 0 R (c襱) +1489 0 R (c襳)1490 0 R (c襵)1491 0 R (c襷)1492 0 R +(c襹)1493 0 R (c鬱)1494 0 R (c鬳)1495 0 R (c鬵) +1496 0 R (c鬷)1497 0 R (c鬹)1498 0 R (c魱)1499 0 R +(c魳)1500 0 R (c魵)1501 0 R (c魷)1502 0 R (c魹) +1503 0 R (c鮱)1504 0 R (c鮳)1505 0 R (c鮵)1506 0 R +(c鮷)1507 0 R (c鮹)1508 0 R (c鯱)1509 0 R (c鯳) +1510 0 R (c鯵)1511 0 R (c鯷)1512 0 R (c鯹)1513 0 R +(c騱)1514 0 R ] +>> +endobj +1707 0 obj +<< +/Limits [ (?j~)(?j|)] +/Names [ (?j~)1515 0 R (?j~)1516 0 R (?j~)1517 0 R (?j~) +1518 0 R (?j)1519 0 R (?j)1520 0 R (?j)1521 0 R +(?j)1522 0 R (?j)1523 0 R (?j|)1524 0 R (?j|) +1525 0 R (?j|)1526 0 R (?j|)1527 0 R (?j|)1528 0 R +(?j})1529 0 R (?j})1530 0 R (?j})1531 0 R (?j}) +1533 0 R (?j})1534 0 R (?jr)1535 0 R (?jr)1536 0 R +(?jr)1537 0 R (?jr)1538 0 R (?jr)1539 0 R (?js) +1540 0 R (?js)1541 0 R (?js)1542 0 R (?js)1543 0 R +(?js)1544 0 R (?jz)1545 0 R (?jz)1546 0 R (?jz) +1547 0 R (?jz)1548 0 R (?jz)1549 0 R (?j{)1550 0 R +(?j{)1551 0 R (?j{)1552 0 R (?j{)1553 0 R (?j{) +1554 0 R (?jx)1555 0 R (?jx)1556 0 R (?jx)1557 0 R +(?jx)1558 0 R (?jx)1559 0 R (?jy)1560 0 R (?jy) +1561 0 R (?jy)1562 0 R (?jy)1563 0 R (?jy)1564 0 R +(?j~)1565 0 R (?j~)1566 0 R (?j~)1567 0 R (?j~) +1568 0 R (?j~)1569 0 R (?j)1570 0 R (?j)1571 0 R +(?j)1572 0 R (?j)1573 0 R (?j)1574 0 R (?j|) +1575 0 R (?j|)1576 0 R (?j|)1577 0 R (?j|)1578 0 R +(?j|)1579 0 R ] +>> +endobj +1708 0 obj +<< +/Limits [ ( vW5)( vVw0)] +/Names [ ( vW5)1580 0 R ( vW7)1581 0 R ( vW1)1582 0 R ( vW3) +1583 0 R ( vW=)1584 0 R ( vW5)1585 0 R ( vW7)1586 0 R +( vW1)1587 0 R ( vW3)1588 0 R ( vW=)1589 0 R ( vW5) +1590 0 R ( vW7)1591 0 R ( vW1)1592 0 R ( vW3)1593 0 R +( vW=)1594 0 R ( vW~5)1595 0 R ( vW~7)1596 0 R ( vW~1) +1597 0 R ( vW~3)1598 0 R ( vW~=)1599 0 R ( vW~5)1600 0 R +( vW~7)1601 0 R ( vW~1)1602 0 R ( vW~3)1603 0 R ( vW~=) +1604 0 R ( vW~5)1605 0 R ( vW~7)1606 0 R ( vW~1)1607 0 R +( vW~3)1608 0 R ( vW~=)1609 0 R ( vW~5)1610 0 R ( vW~7) +1611 0 R ( vW~1)1612 0 R ( vW~3)1613 0 R ( vW~=)1614 0 R +( vW~5)1615 0 R ( vW~7)1616 0 R ( vW~1)1617 0 R ( vW~3) +1618 0 R ( vW~=)1619 0 R ( vW~5)1620 0 R ( vW~7)1621 0 R +( vW~1)1622 0 R ( vW~3)1623 0 R ( vW~=)1624 0 R ( vW~5) +1625 0 R ( vW~7)1626 0 R ( vW~1)1627 0 R ( vW~3)1628 0 R +( vW~=)1629 0 R ( vW~5)1630 0 R ( vW~7)1631 0 R ( vW~1) +1632 0 R ( vW~3)1633 0 R ( vW~=)1634 0 R ( vW~5)1635 0 R +( vW~7)1636 0 R ( vW~1)1637 0 R ( vW~2)1409 0 R ( vVw3) +990 0 R ( vVw<)992 0 R ( vVw4)993 0 R ( vVw6)994 0 R +( vVw0)995 0 R ] +>> +endobj +1709 0 obj +<< +/Limits [ (GX)(DY)] +/Names [ (GX)996 0 R (GX)997 0 R (GX)998 0 R (GX) +1170 0 R (GX)1171 0 R (GV)1125 0 R (GV)1126 0 R +(GV)1257 0 R (GV)1258 0 R (GV)986 0 R (GV) +1532 0 R (DZ)1641 0 R (DZ)1654 0 R (DZ)1642 0 R +(DZ)1643 0 R (DZ)1644 0 R (DZ)1645 0 R (DZ) +1646 0 R (DZ)1647 0 R (DZ)1648 0 R (DZ)1649 0 R +(DZ)1650 0 R (DZ)1651 0 R (DZ)1660 0 R (DZ) +1661 0 R (DZ)1662 0 R (DZ)1663 0 R (DZ)1664 0 R +(DZ)1665 0 R (DZ)1666 0 R (DZ)1667 0 R (DZ) +1668 0 R (DZ)1669 0 R (DZ)1675 0 R (DZ)1655 0 R +(DZ)1656 0 R (DZ)1657 0 R (DZ)1658 0 R (DZ) +1659 0 R (DZ)1672 0 R (DZ)1673 0 R (DZ)1676 0 R +(DZ)1677 0 R (DZ)1678 0 R (DZ)1679 0 R (DZ) +1680 0 R (DZ)1681 0 R (DZ)1682 0 R (DZ)1683 0 R +(DZ)1684 0 R (DZ)1685 0 R (DZ)1686 0 R (DZ) +1687 0 R (DZ)1688 0 R (DZ)1689 0 R (DZ)1690 0 R +(DZ)1691 0 R (DZ)1692 0 R (DZ)1693 0 R (DZ) +1694 0 R (DZ)1674 0 R (DY)1652 0 R (DY)1653 0 R +(DY)1670 0 R ] +>> +endobj +1710 0 obj +<< +/Limits [ (,l$NZ!)(,n8L\\!)] +/Names [ (,l$NZ!)1671 0 R (,l$NZ!)1640 0 R (,o8KU)259 0 R (,o8J\\) +260 0 R (,o8J_)254 0 R (,o8I\\)255 0 R (,o8I\\)256 0 R (,n8MT%) +292 0 R (,n8MU$)346 0 R (,n8MU')347 0 R (,n8MU")291 0 R +(,n8MU )371 0 R (,n8MU')372 0 R (,n8MU%)373 0 R (,n8MU+) +374 0 R (,n8MU#)375 0 R (,n8MU")376 0 R (,n8MU )377 0 R +(,n8MU&)378 0 R (,n8L\\')293 0 R (,n8L\\%)294 0 R (,n8L\\+) +295 0 R (,n8L\\#)296 0 R (,n8L\\!)297 0 R (,n8L\\')298 0 R +(,n8L\\%)299 0 R (,n8L\\+)300 0 R (,n8L\\#)301 0 R (,n8L\\') +302 0 R (,n8L\\%)303 0 R (,n8L\\+)304 0 R (,n8L\\#)305 0 R +(,n8L\\!)306 0 R (,n8L\\')307 0 R (,n8L\\%)308 0 R (,n8L\\+) +309 0 R (,n8L\\#)310 0 R (,n8L\\!)311 0 R (,n8L\\')312 0 R +(,n8L\\%)313 0 R (,n8L\\')314 0 R (,n8L\\%)315 0 R (,n8L\\#) +316 0 R (,n8L\\!)317 0 R (,n8L\\')318 0 R (,n8L\\+)319 0 R +(,n8L\\!)320 0 R (,n8L\\')348 0 R (,n8L\\%)349 0 R (,n8L\\#) +350 0 R (,n8L\\!)351 0 R (,n8L\\%)352 0 R (,n8L\\+)353 0 R +(,n8L\\%)354 0 R (,n8L\\+)355 0 R (,n8L\\$)357 0 R (,n8L\\+) +358 0 R (,n8L\\#)359 0 R (,n8L\\!)360 0 R (,n8L\\ )361 0 R +(,n8L\\&)362 0 R (,n8L\\%)363 0 R (,n8L\\+)364 0 R (,n8L\\!) +365 0 R ] +>> +endobj +1711 0 obj +<< +/Limits [ (@L.v)(@I.)] +/Names [ (@L.v)367 0 R (@L.w)368 0 R (@L.u)369 0 R (@L.z) +370 0 R (@L.{)356 0 R (@L.\rq)366 0 R (@K.\n)384 0 R +(@K.)383 0 R (@K.)408 0 R (@K.)385 0 R (@K.\r) +386 0 R (@K. )387 0 R (@K.)388 0 R (@K.)389 0 R (@K.) +390 0 R (@K.)391 0 R (@K. )396 0 R (@K.\n)397 0 R (@K.) +398 0 R (@K.\r)399 0 R (@K. )403 0 R (@K.)404 0 R (@K.) +405 0 R (@K. )406 0 R (@K.\n)407 0 R (@K.)394 0 R (@K.) +395 0 R (@K. )401 0 R (@K.)402 0 R (@J.\n)417 0 R (@J.) +445 0 R (@J.)418 0 R (@J.\r)419 0 R (@J. )420 0 R (@J.) +421 0 R (@J.)422 0 R (@J. )423 0 R (@J.\n)424 0 R (@J. ) +425 0 R (@J.)426 0 R (@J.)427 0 R (@J.)428 0 R (@J.\r) +429 0 R (@J. )430 0 R (@J.)431 0 R (@J.)432 0 R (@J. ) +433 0 R (@J.\n)437 0 R (@J. )438 0 R (@J.)439 0 R (@J.) +440 0 R (@J.)441 0 R (@J.\r)443 0 R (@J. )444 0 R (@J.) +435 0 R (@J. )436 0 R (@J.)416 0 R (@J.)442 0 R (@I.\n) +450 0 R (@I.)488 0 R (@I.)451 0 R (@I.\r)452 0 R (@I. ) +453 0 R (@I.)454 0 R ] +>> +endobj +1712 0 obj +<< +/Limits [ (#'Է? )(#&Է1)] +/Names [ (#'Է? )455 0 R (#'Է?\n)456 0 R (#'Է?\n)457 0 R (#'Է?\n) +458 0 R (#'Է?\n)460 0 R (#'Է?)461 0 R (#'Է?)462 0 R (#'Է?) +463 0 R (#'Է?)464 0 R (#'Է?)465 0 R (#'Է?)466 0 R (#'Է?) +467 0 R (#'Է?)468 0 R (#'Է?)469 0 R (#'Է>\r)470 0 R (#'Է>\r) +471 0 R (#'Է>\r)472 0 R (#'Է>\r)473 0 R (#'Է>\r)474 0 R +(#'Է> )475 0 R (#'Է> )476 0 R (#'Է> )459 0 R (#'Է> ) +480 0 R (#'Է> )481 0 R (#'Է>)482 0 R (#'Է>)486 0 R (#'Է>) +487 0 R (#'Զ8)478 0 R (#'Զ8)479 0 R (#'Զ;\r)484 0 R (#'Զ;\r) +485 0 R (#'Զ; )449 0 R (#&Դ9\n)494 0 R (#&Է? )495 0 R (#&Է? ) +496 0 R (#&Է1)497 0 R (#&Է1)498 0 R (#&Է1)499 0 R (#&Է1) +500 0 R (#&Է1)501 0 R (#&Է1)502 0 R (#&Է1 )503 0 R (#&Է1 ) +504 0 R (#&Է1 )505 0 R (#&Է1 )506 0 R (#&Է1 )507 0 R (#&Է1) +508 0 R (#&Է1)509 0 R (#&Է1)510 0 R (#&Է1)511 0 R (#&Է1) +512 0 R (#&Է1 )513 0 R (#&Է1 )514 0 R (#&Է1 )515 0 R (#&Է1 ) +516 0 R (#&Է1 )517 0 R (#&Է1\n)518 0 R (#&Է1\n)519 0 R +(#&Է1\n)520 0 R (#&Է1\n)521 0 R (#&Է1\n)522 0 R (#&Է1) +523 0 R (#&Է1)524 0 R (#&Է1)525 0 R ] +>> +endobj +1713 0 obj +<< +/Limits [ (ȫa)(Ȥa)] +/Names [ (ȫa)526 0 R (ȫa)527 0 R (ȫa)528 0 R (ȫa)529 0 R +(ȫa)530 0 R (ȫa)531 0 R (ȫa)532 0 R (ȫa) +533 0 R (ȫa)538 0 R (ȫa)539 0 R (ȫa)540 0 R (ȫa) +541 0 R (ȫa)542 0 R (ȫa)543 0 R (ȫa)544 0 R (ȫa) +545 0 R (ȫa)546 0 R (ȫa)547 0 R (ȫa)548 0 R (ȫa) +549 0 R (ȫa)550 0 R (ȫa)551 0 R (ȫa)552 0 R (ȫa) +553 0 R (ȫa)554 0 R (ȫa)555 0 R (ȫa)556 0 R (ȫa) +557 0 R (ȫa)558 0 R (ȫa)559 0 R (ȫa)560 0 R (ȫa) +561 0 R (ȫa)562 0 R (ȫa)563 0 R (ȫa)537 0 R (ȫ`) +535 0 R (ȫ`)536 0 R (ȫ`)493 0 R (Ȥb)569 0 R (Ȥa) +738 0 R (Ȥa)570 0 R (Ȥa)571 0 R (Ȥa)572 0 R (Ȥa) +573 0 R (Ȥa)574 0 R (Ȥa)579 0 R (Ȥa)581 0 R (Ȥa) +582 0 R (Ȥa)583 0 R (Ȥa)584 0 R (Ȥa)585 0 R (Ȥa) +586 0 R (Ȥa)587 0 R (Ȥa)588 0 R (Ȥa)589 0 R (Ȥa) +590 0 R (Ȥa)591 0 R (Ȥa)592 0 R (Ȥa)593 0 R (Ȥa) +594 0 R (Ȥa)595 0 R (Ȥa)596 0 R (Ȥa)597 0 R (Ȥa) +598 0 R ] +>> +endobj +1714 0 obj +<< +/Limits [ ( -\n|)( " v)] +/Names [ ( -\n|)599 0 R ( -\nz)600 0 R ( -\nx)601 0 R ( -\nv) +602 0 R ( -\r~)603 0 R ( -\r|)604 0 R ( -\rz)605 0 R +( -\rx)606 0 R ( -\rv)607 0 R ( - ~)608 0 R ( - |) +609 0 R ( - z)610 0 R ( - x)611 0 R ( - v)612 0 R ( -~) +613 0 R ( -|)614 0 R ( -z)615 0 R ( -x)616 0 R ( -v) +617 0 R ( -~)618 0 R ( -|)619 0 R ( -z)620 0 R ( -x) +621 0 R ( -v)622 0 R ( -~)623 0 R ( -|)624 0 R ( -z) +625 0 R ( -x)626 0 R ( -v)627 0 R ( -~)628 0 R ( -|) +629 0 R ( -z)630 0 R ( -x)631 0 R ( -v)632 0 R ( " ~) +633 0 R ( " |)634 0 R ( " z)635 0 R ( " x)636 0 R ( " v) +637 0 R ( "~)638 0 R ( "|)639 0 R ( "z)640 0 R ( "x) +641 0 R ( "v)642 0 R ( " ~)643 0 R ( " |)644 0 R ( " z) +645 0 R ( " x)646 0 R ( " v)647 0 R ( "\n~)648 0 R ( "\n|) +649 0 R ( "\nz)650 0 R ( "\nx)651 0 R ( "\nv)652 0 R +( "\r~)653 0 R ( "\r|)654 0 R ( "\rz)655 0 R ( "\rx) +656 0 R ( "\rv)657 0 R ( " ~)658 0 R ( " |)659 0 R ( " z) +660 0 R ( " x)661 0 R ( " v)662 0 R ] +>> +endobj +1715 0 obj +<< +/Limits [ (x,)(x,)] +/Names [ (x,)663 0 R (x,)664 0 R (x,)665 0 R (x,)666 0 R +(x,)667 0 R (x,)668 0 R (x,)669 0 R (x,) +670 0 R (x,)671 0 R (x,)672 0 R (x,)673 0 R (x,) +674 0 R (x,)675 0 R (x,)676 0 R (x,)677 0 R (x,) +678 0 R (x,)679 0 R (x,)680 0 R (x,)681 0 R (x,) +682 0 R (x,)683 0 R (x,)684 0 R (x,)685 0 R (x,) +686 0 R (x,)687 0 R (x,)688 0 R (x,)689 0 R (x,) +690 0 R (x,)691 0 R (x,)692 0 R (x,)693 0 R (x,) +694 0 R (x,)695 0 R (x,)696 0 R (x,)697 0 R (x,) +698 0 R (x,)699 0 R (x,)700 0 R (x,)701 0 R (x,) +702 0 R (x,)703 0 R (x,)704 0 R (x,)705 0 R (x,) +706 0 R (x,)707 0 R (x,)708 0 R (x,)709 0 R (x,) +710 0 R (x,)711 0 R (x,)712 0 R (x,)713 0 R (x,) +714 0 R (x,)715 0 R (x,)716 0 R (x,)717 0 R (x,) +718 0 R (x,)719 0 R (x,)720 0 R (x,)721 0 R (x,) +722 0 R (x,)723 0 R (x,)724 0 R (x,)725 0 R (x,) +726 0 R ] +>> +endobj +1716 0 obj +<< +/Limits [ (Dw{)(Dwp)] +/Names [ (Dw{)727 0 R (Dw{)728 0 R (Dw{)729 0 R (Dw{)730 0 R +(Dw{)731 0 R (Dw{)732 0 R (Dw{)580 0 R (Dws) +735 0 R (Dws)736 0 R (Dws)737 0 R (Dws)781 0 R (Dws) +782 0 R (Dws)783 0 R (Dws)784 0 R (Dws)785 0 R (Dws) +786 0 R (Dws)787 0 R (Dws)774 0 R (Dws)775 0 R (Dws) +776 0 R (Dws)777 0 R (Dws)778 0 R (Dws)779 0 R (Dws) +780 0 R (Dws)767 0 R (Dws)768 0 R (Dws)769 0 R (Dws) +770 0 R (Dws)771 0 R (Dws)772 0 R (Dws)773 0 R (Dws) +760 0 R (Dws)761 0 R (Dws)762 0 R (Dws)763 0 R (Dwp) +764 0 R (Dwp)765 0 R (Dwp)766 0 R (Dwp)753 0 R (Dwp) +754 0 R (Dwp)755 0 R (Dwp)756 0 R (Dwp)757 0 R (Dwp) +758 0 R (Dwp)759 0 R (Dwp)746 0 R (Dwp)747 0 R (Dwp) +748 0 R (Dwp)749 0 R (Dwp)750 0 R (Dwp)751 0 R (Dwp) +752 0 R (Dwp)739 0 R (Dwp)740 0 R (Dwp)741 0 R (Dwp) +742 0 R (Dwp)743 0 R (Dwp)744 0 R (Dwp)745 0 R (Dwp) +577 0 R (Dwp)578 0 R (Dwp)733 0 R (Dwp)734 0 R (Dwp) +568 0 R ] +>> +endobj +1717 0 obj +<< +/Limits [ ( N')(.D<1~)] +/Names [ ( N')790 0 R ( N')791 0 R ( N')792 0 R ( N')793 0 R +( N')798 0 R ( N')799 0 R ( N')800 0 R ( N') +801 0 R ( N')802 0 R ( N')803 0 R ( N')804 0 R ( N') +805 0 R ( N')806 0 R ( N')807 0 R ( N')808 0 R ( N') +809 0 R ( N')810 0 R ( N')811 0 R ( N')812 0 R ( N') +813 0 R ( N')814 0 R ( N')815 0 R ( N')816 0 R ( N') +817 0 R ( N')818 0 R ( N')819 0 R ( N')820 0 R ( N') +821 0 R ( N')822 0 R ( N')823 0 R ( N')824 0 R ( N') +825 0 R ( N')826 0 R ( N')827 0 R ( N')828 0 R ( N') +829 0 R ( N')830 0 R ( N')831 0 R ( N')794 0 R ( N') +795 0 R ( N')796 0 R ( N')797 0 R (.F<)214 0 R (.F#1v) +835 0 R (.D<;})333 0 R (.D<;z)334 0 R (.D<;x)335 0 R +(.D<;v)336 0 R (.D<2})337 0 R (.D<2{)338 0 R (.D<2|) +262 0 R (.D<2z)263 0 R (.D<2x)264 0 R (.D<2v)265 0 R +(.D<3~)266 0 R (.D<3|)267 0 R (.D<3z)268 0 R (.D<3x) +269 0 R (.D<3v)270 0 R (.D<0|)271 0 R (.D<0z)272 0 R +(.D<0x)273 0 R (.D<0v)274 0 R (.D<1~)275 0 R ] +>> +endobj +1718 0 obj +<< +/Limits [ (N1w@\()(J1rI5ASn8pfݚ\nJEh<LWW) +] +/Names [ (N1w@\()276 0 R (N1w@.)277 0 R (N1w@,)278 0 R (N1w@") +279 0 R (N1w@*)280 0 R (N1w@\()281 0 R (N1w@.) +282 0 R (N1w@\()283 0 R (N1w@.)284 0 R (N1w@,) +285 0 R (N1w@")286 0 R (N1w@*)287 0 R (N1w@\() +288 0 R (N1w@,)289 0 R (N1w@*)290 0 R (N1w@\() +330 0 R (N1w@.)332 0 R (N1w@")339 0 R (N1w@*)340 0 R +(N1w@.)341 0 R (N1w@,)342 0 R (N1w@.)343 0 R (N1w@,) +344 0 R (N1w@")345 0 R (N1w@-)323 0 R (N1w@")324 0 R +(N1w@*)325 0 R (N1w@/)326 0 R (N1w@,)327 0 R (N1w@*) +328 0 R (N1w@\()329 0 R (N1w@-)331 0 R (N1u@)382 0 R +(N1uH)393 0 R (N1u@)413 0 R (N1uC)415 0 R (N1u@) +448 0 R (N1uD)477 0 R (N1uD)483 0 R (N1u@)492 0 R +(N1u@)566 0 R (N1uF)576 0 R (N1uD)567 0 R (K) +229 0 R (K/)984 0 R (K.)1638 0 R (K-)1695 0 R (K)258 0 R (K) +322 0 R (K)410 0 R (K)434 0 R (K)489 0 R (K)534 0 R (K)788 0 R +(K)832 0 R (J1uG5IEi&M%MH7.k˓MDy=SK j#WDX) +213 0 R (J/hH-cY{,UM-\rhm>VЈW)834 0 R (J1tF5HP_ZzJ) +381 0 R (J1tF5HP_ZzJ)412 0 R (J1I5HPJ zP$`D1ekÏ\nrm&VV) +414 0 R (J1tF5HP_ZzJ)447 0 R (J1tF5HP_ZzJ)491 0 R +(J1tF5HP_ZzJ)565 0 R (J1rI5ASn8pfݚ\nJEh<LWW) +575 0 R ] +>> +endobj +1719 0 obj +<< +/Limits [ (˷)(˷)] +/Names [ (˷)379 0 R (˷)392 0 R (˷)400 0 R (˷)409 0 R (˷)924 0 R +(˷)943 0 R (˷)981 0 R (˷)983 0 R (˷)211 0 R (˷:)228 0 R +(˷:u)252 0 R (˷%)257 0 R (˷)321 0 R ] +>> +endobj +1720 0 obj +<< +/Kids [ 1696 0 R 1697 0 R 1698 0 R 1699 0 R 1700 0 R 1701 0 R 1702 0 R 1703 0 R +1704 0 R 1705 0 R 1706 0 R 1707 0 R 1708 0 R 1709 0 R 1710 0 R 1711 0 R +1712 0 R 1713 0 R 1714 0 R 1715 0 R 1716 0 R 1717 0 R 1718 0 R 1719 0 R +] +>> +endobj +1721 0 obj +<< +/Linearized 1 +/O 1720 +/H [ 3316 1052 ] +/L 287810 +/E 32243 +/N 34 +/T 253410 +>> +endobj +1722 0 obj +<< +/CreationDate (\)"x<]) +/Producer (pbA*_%MÜ!k̎RJ ) +/Author (vsF&HdʕFۀ{2) +/Title (r}K: IтMl>̻aVF",8 o) +/Creator (aqC-Jn^Ҝ:) +/ModDate (\)"x5]ӝ\(k) +/Subject (pdA*Y%) +>> +endobj +1723 0 obj +<< +/Type /Pages +/Kids [ 1735 0 R 1 0 R 6 0 R 10 0 R 46 0 R 74 0 R 78 0 R 82 0 R ] +/Count 8 +/Parent 1724 0 R +>> +endobj +1724 0 obj +<< +/Type /Pages +/Kids [ 1723 0 R 1725 0 R 1726 0 R 1727 0 R 1728 0 R ] +/Count 34 +>> +endobj +1725 0 obj +<< +/Type /Pages +/Kids [ 86 0 R 90 0 R 94 0 R 98 0 R 102 0 R 106 0 R 110 0 R 114 0 R 118 0 R +] +/Count 9 +/Parent 1724 0 R +>> +endobj +1726 0 obj +<< +/Type /Pages +/Kids [ 122 0 R 126 0 R 130 0 R 134 0 R 138 0 R 142 0 R 146 0 R 150 0 R ] +/Count 8 +/Parent 1724 0 R +>> +endobj +1727 0 obj +<< +/Type /Pages +/Kids [ 154 0 R 158 0 R 162 0 R 166 0 R 170 0 R 174 0 R 178 0 R 182 0 R ] +/Count 8 +/Parent 1724 0 R +>> +endobj +1728 0 obj +<< +/Type /Pages +/Kids [ 186 0 R ] +/Count 1 +/Parent 1724 0 R +>> +endobj +xref +0 1729 +0000000000 65535 f +0000027552 00000 n +0000027744 00000 n +0000027857 00000 n +0000028015 00000 n +0000029714 00000 n +0000029791 00000 n +0000029991 00000 n +0000030166 00000 n +0000030329 00000 n +0000031064 00000 n +0000031474 00000 n +0000031592 00000 n +0000031710 00000 n +0000031828 00000 n +0000031944 00000 n +0000032061 00000 n +0000032178 00000 n +0000032295 00000 n +0000032412 00000 n +0000032530 00000 n +0000032647 00000 n +0000032764 00000 n +0000032881 00000 n +0000032998 00000 n +0000033115 00000 n +0000033232 00000 n +0000033349 00000 n +0000033466 00000 n +0000033583 00000 n +0000033701 00000 n +0000033818 00000 n +0000033935 00000 n +0000034052 00000 n +0000034170 00000 n +0000034287 00000 n +0000034404 00000 n +0000034521 00000 n +0000034638 00000 n +0000034755 00000 n +0000034872 00000 n +0000035048 00000 n +0000035212 00000 n +0000036488 00000 n +0000036541 00000 n +0000036594 00000 n +0000036647 00000 n +0000037012 00000 n +0000037129 00000 n +0000037245 00000 n +0000037361 00000 n +0000037477 00000 n +0000037594 00000 n +0000037711 00000 n +0000037827 00000 n +0000037944 00000 n +0000038060 00000 n +0000038176 00000 n +0000038292 00000 n +0000038408 00000 n +0000038525 00000 n +0000038642 00000 n +0000038759 00000 n +0000038876 00000 n +0000038994 00000 n +0000039111 00000 n +0000039228 00000 n +0000039345 00000 n +0000039462 00000 n +0000039579 00000 n +0000039696 00000 n +0000039814 00000 n +0000039989 00000 n +0000040153 00000 n +0000041418 00000 n +0000041622 00000 n +0000041796 00000 n +0000041973 00000 n +0000044071 00000 n +0000044266 00000 n +0000044440 00000 n +0000044655 00000 n +0000050759 00000 n +0000050954 00000 n +0000051130 00000 n +0000051306 00000 n +0000052188 00000 n +0000052392 00000 n +0000052568 00000 n +0000052770 00000 n +0000054720 00000 n +0000054915 00000 n +0000055091 00000 n +0000055280 00000 n +0000056965 00000 n +0000057169 00000 n +0000057345 00000 n +0000057561 00000 n +0000059397 00000 n +0000059594 00000 n +0000059767 00000 n +0000059983 00000 n +0000062541 00000 n +0000062740 00000 n +0000062915 00000 n +0000063106 00000 n +0000067310 00000 n +0000067518 00000 n +0000067694 00000 n +0000067925 00000 n +0000071128 00000 n +0000071327 00000 n +0000071503 00000 n +0000071694 00000 n +0000072776 00000 n +0000072984 00000 n +0000073159 00000 n +0000073375 00000 n +0000077364 00000 n +0000077563 00000 n +0000077737 00000 n +0000077941 00000 n +0000080848 00000 n +0000081047 00000 n +0000081223 00000 n +0000081440 00000 n +0000085349 00000 n +0000085557 00000 n +0000085734 00000 n +0000085938 00000 n +0000087990 00000 n +0000088198 00000 n +0000088374 00000 n +0000088576 00000 n +0000089902 00000 n +0000090101 00000 n +0000090277 00000 n +0000090493 00000 n +0000092181 00000 n +0000092380 00000 n +0000092557 00000 n +0000092759 00000 n +0000094741 00000 n +0000094940 00000 n +0000095114 00000 n +0000095316 00000 n +0000097174 00000 n +0000097373 00000 n +0000097550 00000 n +0000097752 00000 n +0000099077 00000 n +0000099276 00000 n +0000099450 00000 n +0000099627 00000 n +0000100491 00000 n +0000100690 00000 n +0000100866 00000 n +0000101056 00000 n +0000103409 00000 n +0000103617 00000 n +0000103793 00000 n +0000103997 00000 n +0000106629 00000 n +0000106828 00000 n +0000107002 00000 n +0000107193 00000 n +0000110314 00000 n +0000110513 00000 n +0000110690 00000 n +0000110881 00000 n +0000113463 00000 n +0000113662 00000 n +0000113838 00000 n +0000114029 00000 n +0000116837 00000 n +0000117036 00000 n +0000117213 00000 n +0000117404 00000 n +0000119400 00000 n +0000119608 00000 n +0000119783 00000 n +0000120012 00000 n +0000123971 00000 n +0000124170 00000 n +0000124344 00000 n +0000124574 00000 n +0000126106 00000 n +0000126305 00000 n +0000126484 00000 n +0000126675 00000 n +0000127664 00000 n +0000127771 00000 n +0000127878 00000 n +0000127983 00000 n +0000128096 00000 n +0000128174 00000 n +0000128282 00000 n +0000128388 00000 n +0000128498 00000 n +0000128601 00000 n +0000128688 00000 n +0000128998 00000 n +0000129462 00000 n +0000129844 00000 n +0000132779 00000 n +0000132960 00000 n +0000133365 00000 n +0000133662 00000 n +0000135163 00000 n +0000135599 00000 n +0000135926 00000 n +0000138538 00000 n +0000138600 00000 n +0000138662 00000 n +0000138722 00000 n +0000138782 00000 n +0000138842 00000 n +0000138902 00000 n +0000138962 00000 n +0000139022 00000 n +0000139082 00000 n +0000139142 00000 n +0000139202 00000 n +0000139262 00000 n +0000139322 00000 n +0000139382 00000 n +0000139442 00000 n +0000139502 00000 n +0000139562 00000 n +0000139621 00000 n +0000139680 00000 n +0000139737 00000 n +0000139794 00000 n +0000139851 00000 n +0000139908 00000 n +0000139965 00000 n +0000140022 00000 n +0000140079 00000 n +0000140136 00000 n +0000140193 00000 n +0000140250 00000 n +0000140307 00000 n +0000140364 00000 n +0000140421 00000 n +0000140478 00000 n +0000140535 00000 n +0000140592 00000 n +0000140649 00000 n +0000140706 00000 n +0000140763 00000 n +0000140820 00000 n +0000140877 00000 n +0000140934 00000 n +0000140993 00000 n +0000141052 00000 n +0000141109 00000 n +0000141166 00000 n +0000141223 00000 n +0000141285 00000 n +0000141347 00000 n +0000141406 00000 n +0000141465 00000 n +0000141525 00000 n +0000141583 00000 n +0000141641 00000 n +0000141699 00000 n +0000141757 00000 n +0000141815 00000 n +0000141873 00000 n +0000141931 00000 n +0000141989 00000 n +0000142047 00000 n +0000142105 00000 n +0000142163 00000 n +0000142221 00000 n +0000142279 00000 n +0000142337 00000 n +0000142395 00000 n +0000142453 00000 n +0000142511 00000 n +0000142569 00000 n +0000142627 00000 n +0000142685 00000 n +0000142743 00000 n +0000142801 00000 n +0000142859 00000 n +0000142917 00000 n +0000142975 00000 n +0000143033 00000 n +0000143091 00000 n +0000143149 00000 n +0000143207 00000 n +0000143265 00000 n +0000143323 00000 n +0000143381 00000 n +0000143439 00000 n +0000143497 00000 n +0000143555 00000 n +0000143613 00000 n +0000143671 00000 n +0000143729 00000 n +0000143787 00000 n +0000143845 00000 n +0000143903 00000 n +0000143961 00000 n +0000144019 00000 n +0000144077 00000 n +0000144135 00000 n +0000144193 00000 n +0000144251 00000 n +0000144309 00000 n +0000144367 00000 n +0000144425 00000 n +0000144483 00000 n +0000144541 00000 n +0000144599 00000 n +0000144657 00000 n +0000144715 00000 n +0000144773 00000 n +0000144831 00000 n +0000144889 00000 n +0000144947 00000 n +0000145007 00000 n +0000145067 00000 n +0000145125 00000 n +0000145183 00000 n +0000145241 00000 n +0000145299 00000 n +0000145357 00000 n +0000145415 00000 n +0000145473 00000 n +0000145530 00000 n +0000145588 00000 n +0000145645 00000 n +0000145703 00000 n +0000145761 00000 n +0000145819 00000 n +0000145877 00000 n +0000145935 00000 n +0000145993 00000 n +0000146050 00000 n +0000146107 00000 n +0000146164 00000 n +0000146221 00000 n +0000146278 00000 n +0000146335 00000 n +0000146393 00000 n +0000146450 00000 n +0000146507 00000 n +0000146564 00000 n +0000146621 00000 n +0000146678 00000 n +0000146735 00000 n +0000146792 00000 n +0000146849 00000 n +0000146906 00000 n +0000146963 00000 n +0000147020 00000 n +0000147077 00000 n +0000147134 00000 n +0000147191 00000 n +0000147248 00000 n +0000147305 00000 n +0000147362 00000 n +0000147419 00000 n +0000147476 00000 n +0000147533 00000 n +0000147590 00000 n +0000147647 00000 n +0000147704 00000 n +0000147761 00000 n +0000147818 00000 n +0000147875 00000 n +0000147932 00000 n +0000147989 00000 n +0000148046 00000 n +0000148103 00000 n +0000148160 00000 n +0000148217 00000 n +0000148274 00000 n +0000148334 00000 n +0000148394 00000 n +0000148452 00000 n +0000148510 00000 n +0000148568 00000 n +0000148626 00000 n +0000148684 00000 n +0000148742 00000 n +0000148800 00000 n +0000148858 00000 n +0000148916 00000 n +0000148974 00000 n +0000149032 00000 n +0000149092 00000 n +0000149150 00000 n +0000149207 00000 n +0000149264 00000 n +0000149321 00000 n +0000149378 00000 n +0000149435 00000 n +0000149492 00000 n +0000149552 00000 n +0000149610 00000 n +0000149668 00000 n +0000149726 00000 n +0000149784 00000 n +0000149842 00000 n +0000149900 00000 n +0000149958 00000 n +0000150016 00000 n +0000150078 00000 n +0000150140 00000 n +0000150200 00000 n +0000150258 00000 n +0000150316 00000 n +0000150374 00000 n +0000150432 00000 n +0000150490 00000 n +0000150548 00000 n +0000150606 00000 n +0000150664 00000 n +0000150722 00000 n +0000150780 00000 n +0000150838 00000 n +0000150896 00000 n +0000150954 00000 n +0000151012 00000 n +0000151070 00000 n +0000151128 00000 n +0000151186 00000 n +0000151244 00000 n +0000151302 00000 n +0000151360 00000 n +0000151418 00000 n +0000151476 00000 n +0000151536 00000 n +0000151593 00000 n +0000151650 00000 n +0000151707 00000 n +0000151764 00000 n +0000151821 00000 n +0000151878 00000 n +0000151935 00000 n +0000151992 00000 n +0000152049 00000 n +0000152106 00000 n +0000152163 00000 n +0000152223 00000 n +0000152281 00000 n +0000152339 00000 n +0000152397 00000 n +0000152455 00000 n +0000152513 00000 n +0000152571 00000 n +0000152629 00000 n +0000152687 00000 n +0000152745 00000 n +0000152803 00000 n +0000152861 00000 n +0000152919 00000 n +0000152977 00000 n +0000153035 00000 n +0000153093 00000 n +0000153151 00000 n +0000153209 00000 n +0000153267 00000 n +0000153325 00000 n +0000153383 00000 n +0000153441 00000 n +0000153499 00000 n +0000153557 00000 n +0000153615 00000 n +0000153673 00000 n +0000153731 00000 n +0000153789 00000 n +0000153847 00000 n +0000153905 00000 n +0000153963 00000 n +0000154021 00000 n +0000154078 00000 n +0000154135 00000 n +0000154192 00000 n +0000154249 00000 n +0000154306 00000 n +0000154365 00000 n +0000154424 00000 n +0000154483 00000 n +0000154542 00000 n +0000154601 00000 n +0000154660 00000 n +0000154722 00000 n +0000154783 00000 n +0000154842 00000 n +0000154901 00000 n +0000154960 00000 n +0000155019 00000 n +0000155078 00000 n +0000155137 00000 n +0000155196 00000 n +0000155255 00000 n +0000155314 00000 n +0000155373 00000 n +0000155432 00000 n +0000155491 00000 n +0000155550 00000 n +0000155609 00000 n +0000155668 00000 n +0000155727 00000 n +0000155786 00000 n +0000155845 00000 n +0000155904 00000 n +0000155963 00000 n +0000156022 00000 n +0000156081 00000 n +0000156140 00000 n +0000156199 00000 n +0000156258 00000 n +0000156317 00000 n +0000156376 00000 n +0000156435 00000 n +0000156494 00000 n +0000156553 00000 n +0000156612 00000 n +0000156671 00000 n +0000156730 00000 n +0000156789 00000 n +0000156848 00000 n +0000156907 00000 n +0000156966 00000 n +0000157025 00000 n +0000157084 00000 n +0000157143 00000 n +0000157202 00000 n +0000157261 00000 n +0000157320 00000 n +0000157381 00000 n +0000157439 00000 n +0000157497 00000 n +0000157555 00000 n +0000157614 00000 n +0000157673 00000 n +0000157732 00000 n +0000157791 00000 n +0000157850 00000 n +0000157909 00000 n +0000157968 00000 n +0000158027 00000 n +0000158086 00000 n +0000158145 00000 n +0000158204 00000 n +0000158263 00000 n +0000158322 00000 n +0000158381 00000 n +0000158440 00000 n +0000158499 00000 n +0000158558 00000 n +0000158617 00000 n +0000158676 00000 n +0000158735 00000 n +0000158794 00000 n +0000158853 00000 n +0000158912 00000 n +0000158971 00000 n +0000159030 00000 n +0000159089 00000 n +0000159150 00000 n +0000159209 00000 n +0000159268 00000 n +0000159327 00000 n +0000159386 00000 n +0000159445 00000 n +0000159504 00000 n +0000159563 00000 n +0000159622 00000 n +0000159681 00000 n +0000159740 00000 n +0000159799 00000 n +0000159858 00000 n +0000159916 00000 n +0000159974 00000 n +0000160032 00000 n +0000160090 00000 n +0000160148 00000 n +0000160206 00000 n +0000160264 00000 n +0000160323 00000 n +0000160382 00000 n +0000160440 00000 n +0000160499 00000 n +0000160558 00000 n +0000160617 00000 n +0000160676 00000 n +0000160735 00000 n +0000160794 00000 n +0000160852 00000 n +0000160911 00000 n +0000160970 00000 n +0000161029 00000 n +0000161088 00000 n +0000161147 00000 n +0000161206 00000 n +0000161264 00000 n +0000161323 00000 n +0000161382 00000 n +0000161441 00000 n +0000161500 00000 n +0000161559 00000 n +0000161618 00000 n +0000161676 00000 n +0000161735 00000 n +0000161794 00000 n +0000161853 00000 n +0000161912 00000 n +0000161971 00000 n +0000162030 00000 n +0000162088 00000 n +0000162147 00000 n +0000162206 00000 n +0000162265 00000 n +0000162324 00000 n +0000162383 00000 n +0000162442 00000 n +0000162500 00000 n +0000162559 00000 n +0000162618 00000 n +0000162677 00000 n +0000162736 00000 n +0000162795 00000 n +0000162854 00000 n +0000162912 00000 n +0000162971 00000 n +0000163030 00000 n +0000163089 00000 n +0000163148 00000 n +0000163207 00000 n +0000163266 00000 n +0000163324 00000 n +0000163383 00000 n +0000163442 00000 n +0000163501 00000 n +0000163560 00000 n +0000163619 00000 n +0000163678 00000 n +0000163736 00000 n +0000163795 00000 n +0000163854 00000 n +0000163913 00000 n +0000163972 00000 n +0000164031 00000 n +0000164090 00000 n +0000164148 00000 n +0000164207 00000 n +0000164266 00000 n +0000164325 00000 n +0000164384 00000 n +0000164443 00000 n +0000164502 00000 n +0000164560 00000 n +0000164619 00000 n +0000164678 00000 n +0000164737 00000 n +0000164796 00000 n +0000164855 00000 n +0000164914 00000 n +0000164972 00000 n +0000165031 00000 n +0000165090 00000 n +0000165149 00000 n +0000165208 00000 n +0000165267 00000 n +0000165326 00000 n +0000165384 00000 n +0000165443 00000 n +0000165502 00000 n +0000165561 00000 n +0000165620 00000 n +0000165679 00000 n +0000165738 00000 n +0000165796 00000 n +0000165855 00000 n +0000165914 00000 n +0000165973 00000 n +0000166032 00000 n +0000166091 00000 n +0000166150 00000 n +0000166208 00000 n +0000166267 00000 n +0000166326 00000 n +0000166385 00000 n +0000166444 00000 n +0000166503 00000 n +0000166562 00000 n +0000166620 00000 n +0000166679 00000 n +0000166738 00000 n +0000166797 00000 n +0000166856 00000 n +0000166915 00000 n +0000166974 00000 n +0000167032 00000 n +0000167091 00000 n +0000167150 00000 n +0000167209 00000 n +0000167268 00000 n +0000167327 00000 n +0000167386 00000 n +0000167444 00000 n +0000167503 00000 n +0000167562 00000 n +0000167621 00000 n +0000167680 00000 n +0000167739 00000 n +0000167798 00000 n +0000167856 00000 n +0000167915 00000 n +0000167974 00000 n +0000168033 00000 n +0000168092 00000 n +0000168151 00000 n +0000168210 00000 n +0000168268 00000 n +0000168327 00000 n +0000168386 00000 n +0000168445 00000 n +0000168504 00000 n +0000168563 00000 n +0000168622 00000 n +0000168680 00000 n +0000168739 00000 n +0000168798 00000 n +0000168857 00000 n +0000168916 00000 n +0000168975 00000 n +0000169034 00000 n +0000169093 00000 n +0000169152 00000 n +0000169211 00000 n +0000169270 00000 n +0000169329 00000 n +0000169388 00000 n +0000169447 00000 n +0000169506 00000 n +0000169565 00000 n +0000169624 00000 n +0000169683 00000 n +0000169742 00000 n +0000169801 00000 n +0000169860 00000 n +0000169919 00000 n +0000169978 00000 n +0000170037 00000 n +0000170096 00000 n +0000170155 00000 n +0000170214 00000 n +0000170273 00000 n +0000170332 00000 n +0000170391 00000 n +0000170450 00000 n +0000170509 00000 n +0000170568 00000 n +0000170627 00000 n +0000170686 00000 n +0000170745 00000 n +0000170804 00000 n +0000170863 00000 n +0000170922 00000 n +0000170981 00000 n +0000171040 00000 n +0000171099 00000 n +0000171158 00000 n +0000171217 00000 n +0000171276 00000 n +0000171335 00000 n +0000171394 00000 n +0000171453 00000 n +0000171512 00000 n +0000171571 00000 n +0000171630 00000 n +0000171689 00000 n +0000171748 00000 n +0000171807 00000 n +0000171866 00000 n +0000171925 00000 n +0000171984 00000 n +0000172043 00000 n +0000172102 00000 n +0000172161 00000 n +0000172220 00000 n +0000172279 00000 n +0000172341 00000 n +0000172402 00000 n +0000172461 00000 n +0000172520 00000 n +0000172579 00000 n +0000172638 00000 n +0000172697 00000 n +0000172756 00000 n +0000172815 00000 n +0000172874 00000 n +0000172933 00000 n +0000172992 00000 n +0000173051 00000 n +0000173110 00000 n +0000173169 00000 n +0000173228 00000 n +0000173287 00000 n +0000173346 00000 n +0000173405 00000 n +0000173464 00000 n +0000173523 00000 n +0000173582 00000 n +0000173641 00000 n +0000173700 00000 n +0000173759 00000 n +0000173818 00000 n +0000173877 00000 n +0000173936 00000 n +0000173995 00000 n +0000174054 00000 n +0000174113 00000 n +0000174172 00000 n +0000174231 00000 n +0000174290 00000 n +0000174349 00000 n +0000174408 00000 n +0000174467 00000 n +0000174526 00000 n +0000174585 00000 n +0000174644 00000 n +0000174703 00000 n +0000174762 00000 n +0000174821 00000 n +0000174880 00000 n +0000174938 00000 n +0000174999 00000 n +0000175058 00000 n +0000175117 00000 n +0000175176 00000 n +0000175235 00000 n +0000175294 00000 n +0000175353 00000 n +0000175412 00000 n +0000175471 00000 n +0000175530 00000 n +0000175589 00000 n +0000175648 00000 n +0000175706 00000 n +0000175764 00000 n +0000175822 00000 n +0000175880 00000 n +0000175938 00000 n +0000175996 00000 n +0000176054 00000 n +0000176112 00000 n +0000176170 00000 n +0000176228 00000 n +0000176286 00000 n +0000176344 00000 n +0000176402 00000 n +0000176460 00000 n +0000176519 00000 n +0000176578 00000 n +0000176637 00000 n +0000176696 00000 n +0000176755 00000 n +0000176814 00000 n +0000176873 00000 n +0000176932 00000 n +0000176991 00000 n +0000177050 00000 n +0000177109 00000 n +0000177168 00000 n +0000177227 00000 n +0000177286 00000 n +0000177345 00000 n +0000177404 00000 n +0000177463 00000 n +0000177522 00000 n +0000177581 00000 n +0000177640 00000 n +0000177699 00000 n +0000177758 00000 n +0000177817 00000 n +0000177876 00000 n +0000177935 00000 n +0000177994 00000 n +0000178053 00000 n +0000178112 00000 n +0000178171 00000 n +0000178230 00000 n +0000178289 00000 n +0000178348 00000 n +0000178407 00000 n +0000178466 00000 n +0000178525 00000 n +0000178584 00000 n +0000178643 00000 n +0000178702 00000 n +0000178760 00000 n +0000178818 00000 n +0000178876 00000 n +0000178934 00000 n +0000178992 00000 n +0000179050 00000 n +0000179108 00000 n +0000179166 00000 n +0000179224 00000 n +0000179282 00000 n +0000179340 00000 n +0000179398 00000 n +0000179457 00000 n +0000179516 00000 n +0000179575 00000 n +0000179634 00000 n +0000179693 00000 n +0000179752 00000 n +0000179811 00000 n +0000179870 00000 n +0000179929 00000 n +0000179988 00000 n +0000180047 00000 n +0000180106 00000 n +0000180165 00000 n +0000180224 00000 n +0000180283 00000 n +0000180344 00000 n +0000180403 00000 n +0000180462 00000 n +0000180521 00000 n +0000180580 00000 n +0000180639 00000 n +0000180698 00000 n +0000180757 00000 n +0000180816 00000 n +0000180875 00000 n +0000180934 00000 n +0000180993 00000 n +0000181052 00000 n +0000181111 00000 n +0000181170 00000 n +0000181229 00000 n +0000181288 00000 n +0000181347 00000 n +0000181406 00000 n +0000181467 00000 n +0000181525 00000 n +0000181583 00000 n +0000181641 00000 n +0000181699 00000 n +0000181757 00000 n +0000181815 00000 n +0000181873 00000 n +0000181931 00000 n +0000181989 00000 n +0000182047 00000 n +0000182105 00000 n +0000182163 00000 n +0000182221 00000 n +0000182279 00000 n +0000182337 00000 n +0000182395 00000 n +0000182453 00000 n +0000182511 00000 n +0000182569 00000 n +0000182627 00000 n +0000182685 00000 n +0000182743 00000 n +0000182801 00000 n +0000182859 00000 n +0000182917 00000 n +0000182975 00000 n +0000183033 00000 n +0000183091 00000 n +0000183149 00000 n +0000183207 00000 n +0000183265 00000 n +0000183323 00000 n +0000183381 00000 n +0000183439 00000 n +0000183497 00000 n +0000183555 00000 n +0000183613 00000 n +0000183674 00000 n +0000183733 00000 n +0000183791 00000 n +0000183849 00000 n +0000183910 00000 n +0000183969 00000 n +0000184028 00000 n +0000184087 00000 n +0000184146 00000 n +0000184205 00000 n +0000184264 00000 n +0000184323 00000 n +0000184382 00000 n +0000184441 00000 n +0000184500 00000 n +0000184559 00000 n +0000184618 00000 n +0000184677 00000 n +0000184736 00000 n +0000184796 00000 n +0000184856 00000 n +0000184916 00000 n +0000184976 00000 n +0000185036 00000 n +0000185096 00000 n +0000185156 00000 n +0000185216 00000 n +0000185276 00000 n +0000185336 00000 n +0000185396 00000 n +0000185456 00000 n +0000185516 00000 n +0000185576 00000 n +0000185636 00000 n +0000185696 00000 n +0000185756 00000 n +0000185816 00000 n +0000185876 00000 n +0000185936 00000 n +0000185996 00000 n +0000186056 00000 n +0000186116 00000 n +0000186176 00000 n +0000186236 00000 n +0000186296 00000 n +0000186356 00000 n +0000186416 00000 n +0000186476 00000 n +0000186536 00000 n +0000186596 00000 n +0000186656 00000 n +0000186716 00000 n +0000186776 00000 n +0000186836 00000 n +0000186896 00000 n +0000186956 00000 n +0000187016 00000 n +0000187076 00000 n +0000187136 00000 n +0000187196 00000 n +0000187256 00000 n +0000187316 00000 n +0000187376 00000 n +0000187436 00000 n +0000187496 00000 n +0000187556 00000 n +0000187616 00000 n +0000187676 00000 n +0000187736 00000 n +0000187796 00000 n +0000187856 00000 n +0000187916 00000 n +0000187976 00000 n +0000188036 00000 n +0000188096 00000 n +0000188156 00000 n +0000188216 00000 n +0000188276 00000 n +0000188336 00000 n +0000188396 00000 n +0000188456 00000 n +0000188516 00000 n +0000188576 00000 n +0000188636 00000 n +0000188696 00000 n +0000188756 00000 n +0000188816 00000 n +0000188876 00000 n +0000188936 00000 n +0000188996 00000 n +0000189056 00000 n +0000189116 00000 n +0000189176 00000 n +0000189236 00000 n +0000189296 00000 n +0000189356 00000 n +0000189416 00000 n +0000189476 00000 n +0000189536 00000 n +0000189596 00000 n +0000189656 00000 n +0000189716 00000 n +0000189776 00000 n +0000189836 00000 n +0000189896 00000 n +0000189956 00000 n +0000190016 00000 n +0000190076 00000 n +0000190136 00000 n +0000190196 00000 n +0000190256 00000 n +0000190316 00000 n +0000190376 00000 n +0000190436 00000 n +0000190496 00000 n +0000190556 00000 n +0000190616 00000 n +0000190676 00000 n +0000190736 00000 n +0000190796 00000 n +0000190856 00000 n +0000190916 00000 n +0000190976 00000 n +0000191036 00000 n +0000191096 00000 n +0000191156 00000 n +0000191216 00000 n +0000191276 00000 n +0000191336 00000 n +0000191396 00000 n +0000191456 00000 n +0000191516 00000 n +0000191576 00000 n +0000191636 00000 n +0000191696 00000 n +0000191756 00000 n +0000191816 00000 n +0000191876 00000 n +0000191936 00000 n +0000191996 00000 n +0000192056 00000 n +0000192116 00000 n +0000192176 00000 n +0000192236 00000 n +0000192295 00000 n +0000192354 00000 n +0000192413 00000 n +0000192472 00000 n +0000192532 00000 n +0000192592 00000 n +0000192652 00000 n +0000192712 00000 n +0000192772 00000 n +0000192832 00000 n +0000192891 00000 n +0000192951 00000 n +0000193011 00000 n +0000193071 00000 n +0000193131 00000 n +0000193191 00000 n +0000193251 00000 n +0000193310 00000 n +0000193370 00000 n +0000193430 00000 n +0000193490 00000 n +0000193550 00000 n +0000193610 00000 n +0000193670 00000 n +0000193729 00000 n +0000193789 00000 n +0000193849 00000 n +0000193909 00000 n +0000193969 00000 n +0000194029 00000 n +0000194089 00000 n +0000194148 00000 n +0000194208 00000 n +0000194268 00000 n +0000194328 00000 n +0000194388 00000 n +0000194448 00000 n +0000194508 00000 n +0000194567 00000 n +0000194627 00000 n +0000194687 00000 n +0000194747 00000 n +0000194807 00000 n +0000194867 00000 n +0000194927 00000 n +0000194986 00000 n +0000195046 00000 n +0000195106 00000 n +0000195166 00000 n +0000195226 00000 n +0000195286 00000 n +0000195346 00000 n +0000195406 00000 n +0000195466 00000 n +0000195526 00000 n +0000195586 00000 n +0000195646 00000 n +0000195706 00000 n +0000195766 00000 n +0000195826 00000 n +0000195886 00000 n +0000195946 00000 n +0000196006 00000 n +0000196066 00000 n +0000196126 00000 n +0000196186 00000 n +0000196246 00000 n +0000196306 00000 n +0000196366 00000 n +0000196426 00000 n +0000196486 00000 n +0000196546 00000 n +0000196606 00000 n +0000196666 00000 n +0000196726 00000 n +0000196786 00000 n +0000196846 00000 n +0000196906 00000 n +0000196966 00000 n +0000197026 00000 n +0000197086 00000 n +0000197146 00000 n +0000197206 00000 n +0000197266 00000 n +0000197326 00000 n +0000197386 00000 n +0000197446 00000 n +0000197506 00000 n +0000197566 00000 n +0000197626 00000 n +0000197686 00000 n +0000197746 00000 n +0000197806 00000 n +0000197866 00000 n +0000197926 00000 n +0000197986 00000 n +0000198046 00000 n +0000198106 00000 n +0000198166 00000 n +0000198226 00000 n +0000198286 00000 n +0000198346 00000 n +0000198406 00000 n +0000198466 00000 n +0000198526 00000 n +0000198586 00000 n +0000198646 00000 n +0000198706 00000 n +0000198766 00000 n +0000198826 00000 n +0000198886 00000 n +0000198946 00000 n +0000199006 00000 n +0000199066 00000 n +0000199126 00000 n +0000199186 00000 n +0000199246 00000 n +0000199306 00000 n +0000199366 00000 n +0000199426 00000 n +0000199486 00000 n +0000199546 00000 n +0000199606 00000 n +0000199666 00000 n +0000199726 00000 n +0000199786 00000 n +0000199846 00000 n +0000199906 00000 n +0000199966 00000 n +0000200026 00000 n +0000200086 00000 n +0000200146 00000 n +0000200206 00000 n +0000200266 00000 n +0000200326 00000 n +0000200386 00000 n +0000200446 00000 n +0000200506 00000 n +0000200566 00000 n +0000200626 00000 n +0000200686 00000 n +0000200746 00000 n +0000200806 00000 n +0000200866 00000 n +0000200926 00000 n +0000200986 00000 n +0000201046 00000 n +0000201106 00000 n +0000201166 00000 n +0000201226 00000 n +0000201286 00000 n +0000201346 00000 n +0000201406 00000 n +0000201466 00000 n +0000201526 00000 n +0000201586 00000 n +0000201646 00000 n +0000201706 00000 n +0000201766 00000 n +0000201826 00000 n +0000201886 00000 n +0000201946 00000 n +0000202006 00000 n +0000202066 00000 n +0000202126 00000 n +0000202186 00000 n +0000202246 00000 n +0000202306 00000 n +0000202366 00000 n +0000202426 00000 n +0000202486 00000 n +0000202546 00000 n +0000202606 00000 n +0000202666 00000 n +0000202726 00000 n +0000202786 00000 n +0000202846 00000 n +0000202906 00000 n +0000202966 00000 n +0000203026 00000 n +0000203086 00000 n +0000203146 00000 n +0000203206 00000 n +0000203266 00000 n +0000203326 00000 n +0000203386 00000 n +0000203446 00000 n +0000203506 00000 n +0000203566 00000 n +0000203626 00000 n +0000203686 00000 n +0000203746 00000 n +0000203806 00000 n +0000203866 00000 n +0000203926 00000 n +0000203986 00000 n +0000204046 00000 n +0000204106 00000 n +0000204166 00000 n +0000204226 00000 n +0000204286 00000 n +0000204346 00000 n +0000204406 00000 n +0000204466 00000 n +0000204526 00000 n +0000204586 00000 n +0000204646 00000 n +0000204706 00000 n +0000204766 00000 n +0000204826 00000 n +0000204886 00000 n +0000204946 00000 n +0000205006 00000 n +0000205066 00000 n +0000205126 00000 n +0000205186 00000 n +0000205246 00000 n +0000205306 00000 n +0000205366 00000 n +0000205426 00000 n +0000205486 00000 n +0000205546 00000 n +0000205606 00000 n +0000205666 00000 n +0000205726 00000 n +0000205786 00000 n +0000205846 00000 n +0000205906 00000 n +0000205966 00000 n +0000206026 00000 n +0000206086 00000 n +0000206146 00000 n +0000206206 00000 n +0000206266 00000 n +0000206326 00000 n +0000206386 00000 n +0000206446 00000 n +0000206506 00000 n +0000206566 00000 n +0000206626 00000 n +0000206686 00000 n +0000206746 00000 n +0000206806 00000 n +0000206866 00000 n +0000206926 00000 n +0000206986 00000 n +0000207046 00000 n +0000207106 00000 n +0000207166 00000 n +0000207226 00000 n +0000207286 00000 n +0000207346 00000 n +0000207406 00000 n +0000207466 00000 n +0000207526 00000 n +0000207586 00000 n +0000207646 00000 n +0000207706 00000 n +0000207766 00000 n +0000207826 00000 n +0000207886 00000 n +0000207946 00000 n +0000208006 00000 n +0000208066 00000 n +0000208126 00000 n +0000208186 00000 n +0000208246 00000 n +0000208306 00000 n +0000208366 00000 n +0000208426 00000 n +0000208486 00000 n +0000208546 00000 n +0000208606 00000 n +0000208666 00000 n +0000208726 00000 n +0000208786 00000 n +0000208846 00000 n +0000208906 00000 n +0000208966 00000 n +0000209026 00000 n +0000209086 00000 n +0000209146 00000 n +0000209206 00000 n +0000209266 00000 n +0000209325 00000 n +0000209385 00000 n +0000209445 00000 n +0000209505 00000 n +0000209565 00000 n +0000209625 00000 n +0000209685 00000 n +0000209745 00000 n +0000209805 00000 n +0000209865 00000 n +0000209925 00000 n +0000209985 00000 n +0000210045 00000 n +0000210105 00000 n +0000210165 00000 n +0000210225 00000 n +0000210285 00000 n +0000210345 00000 n +0000210405 00000 n +0000210465 00000 n +0000210525 00000 n +0000210585 00000 n +0000210645 00000 n +0000210705 00000 n +0000210765 00000 n +0000210825 00000 n +0000210885 00000 n +0000210945 00000 n +0000211005 00000 n +0000211065 00000 n +0000211125 00000 n +0000211185 00000 n +0000211245 00000 n +0000211305 00000 n +0000211365 00000 n +0000211425 00000 n +0000211485 00000 n +0000211545 00000 n +0000211605 00000 n +0000211665 00000 n +0000211725 00000 n +0000211785 00000 n +0000211845 00000 n +0000211905 00000 n +0000211965 00000 n +0000212025 00000 n +0000212085 00000 n +0000212145 00000 n +0000212205 00000 n +0000212265 00000 n +0000212325 00000 n +0000212385 00000 n +0000212445 00000 n +0000212505 00000 n +0000212565 00000 n +0000212625 00000 n +0000212685 00000 n +0000212745 00000 n +0000212805 00000 n +0000212865 00000 n +0000212925 00000 n +0000212985 00000 n +0000213045 00000 n +0000213105 00000 n +0000213165 00000 n +0000213225 00000 n +0000213285 00000 n +0000213345 00000 n +0000213405 00000 n +0000213465 00000 n +0000213525 00000 n +0000213585 00000 n +0000213645 00000 n +0000213705 00000 n +0000213765 00000 n +0000213825 00000 n +0000213885 00000 n +0000213945 00000 n +0000214005 00000 n +0000214065 00000 n +0000214125 00000 n +0000214185 00000 n +0000214245 00000 n +0000214305 00000 n +0000214365 00000 n +0000214425 00000 n +0000214485 00000 n +0000214545 00000 n +0000214605 00000 n +0000214665 00000 n +0000214725 00000 n +0000214785 00000 n +0000214845 00000 n +0000214905 00000 n +0000214965 00000 n +0000215025 00000 n +0000215085 00000 n +0000215145 00000 n +0000215205 00000 n +0000215265 00000 n +0000215325 00000 n +0000215385 00000 n +0000215445 00000 n +0000215505 00000 n +0000215565 00000 n +0000215625 00000 n +0000215685 00000 n +0000215745 00000 n +0000215805 00000 n +0000215865 00000 n +0000215925 00000 n +0000215985 00000 n +0000216045 00000 n +0000216105 00000 n +0000216165 00000 n +0000216225 00000 n +0000216285 00000 n +0000216345 00000 n +0000216405 00000 n +0000216465 00000 n +0000216525 00000 n +0000216585 00000 n +0000216645 00000 n +0000216705 00000 n +0000216765 00000 n +0000216825 00000 n +0000216885 00000 n +0000216945 00000 n +0000217005 00000 n +0000217065 00000 n +0000217125 00000 n +0000217185 00000 n +0000217245 00000 n +0000217305 00000 n +0000217365 00000 n +0000217425 00000 n +0000217485 00000 n +0000217545 00000 n +0000217605 00000 n +0000217665 00000 n +0000217725 00000 n +0000217785 00000 n +0000217845 00000 n +0000217905 00000 n +0000217965 00000 n +0000218025 00000 n +0000218085 00000 n +0000218145 00000 n +0000218205 00000 n +0000218265 00000 n +0000218325 00000 n +0000218385 00000 n +0000218445 00000 n +0000218505 00000 n +0000218565 00000 n +0000218625 00000 n +0000218685 00000 n +0000218745 00000 n +0000218805 00000 n +0000218865 00000 n +0000218925 00000 n +0000218985 00000 n +0000219045 00000 n +0000219105 00000 n +0000219165 00000 n +0000219225 00000 n +0000219285 00000 n +0000219345 00000 n +0000219405 00000 n +0000219465 00000 n +0000219525 00000 n +0000219585 00000 n +0000219645 00000 n +0000219705 00000 n +0000219765 00000 n +0000219825 00000 n +0000219885 00000 n +0000219945 00000 n +0000220005 00000 n +0000220065 00000 n +0000220125 00000 n +0000220185 00000 n +0000220245 00000 n +0000220305 00000 n +0000220365 00000 n +0000220425 00000 n +0000220485 00000 n +0000220545 00000 n +0000220605 00000 n +0000220665 00000 n +0000220725 00000 n +0000220785 00000 n +0000220845 00000 n +0000220905 00000 n +0000220965 00000 n +0000221025 00000 n +0000221085 00000 n +0000221145 00000 n +0000221205 00000 n +0000221265 00000 n +0000221325 00000 n +0000221385 00000 n +0000221445 00000 n +0000221505 00000 n +0000221565 00000 n +0000221625 00000 n +0000221685 00000 n +0000221745 00000 n +0000221805 00000 n +0000221865 00000 n +0000221925 00000 n +0000221985 00000 n +0000222045 00000 n +0000222105 00000 n +0000222165 00000 n +0000222225 00000 n +0000222285 00000 n +0000222345 00000 n +0000222405 00000 n +0000222465 00000 n +0000222525 00000 n +0000222585 00000 n +0000222645 00000 n +0000222705 00000 n +0000222765 00000 n +0000222825 00000 n +0000222885 00000 n +0000222945 00000 n +0000223005 00000 n +0000223064 00000 n +0000223126 00000 n +0000223186 00000 n +0000223246 00000 n +0000223306 00000 n +0000223366 00000 n +0000223426 00000 n +0000223486 00000 n +0000223546 00000 n +0000223606 00000 n +0000223666 00000 n +0000223726 00000 n +0000223786 00000 n +0000223846 00000 n +0000223905 00000 n +0000223964 00000 n +0000224023 00000 n +0000224082 00000 n +0000224141 00000 n +0000224200 00000 n +0000224259 00000 n +0000224318 00000 n +0000224378 00000 n +0000224438 00000 n +0000224498 00000 n +0000224558 00000 n +0000224618 00000 n +0000224678 00000 n +0000224738 00000 n +0000224798 00000 n +0000224858 00000 n +0000224918 00000 n +0000224978 00000 n +0000225038 00000 n +0000225098 00000 n +0000225158 00000 n +0000225218 00000 n +0000225278 00000 n +0000225338 00000 n +0000225398 00000 n +0000225458 00000 n +0000225518 00000 n +0000225578 00000 n +0000225638 00000 n +0000225698 00000 n +0000225758 00000 n +0000225818 00000 n +0000225878 00000 n +0000225938 00000 n +0000225998 00000 n +0000226058 00000 n +0000226118 00000 n +0000226178 00000 n +0000226238 00000 n +0000226298 00000 n +0000226358 00000 n +0000226418 00000 n +0000226477 00000 n +0000227626 00000 n +0000228933 00000 n +0000230240 00000 n +0000231608 00000 n +0000232998 00000 n +0000234368 00000 n +0000235739 00000 n +0000237110 00000 n +0000238495 00000 n +0000239866 00000 n +0000241237 00000 n +0000242608 00000 n +0000243974 00000 n +0000245341 00000 n +0000246689 00000 n +0000247949 00000 n +0000249205 00000 n +0000250444 00000 n +0000251703 00000 n +0000252942 00000 n +0000254181 00000 n +0000255487 00000 n +0000257082 00000 n +0000257318 00000 n +0000257574 00000 n +0000257681 00000 n +0000257969 00000 n +0000258104 00000 n +0000258211 00000 n +0000258359 00000 n +0000258502 00000 n +0000258645 00000 n +trailer +<< +/Size 1729 +/ID[] +>> +startxref +173 +%%EOF Index: qaz_libs/trunk/camera_link/docs/ds90cr286.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: qaz_libs/trunk/camera_link/docs/ds90cr286.pdf =================================================================== --- qaz_libs/trunk/camera_link/docs/ds90cr286.pdf (nonexistent) +++ qaz_libs/trunk/camera_link/docs/ds90cr286.pdf (revision 49)
qaz_libs/trunk/camera_link/docs/ds90cr286.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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