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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/sim/tests
    from Rev 40 to Rev 50
    Reverse comparison

Rev 40 → Rev 50

/tb_riffa_register_file/files.f
0,0 → 1,14
#
 
# ${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
# ${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/tb_riffa_register_file/init_test.do
7,7 → 7,6
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
19,18 → 18,8
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
vlog -f ./tb_files.f
vlog -f ./files.f
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tb_riffa_register_file/sim.do
3,9 → 3,8
 
quit -sim
 
vsim -novopt work.tb_top
# vsim -suppress 12110 -novopt work.tb_top
vsim -f ./sim.f work.tb_top
 
# log all signals
log -r *
 
 
log /* -r
/tb_riffa_register_file/sim.f
0,0 → 1,10
#
#
 
# +UVM_VERBOSITY=UVM_DEBUG
+UVM_VERBOSITY=UVM_HIGH
 
-voptargs=+acc=npr+/tb_top
-voptargs=+acc=npr+/tb_top/dut
 
 
/tb_riffa_register_file/tb_files.f
0,0 → 1,9
#
 
# +incdir+../../src/RIFFA
 
../../src/RIFFA/riffa_pkg.sv
 
./tb_top_pkg.sv
 
./tb_top.sv
/tb_riffa_register_file/tb_top.sv
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module tb_top;
import uvm_pkg::*;
import tb_top_pkg::*;
import riffa_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire clk_1000mhz;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire clk = clk_100mhz;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
// --------------------------------------------------------------------
riffa_chnl_if #(N) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
// --------------------------------------------------------------------
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
// --------------------------------------------------------------------
riffa_config #(N) cfg_h = new(chnl_bus);
 
initial
begin
uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
run_test("t_debug");
end
 
// --------------------------------------------------------------------
endmodule
/tb_riffa_register_file/tb_top_pkg.sv
0,0 → 1,47
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package tb_top_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import riffa_pkg::*;
 
// --------------------------------------------------------------------
localparam N = 16; // width of the bus in bytes
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
// --------------------------------------------------------------------
`include "../../src/tb_riffa_debug/vs_top_base.svh"
`include "vs_debug.svh"
`include "../../src/tb_riffa_debug/tb_env.svh"
`include "../../src/tb_riffa_debug/t_top_base.svh"
`include "../../src/tb_riffa_debug/t_debug.svh"
 
 
// --------------------------------------------------------------------
endpackage
/tb_riffa_register_file/vs_debug.svh
0,0 → 1,22
// --------------------------------------------------------------------
class vs_debug extends vs_top_base;
`uvm_object_utils(vs_debug)
 
// --------------------------------------------------------------------
function new(string name = "vs_debug");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
task body();
int size = B * (N / 4);
tx_api_h.init(tx_h, this, N);
rx_api_h.init(rx_h, this, N);
 
tx_api_h.counting(N , size, 0);
// rx_api_h.display(N , size, 0);
rx_api_h.get(N , size, 0);
endtask: body
 
// --------------------------------------------------------------------
endclass
/tb_riffa_register_file/wip.do
1,13 → 1,5
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
vlog -f ./tb_files.f
vlog -f ./files.f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 

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