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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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    /qaz_libs/trunk/PCIe/sim
    from Rev 31 to Rev 32
    Reverse comparison

Rev 31 → Rev 32

/src/pcie_bfm_pkg.sv
0,0 → 1,331
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package pcie_bfm_pkg;
 
// --------------------------------------------------------------------
//
import pcie_common_pkg::*;
 
 
// --------------------------------------------------------------------
//
class altera_pcie_transaction;
tlp_header_class hd_h;
byte packet[];
 
 
//--------------------------------------------------------------------
//
function new(tlp_header_class hd_h, bit qword_aligned);
this.hd_h = hd_h;
if(qword_aligned & hd_h.fmt_type[5] == 0)
if(hd_h.length == 0)
this.packet = new[1024 + 1];
else
this.packet = new[hd_h.length + 1];
else
if(hd_h.length == 0)
this.packet = new[1024];
else
this.packet = new[hd_h.length];
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: altera_pcie_transaction
// // --------------------------------------------------------------------
// //
// class base_tlp_packet_class;
 
// tlp_type_t header_type = Reserved;
// tlp_routing_t routing_type = ROUTING_UNKNOWN;
// tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
// logic [7:0] fmt_type;
// logic [2:0] tc;
// logic th;
// logic [2:0] attr;
// logic td;
// logic ep;
// logic [9:0] length;
// logic [7:0] header [16];
// logic header_is_4_dw;
 
 
// // --------------------------------------------------------------------
// //
// function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
 
// casez(fmt_type)
// 8'b000_00000: get_tlp_type = MRd;
// 8'b001_00000: get_tlp_type = MRd;
// 8'b000_00001: get_tlp_type = MRdLk;
// 8'b001_00001: get_tlp_type = MRdLk;
// 8'b010_00000: get_tlp_type = MWr;
// 8'b011_00000: get_tlp_type = MWr;
// 8'b000_00010: get_tlp_type = IORd;
// 8'b010_00010: get_tlp_type = IOWr;
// 8'b000_00100: get_tlp_type = CfgRd0;
// 8'b010_00100: get_tlp_type = CfgWr0;
// 8'b000_00101: get_tlp_type = CfgRd1;
// 8'b010_00101: get_tlp_type = CfgWr1;
// 8'b000_11011: get_tlp_type = TCfgRd;
// 8'b010_11011: get_tlp_type = TCfgWr;
// 8'b001_10???: get_tlp_type = Msg;
// 8'b011_10???: get_tlp_type = MsgD;
// 8'b000_01010: get_tlp_type = Cpl;
// 8'b010_01010: get_tlp_type = CplD;
// 8'b000_01011: get_tlp_type = CplLk;
// 8'b010_01011: get_tlp_type = CplDLk;
// 8'b010_01100: get_tlp_type = FetchAdd;
// 8'b011_01100: get_tlp_type = FetchAdd;
// 8'b010_01101: get_tlp_type = Swap;
// 8'b011_01101: get_tlp_type = Swap;
// 8'b010_01110: get_tlp_type = CAS;
// 8'b011_01110: get_tlp_type = CAS;
// 8'b100_0????: get_tlp_type = LPrfx;
// 8'b100_1????: get_tlp_type = EPrfx;
// default: get_tlp_type = Reserved;
// endcase
 
// endfunction: get_tlp_type
 
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
// MWr: get_tlp_routing = ADDRESS;
// IORd: get_tlp_routing = ADDRESS;
// IOWr: get_tlp_routing = ADDRESS;
// CfgRd0: get_tlp_routing = ID;
// CfgWr0: get_tlp_routing = ID;
// CfgRd1: get_tlp_routing = ID;
// CfgWr1: get_tlp_routing = ID;
// TCfgRd: get_tlp_routing = ID;
// TCfgWr: get_tlp_routing = ID;
// Msg: get_tlp_routing = ROUTING_UNKNOWN;
// MsgD: get_tlp_routing = ROUTING_UNKNOWN;
// Cpl: get_tlp_routing = ID;
// CplD: get_tlp_routing = ID;
// CplLk: get_tlp_routing = ID;
// CplDLk: get_tlp_routing = ID;
// FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
// Swap: get_tlp_routing = ROUTING_UNKNOWN;
// CAS: get_tlp_routing = ROUTING_UNKNOWN;
// LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// default: get_tlp_routing = ROUTING_UNKNOWN;
// endcase
 
// endfunction: get_tlp_routing
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
// MWr: get_tlp_transaction = REQUESTER;
// IORd: get_tlp_transaction = REQUESTER;
// IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: get_tlp_transaction = REQUESTER;
// CfgWr0: get_tlp_transaction = REQUESTER;
// CfgRd1: get_tlp_transaction = REQUESTER;
// CfgWr1: get_tlp_transaction = REQUESTER;
// TCfgRd: get_tlp_transaction = REQUESTER;
// TCfgWr: get_tlp_transaction = REQUESTER;
// Msg: get_tlp_transaction = REQUESTER;
// MsgD: get_tlp_transaction = REQUESTER;
// Cpl: get_tlp_transaction = COMPLETER;
// CplD: get_tlp_transaction = COMPLETER;
// CplLk: get_tlp_transaction = COMPLETER;
// CplDLk: get_tlp_transaction = COMPLETER;
// FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: get_tlp_transaction = TRANSACTION_UNKNOWN;
// endcase
 
// endfunction: get_tlp_transaction
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_type_t tlp_type);
// logic [5:0] Register_Number = header[11][7:2];
// logic [3:0] Extended_Register_Number = header[10][3:0];
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
// endfunction: display_tlp_cfg
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
// // MWr: get_tlp_transaction = REQUESTER;
// // IORd: get_tlp_transaction = REQUESTER;
// // IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: display_tlp_cfg(tlp_type);
// CfgWr0: display_tlp_cfg(tlp_type);
// CfgRd1: display_tlp_cfg(tlp_type);
// CfgWr1: display_tlp_cfg(tlp_type);
// TCfgRd: display_tlp_cfg(tlp_type);
// TCfgWr: display_tlp_cfg(tlp_type);
// // Msg: get_tlp_transaction = REQUESTER;
// // MsgD: get_tlp_transaction = REQUESTER;
// // Cpl: get_tlp_transaction = COMPLETER;
// // CplD: get_tlp_transaction = COMPLETER;
// // CplLk: get_tlp_transaction = COMPLETER;
// // CplDLk: get_tlp_transaction = COMPLETER;
// // FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: return;
// endcase
 
// endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
// $stop;
// end
 
// header_is_4_dw = data[5];
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
// attr = {header[1][2], header[2][5:4]};
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
// endfunction: set_little_endian_header
 
 
// // --------------------------------------------------------------------
// //
// function void display_header(string str);
 
// $display("??? %16.t | .....................", $time);
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
// $display("??? %16.t | tag = %b", $time, header[10]);
// end
// else
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
// display_tlp_type(header_type);
// $display("??? %16.t | ---------------------", $time);
 
// endfunction: display_header
 
 
// // //--------------------------------------------------------------------
// // //
// // function new;
 
// // endfunction: new
 
 
// // --------------------------------------------------------------------
// //
// endclass: base_tlp_packet_class
 
 
// --------------------------------------------------------------------
//
endpackage: pcie_bfm_pkg
 
 
/src/pcie_common_pkg.sv
0,0 → 1,303
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// --------------------------------------------------------------------
//
package pcie_common_pkg;
 
typedef enum
{
MRd, // Memory Read Request
MRdLk, // Memory Read Request-Locked
MWr, // Memory Write Request
IORd, // I/O Read Request
IOWr, // I/O Write Request
CfgRd0, // Configuration Read Type
CfgWr0, // Configuration Write Type
CfgRd1, // Configuration Read Type
CfgWr1, // Configuration Write Type
TCfgRd, // Deprecated TLP Type3
TCfgWr, // Deprecated TLP Type3
Msg, // Message Request
MsgD, // Message Request with data payload
Cpl, // Completion without Data
CplD, // Completion with Data
CplLk, // Completion for Locked Memory Read without Data
CplDLk, // Completion for Locked Memory Read
FetchAdd, // Fetch and Add AtomicOp Request
Swap, // Unconditional Swap AtomicOp Request
CAS, // Compare and Swap AtomicOp Request
LPrfx, // Local TLP Prefix
EPrfx, // End-End TLP Prefix
Reserved
} tlp_type_t;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
IMPLICIT
} tlp_routing_t;
 
typedef enum
{
TRANSACTION_UNKNOWN,
REQUESTER,
COMPLETER
} tlp_transaction_t;
 
 
// --------------------------------------------------------------------
//
class tlp_header_class;
 
tlp_type_t header_type;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
logic [2:0] attr;
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header[16];
logic header_is_4_dw;
 
 
// --------------------------------------------------------------------
//
// function logic [7:0] get_fmt_type(tlp_type_t header_type);
function logic [7:0] get_fmt_type;
casez(header_type)
MRd: get_fmt_type = 8'b000_00000;
MRd: get_fmt_type = 8'b001_00000;
MRdLk: get_fmt_type = 8'b000_00001;
MRdLk: get_fmt_type = 8'b001_00001;
MWr: get_fmt_type = 8'b010_00000;
MWr: get_fmt_type = 8'b011_00000;
IORd: get_fmt_type = 8'b000_00010;
IOWr: get_fmt_type = 8'b010_00010;
CfgRd0: get_fmt_type = 8'b000_00100;
CfgWr0: get_fmt_type = 8'b010_00100;
CfgRd1: get_fmt_type = 8'b000_00101;
CfgWr1: get_fmt_type = 8'b010_00101;
TCfgRd: get_fmt_type = 8'b000_11011;
TCfgWr: get_fmt_type = 8'b010_11011;
Msg: get_fmt_type = 8'b001_10xxx;
MsgD: get_fmt_type = 8'b011_10xxx;
Cpl: get_fmt_type = 8'b000_01010;
CplD: get_fmt_type = 8'b010_01010;
CplLk: get_fmt_type = 8'b000_01011;
CplDLk: get_fmt_type = 8'b010_01011;
FetchAdd: get_fmt_type = 8'b010_01100;
FetchAdd: get_fmt_type = 8'b011_01100;
Swap: get_fmt_type = 8'b010_01101;
Swap: get_fmt_type = 8'b011_01101;
CAS: get_fmt_type = 8'b010_01110;
CAS: get_fmt_type = 8'b011_01110;
LPrfx: get_fmt_type = 8'b100_0xxxx;
EPrfx: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
endcase
endfunction: get_fmt_type
 
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
8'b000_00001: get_tlp_type = MRdLk;
8'b001_00001: get_tlp_type = MRdLk;
8'b010_00000: get_tlp_type = MWr;
8'b011_00000: get_tlp_type = MWr;
8'b000_00010: get_tlp_type = IORd;
8'b010_00010: get_tlp_type = IOWr;
8'b000_00100: get_tlp_type = CfgRd0;
8'b010_00100: get_tlp_type = CfgWr0;
8'b000_00101: get_tlp_type = CfgRd1;
8'b010_00101: get_tlp_type = CfgWr1;
8'b000_11011: get_tlp_type = TCfgRd;
8'b010_11011: get_tlp_type = TCfgWr;
8'b001_10???: get_tlp_type = Msg;
8'b011_10???: get_tlp_type = MsgD;
8'b000_01010: get_tlp_type = Cpl;
8'b010_01010: get_tlp_type = CplD;
8'b000_01011: get_tlp_type = CplLk;
8'b010_01011: get_tlp_type = CplDLk;
8'b010_01100: get_tlp_type = FetchAdd;
8'b011_01100: get_tlp_type = FetchAdd;
8'b010_01101: get_tlp_type = Swap;
8'b011_01101: get_tlp_type = Swap;
8'b010_01110: get_tlp_type = CAS;
8'b011_01110: get_tlp_type = CAS;
8'b100_0????: get_tlp_type = LPrfx;
8'b100_1????: get_tlp_type = EPrfx;
default: get_tlp_type = Reserved;
endcase
endfunction: get_tlp_type
 
 
// --------------------------------------------------------------------
//
// function tlp_routing_t get_tlp_routing(tlp_type_t header_type);
function tlp_routing_t get_tlp_routing;
 
case(header_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
IORd: get_tlp_routing = ADDRESS;
IOWr: get_tlp_routing = ADDRESS;
CfgRd0: get_tlp_routing = ID;
CfgWr0: get_tlp_routing = ID;
CfgRd1: get_tlp_routing = ID;
CfgWr1: get_tlp_routing = ID;
TCfgRd: get_tlp_routing = ID;
TCfgWr: get_tlp_routing = ID;
Msg: get_tlp_routing = ROUTING_UNKNOWN;
MsgD: get_tlp_routing = ROUTING_UNKNOWN;
Cpl: get_tlp_routing = ID;
CplD: get_tlp_routing = ID;
CplLk: get_tlp_routing = ID;
CplDLk: get_tlp_routing = ID;
FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
Swap: get_tlp_routing = ROUTING_UNKNOWN;
CAS: get_tlp_routing = ROUTING_UNKNOWN;
LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
default: get_tlp_routing = ROUTING_UNKNOWN;
endcase
 
endfunction: get_tlp_routing
 
 
// --------------------------------------------------------------------
//
// function tlp_transaction_t get_tlp_transaction(tlp_type_t header_type);
function tlp_transaction_t get_tlp_transaction;
 
case(header_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
IORd: get_tlp_transaction = REQUESTER;
IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: get_tlp_transaction = REQUESTER;
CfgWr0: get_tlp_transaction = REQUESTER;
CfgRd1: get_tlp_transaction = REQUESTER;
CfgWr1: get_tlp_transaction = REQUESTER;
TCfgRd: get_tlp_transaction = REQUESTER;
TCfgWr: get_tlp_transaction = REQUESTER;
Msg: get_tlp_transaction = REQUESTER;
MsgD: get_tlp_transaction = REQUESTER;
Cpl: get_tlp_transaction = COMPLETER;
CplD: get_tlp_transaction = COMPLETER;
CplLk: get_tlp_transaction = COMPLETER;
CplDLk: get_tlp_transaction = COMPLETER;
FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: get_tlp_transaction = TRANSACTION_UNKNOWN;
endcase
 
endfunction: get_tlp_transaction
 
 
// --------------------------------------------------------------------
//
function void display_header(string str);
tlp_routing_t routing_type = get_tlp_routing;
tlp_transaction_t transaction_type = get_tlp_transaction;
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
$time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
else
$display("??? %16.t | address[31:0] = 0x%8.x", $time,
{ header[8], header[9], header[10], header[11][7:2], 2'b00});
else if(routing_type == ID)
$display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
header[8], header[9][7:3], header[9][2:0]);
 
if(transaction_type == COMPLETER)
begin
$display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
$display("??? %16.t | tag = %b", $time, header[10]);
end
else
begin
$display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | tag = %b", $time, header[6]);
$display("??? %16.t | last DW BE = %b | first DW BE = %b",
$time, header[7][7:4], header[7][3:0]);
end
 
// display_tlp_type(header_type);
 
$display("??? %16.t | ---------------------", $time);
 
endfunction: display_header
 
 
//--------------------------------------------------------------------
//
function new(tlp_type_t header_type, logic [9:0] length);
this.header_type = header_type;
this.fmt_type = get_fmt_type;
this.length = length;
this.header_is_4_dw = fmt_type[5];
this.header[0] = fmt_type;
this.header[3] = length[7:0];
this.header[2][1:0] = length[9:8];
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tlp_header_class
 
 
// --------------------------------------------------------------------
//
endpackage: pcie_common_pkg
 
 
/src/pcie_monitor_pkg.sv
30,203 → 30,117
//
package pcie_monitor_pkg;
 
typedef enum
{
MRd, // Memory Read Request
MRdLk, // Memory Read Request-Locked
MWr, // Memory Write Request
IORd, // I/O Read Request
IOWr, // I/O Write Request
CfgRd0, // Configuration Read Type
CfgWr0, // Configuration Write Type
CfgRd1, // Configuration Read Type
CfgWr1, // Configuration Write Type
TCfgRd, // Deprecated TLP Type3
TCfgWr, // Deprecated TLP Type3
Msg, // Message Request
MsgD, // Message Request with data payload
Cpl, // Completion without Data
CplD, // Completion with Data
CplLk, // Completion for Locked Memory Read without Data
CplDLk, // Completion for Locked Memory Read
FetchAdd, // Fetch and Add AtomicOp Request
Swap, // Unconditional Swap AtomicOp Request
CAS, // Compare and Swap AtomicOp Request
LPrfx, // Local TLP Prefix
EPrfx, // End-End TLP Prefix
Reserved
} tlp_type_t;
// --------------------------------------------------------------------
//
import pcie_common_pkg::*;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
IMPLICIT
} tlp_routing_t;
 
typedef enum
{
TRANSACTION_UNKNOWN,
REQUESTER,
COMPLETER
} tlp_transaction_t;
 
 
// --------------------------------------------------------------------
//
class base_tlp_packet_class;
class tlp_monitor_class;
 
tlp_type_t header_type = Reserved;
tlp_routing_t routing_type = ROUTING_UNKNOWN;
tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
logic [2:0] attr;
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header [16];
logic header_is_4_dw;
// tlp_type_t header_type = Reserved;
// tlp_routing_t routing_type = ROUTING_UNKNOWN;
// tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
// logic [7:0] fmt_type;
// logic [2:0] tc;
// logic th;
// logic [2:0] attr;
// logic td;
// logic ep;
// logic [9:0] length;
// logic [7:0] header [16];
// logic header_is_4_dw;
 
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
// // --------------------------------------------------------------------
// //
// function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
 
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
8'b000_00001: get_tlp_type = MRdLk;
8'b001_00001: get_tlp_type = MRdLk;
8'b010_00000: get_tlp_type = MWr;
8'b011_00000: get_tlp_type = MWr;
8'b000_00010: get_tlp_type = IORd;
8'b010_00010: get_tlp_type = IOWr;
8'b000_00100: get_tlp_type = CfgRd0;
8'b010_00100: get_tlp_type = CfgWr0;
8'b000_00101: get_tlp_type = CfgRd1;
8'b010_00101: get_tlp_type = CfgWr1;
8'b000_11011: get_tlp_type = TCfgRd;
8'b010_11011: get_tlp_type = TCfgWr;
8'b001_10???: get_tlp_type = Msg;
8'b011_10???: get_tlp_type = MsgD;
8'b000_01010: get_tlp_type = Cpl;
8'b010_01010: get_tlp_type = CplD;
8'b000_01011: get_tlp_type = CplLk;
8'b010_01011: get_tlp_type = CplDLk;
8'b010_01100: get_tlp_type = FetchAdd;
8'b011_01100: get_tlp_type = FetchAdd;
8'b010_01101: get_tlp_type = Swap;
8'b011_01101: get_tlp_type = Swap;
8'b010_01110: get_tlp_type = CAS;
8'b011_01110: get_tlp_type = CAS;
8'b100_0????: get_tlp_type = LPrfx;
8'b100_1????: get_tlp_type = EPrfx;
default: get_tlp_type = Reserved;
endcase
// casez(fmt_type)
// 8'b000_00000: get_tlp_type = MRd;
// 8'b001_00000: get_tlp_type = MRd;
// 8'b000_00001: get_tlp_type = MRdLk;
// 8'b001_00001: get_tlp_type = MRdLk;
// 8'b010_00000: get_tlp_type = MWr;
// 8'b011_00000: get_tlp_type = MWr;
// 8'b000_00010: get_tlp_type = IORd;
// 8'b010_00010: get_tlp_type = IOWr;
// 8'b000_00100: get_tlp_type = CfgRd0;
// 8'b010_00100: get_tlp_type = CfgWr0;
// 8'b000_00101: get_tlp_type = CfgRd1;
// 8'b010_00101: get_tlp_type = CfgWr1;
// 8'b000_11011: get_tlp_type = TCfgRd;
// 8'b010_11011: get_tlp_type = TCfgWr;
// 8'b001_10???: get_tlp_type = Msg;
// 8'b011_10???: get_tlp_type = MsgD;
// 8'b000_01010: get_tlp_type = Cpl;
// 8'b010_01010: get_tlp_type = CplD;
// 8'b000_01011: get_tlp_type = CplLk;
// 8'b010_01011: get_tlp_type = CplDLk;
// 8'b010_01100: get_tlp_type = FetchAdd;
// 8'b011_01100: get_tlp_type = FetchAdd;
// 8'b010_01101: get_tlp_type = Swap;
// 8'b011_01101: get_tlp_type = Swap;
// 8'b010_01110: get_tlp_type = CAS;
// 8'b011_01110: get_tlp_type = CAS;
// 8'b100_0????: get_tlp_type = LPrfx;
// 8'b100_1????: get_tlp_type = EPrfx;
// default: get_tlp_type = Reserved;
// endcase
 
endfunction: get_tlp_type
// endfunction: get_tlp_type
 
// --------------------------------------------------------------------
//
function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
case(tlp_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
IORd: get_tlp_routing = ADDRESS;
IOWr: get_tlp_routing = ADDRESS;
CfgRd0: get_tlp_routing = ID;
CfgWr0: get_tlp_routing = ID;
CfgRd1: get_tlp_routing = ID;
CfgWr1: get_tlp_routing = ID;
TCfgRd: get_tlp_routing = ID;
TCfgWr: get_tlp_routing = ID;
Msg: get_tlp_routing = ROUTING_UNKNOWN;
MsgD: get_tlp_routing = ROUTING_UNKNOWN;
Cpl: get_tlp_routing = ID;
CplD: get_tlp_routing = ID;
CplLk: get_tlp_routing = ID;
CplDLk: get_tlp_routing = ID;
FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
Swap: get_tlp_routing = ROUTING_UNKNOWN;
CAS: get_tlp_routing = ROUTING_UNKNOWN;
LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
default: get_tlp_routing = ROUTING_UNKNOWN;
endcase
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
// MWr: get_tlp_routing = ADDRESS;
// IORd: get_tlp_routing = ADDRESS;
// IOWr: get_tlp_routing = ADDRESS;
// CfgRd0: get_tlp_routing = ID;
// CfgWr0: get_tlp_routing = ID;
// CfgRd1: get_tlp_routing = ID;
// CfgWr1: get_tlp_routing = ID;
// TCfgRd: get_tlp_routing = ID;
// TCfgWr: get_tlp_routing = ID;
// Msg: get_tlp_routing = ROUTING_UNKNOWN;
// MsgD: get_tlp_routing = ROUTING_UNKNOWN;
// Cpl: get_tlp_routing = ID;
// CplD: get_tlp_routing = ID;
// CplLk: get_tlp_routing = ID;
// CplDLk: get_tlp_routing = ID;
// FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
// Swap: get_tlp_routing = ROUTING_UNKNOWN;
// CAS: get_tlp_routing = ROUTING_UNKNOWN;
// LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// default: get_tlp_routing = ROUTING_UNKNOWN;
// endcase
 
endfunction: get_tlp_routing
// endfunction: get_tlp_routing
// --------------------------------------------------------------------
//
function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
case(tlp_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
IORd: get_tlp_transaction = REQUESTER;
IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: get_tlp_transaction = REQUESTER;
CfgWr0: get_tlp_transaction = REQUESTER;
CfgRd1: get_tlp_transaction = REQUESTER;
CfgWr1: get_tlp_transaction = REQUESTER;
TCfgRd: get_tlp_transaction = REQUESTER;
TCfgWr: get_tlp_transaction = REQUESTER;
Msg: get_tlp_transaction = REQUESTER;
MsgD: get_tlp_transaction = REQUESTER;
Cpl: get_tlp_transaction = COMPLETER;
CplD: get_tlp_transaction = COMPLETER;
CplLk: get_tlp_transaction = COMPLETER;
CplDLk: get_tlp_transaction = COMPLETER;
FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: get_tlp_transaction = TRANSACTION_UNKNOWN;
endcase
 
endfunction: get_tlp_transaction
// --------------------------------------------------------------------
//
function void display_tlp_cfg(tlp_type_t tlp_type);
logic [5:0] Register_Number = header[11][7:2];
logic [3:0] Extended_Register_Number = header[10][3:0];
// $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
$display("??? %16.t | config offset = 0x%5.x",
$time, {Extended_Register_Number, Register_Number, 2'b00});
endfunction: display_tlp_cfg
// --------------------------------------------------------------------
//
function void display_tlp_type(tlp_type_t tlp_type);
case(tlp_type)
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
// MWr: get_tlp_transaction = REQUESTER;
// IORd: get_tlp_transaction = REQUESTER;
// IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: display_tlp_cfg(tlp_type);
CfgWr0: display_tlp_cfg(tlp_type);
CfgRd1: display_tlp_cfg(tlp_type);
CfgWr1: display_tlp_cfg(tlp_type);
TCfgRd: display_tlp_cfg(tlp_type);
TCfgWr: display_tlp_cfg(tlp_type);
// CfgRd0: get_tlp_transaction = REQUESTER;
// CfgWr0: get_tlp_transaction = REQUESTER;
// CfgRd1: get_tlp_transaction = REQUESTER;
// CfgWr1: get_tlp_transaction = REQUESTER;
// TCfgRd: get_tlp_transaction = REQUESTER;
// TCfgWr: get_tlp_transaction = REQUESTER;
// Msg: get_tlp_transaction = REQUESTER;
// MsgD: get_tlp_transaction = REQUESTER;
// Cpl: get_tlp_transaction = COMPLETER;
238,86 → 152,134
// CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: return;
endcase
// default: get_tlp_transaction = TRANSACTION_UNKNOWN;
// endcase
 
endfunction: display_tlp_type
// endfunction: get_tlp_transaction
// --------------------------------------------------------------------
//
function void set_little_endian_header( logic [127:0] data);
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_header_class hd_h);
// logic [5:0] Register_Number = hd_h.header[11][7:2];
// logic [3:0] Extended_Register_Number = hd_h.header[10][3:0];
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
// endfunction: display_tlp_cfg
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
// // MWr: get_tlp_transaction = REQUESTER;
// // IORd: get_tlp_transaction = REQUESTER;
// // IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: display_tlp_cfg(tlp_type);
// CfgWr0: display_tlp_cfg(tlp_type);
// CfgRd1: display_tlp_cfg(tlp_type);
// CfgWr1: display_tlp_cfg(tlp_type);
// TCfgRd: display_tlp_cfg(tlp_type);
// TCfgWr: display_tlp_cfg(tlp_type);
// // Msg: get_tlp_transaction = REQUESTER;
// // MsgD: get_tlp_transaction = REQUESTER;
// // Cpl: get_tlp_transaction = COMPLETER;
// // CplD: get_tlp_transaction = COMPLETER;
// // CplLk: get_tlp_transaction = COMPLETER;
// // CplDLk: get_tlp_transaction = COMPLETER;
// // FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: return;
// endcase
 
logic [2:0] fmt = data[7:5];
// endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
if(fmt > 3'b011)
begin
$display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
$stop;
end
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
// $stop;
// end
 
header_is_4_dw = data[5];
// header_is_4_dw = data[5];
for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
{header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
header_type = get_tlp_type(header[0]);
routing_type = get_tlp_routing(header_type);
transaction_type = get_tlp_transaction(header_type);
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
fmt_type = header[0];
tc = header[1][6:4];
th = header[1][0];
attr = {header[1][2], header[2][5:4]};
td = header[2][7];
ep = header[2][6];
length = {header[2][1:0], header[3]};
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
// attr = {header[1][2], header[2][5:4]};
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
endfunction: set_little_endian_header
// endfunction: set_little_endian_header
 
 
// --------------------------------------------------------------------
//
function void display_header(string str);
// // --------------------------------------------------------------------
// //
// function void display_header(string str);
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
$time, tc, th, attr, td, ep);
// $display("??? %16.t | .....................", $time);
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
else
$display("??? %16.t | address[31:0] = 0x%8.x", $time,
{ header[8], header[9], header[10], header[11][7:2], 2'b00});
else if(routing_type == ID)
$display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
header[8], header[9][7:3], header[9][2:0]);
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
if(transaction_type == COMPLETER)
begin
$display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
$display("??? %16.t | tag = %b", $time, header[10]);
end
else
begin
$display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | tag = %b", $time, header[6]);
$display("??? %16.t | last DW BE = %b | first DW BE = %b",
$time, header[7][7:4], header[7][3:0]);
end
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
// $display("??? %16.t | tag = %b", $time, header[10]);
// end
// else
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
display_tlp_type(header_type);
// display_tlp_type(header_type);
$display("??? %16.t | ---------------------", $time);
// $display("??? %16.t | ---------------------", $time);
 
endfunction: display_header
// endfunction: display_header
 
 
// //--------------------------------------------------------------------
329,7 → 291,7
 
// --------------------------------------------------------------------
//
endclass: base_tlp_packet_class
endclass: tlp_monitor_class
 
 
// --------------------------------------------------------------------
/src/riffa_agent_class_pkg.sv
0,0 → 1,107
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package riffa_agent_class_pkg;
 
// --------------------------------------------------------------------
//
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
class riffa_agent_class #(N);
 
riffa_transaction_class #(N) tr_h;
rp_tx_bfm_class #(N) tx_h;
rp_rx_bfm_class #(N) rx_h;
mailbox #(riffa_transaction_class #(N)) q;
 
 
// --------------------------------------------------------------------
//
task queue_tx(riffa_transaction_class #(N) tr_h);
tx_h.put(tr_h);
q.put(tr_h);
endtask: queue_tx
 
 
// --------------------------------------------------------------------
//
task queue_tx_random(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.random(len, off, last);
tx_h.put(tr_h);
q.put(tr_h);
endtask: queue_tx_random
 
 
// --------------------------------------------------------------------
//
task queue_rx(int len, int off, bit last);
tr_h = new(len, off, last);
rx_h.put(tr_h);
endtask: queue_rx
 
 
// --------------------------------------------------------------------
//
task wait_for_tx;
@(tx_h.tx_done);
endtask: wait_for_tx
 
 
// --------------------------------------------------------------------
//
task wait_for_rx;
@(rx_h.rx_done);
endtask: wait_for_rx
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
tx_h = new(chnl_bus);
rx_h = new(chnl_bus);
this.q = new;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: riffa_agent_class
 
 
// --------------------------------------------------------------------
//
endpackage: riffa_agent_class_pkg
 
 
 
 
 
/src/riffa_bfm_class_pkg.sv
0,0 → 1,239
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package riffa_bfm_class_pkg;
 
// --------------------------------------------------------------------
//
import q_pkg::*;
 
 
// --------------------------------------------------------------------
//
class riffa_transaction_class #(N);
 
rand logic [31:0] len;
rand logic [30:0] off;
rand logic last;
rand logic [(8*N)-1:0] data[];
 
 
//--------------------------------------------------------------------
//
function int get_data_size(int len);
// int words = $ceil(len/(N/4)); // need to fix
int words = len/(N/4);
// $display("^^^ %16.t | words = %d", $time, words);
return(words);
endfunction: get_data_size
 
 
//--------------------------------------------------------------------
//
function void random(int len, int off, bit last);
this.data = new[get_data_size(len)];
assert(this.randomize() with
{
this.len == len; // why not working?
this.off == off;
this.last == last;
});
this.len = len;
this.off = off;
this.last = last;
endfunction: random
 
 
// // --------------------------------------------------------------------
// //
// function void copy(ref riffa_transaction_class #(N) from);
// this.len = from.len;
// this.off = from.off;
// this.last = from.last;
// endfunction: copy
 
 
// // --------------------------------------------------------------------
// //
// function riffa_transaction_class #(N) clone();
// clone = new(0, 0, 0);
// clone.copy(this);
// endfunction: clone
 
 
//--------------------------------------------------------------------
function new(int len, int off, bit last);
this.data = new[get_data_size(len)];
this.len = len;
this.off = off;
this.last = last;
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: riffa_transaction_class
 
 
// --------------------------------------------------------------------
// root port tx
class rp_tx_bfm_class #(N)
extends blocking_transmission_q_class #(riffa_transaction_class #(N));
 
virtual riffa_chnl_if #(.N(N)) chnl_bus;
 
// --------------------------------------------------------------------
//
task set_default;
 
chnl_bus.cb_rp_tx.rx <= 0;
chnl_bus.cb_rp_tx.rx_last <= 'bx;
chnl_bus.cb_rp_tx.rx_len <= 'bx;
chnl_bus.cb_rp_tx.rx_off <= 'bx;
chnl_bus.cb_rp_tx.rx_data <= 'bx;
chnl_bus.cb_rp_tx.rx_data_valid <= 0;
 
endtask: set_default
 
 
// --------------------------------------------------------------------
//
event tx_done;
 
task transmit(ref Q_T tr_h);
 
@(chnl_bus.cb_rp_tx);
chnl_bus.cb_rp_tx.rx_len <= tr_h.len; // must be => 4
chnl_bus.cb_rp_tx.rx_off <= tr_h.off;
chnl_bus.cb_rp_tx.rx_last <= tr_h.last;
chnl_bus.cb_rp_tx.rx <= 1;
 
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_tx.rx_ack);
chnl_bus.cb_rp_tx.rx_data_valid <= 1;
 
foreach(tr_h.data[i])
begin
chnl_bus.cb_rp_tx.rx_data <= tr_h.data[i];
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_tx.rx_data_ren);
end
 
set_default();
->tx_done;
endtask: transmit
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
this.chnl_bus = chnl_bus;
fork
set_default();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: rp_tx_bfm_class
 
 
// --------------------------------------------------------------------
// root port rx
class rp_rx_bfm_class #(N)
extends blocking_transmission_q_class #(riffa_transaction_class #(N));
 
virtual riffa_chnl_if #(.N(N)) chnl_bus;
mailbox #(riffa_transaction_class #(N)) rx_q;
 
 
// --------------------------------------------------------------------
//
task set_default;
 
chnl_bus.cb_rp_rx.tx_ack <= 0;
chnl_bus.cb_rp_rx.tx_data_ren <= 0;
 
endtask: set_default
 
 
// --------------------------------------------------------------------
//
event rx_done;
 
task automatic transmit(ref Q_T tr_h);
int last;
int len;
int off;
 
@(chnl_bus.cb_rp_rx iff chnl_bus.cb_rp_rx.tx);
 
last = chnl_bus.cb_rp_rx.tx_last;
len = chnl_bus.cb_rp_rx.tx_len; // must be => 4
off = chnl_bus.cb_rp_rx.tx_off;
tr_h = new(len, off, last);
 
chnl_bus.cb_rp_rx.tx_ack <= 1;
chnl_bus.cb_rp_rx.tx_data_ren <= 1;
fork
@(chnl_bus.cb_rp_tx)
chnl_bus.cb_rp_rx.tx_ack <= 0;
join_none
foreach(tr_h.data[i])
@(chnl_bus.cb_rp_tx)
if(~chnl_bus.cb_rp_rx.tx)
break;
else if(chnl_bus.cb_rp_rx.tx_data_valid)
tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
 
rx_q.put(tr_h);
set_default();
->rx_done;
endtask: transmit
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
this.chnl_bus = chnl_bus;
this.rx_q = new();
fork
set_default();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: rp_rx_bfm_class
 
// --------------------------------------------------------------------
//
endpackage: riffa_bfm_class_pkg
 
/tests/tb_chnl_convolution/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_chnl_convolution
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tests/tb_chnl_convolution/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/tests/tb_chnl_convolution/src/RIFFA_example_readme.txt
0,0 → 1,6
 
Download example from link below.
 
https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/v6_pcie_convolution.zip?attredirects=0&d=1
 
files are from ./v6_pcie_convolution/hdl/verilog
/tests/tb_chnl_convolution/tb_chnl_convolution.f
0,0 → 1,18
#
 
+incdir+./src
 
./src/accumulate_bytes.v
./src/chnl_convolution.v
./src/distribute_bytes.v
./src/ram_1clk_1w_1r.v
./src/sliding_window.v
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl/chnl_tester.v
 
 
/tests/tb_chnl_convolution/tb_chnl_convolution.sv
0,0 → 1,166
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_chnl_convolution_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus();
 
 
// --------------------------------------------------------------------
//
wire CLK = tb_clk;
wire RST = tb_rst_s;
assign chnl_bus.rx_clk = CLK;
assign chnl_bus.tx_clk = CLK;
 
chnl_convolution #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
dut
(
.CHNL_RX_CLK(chnl_bus.rx_clk),
.CHNL_RX(chnl_bus.rx),
.CHNL_RX_ACK(chnl_bus.rx_ack),
.CHNL_RX_LAST(chnl_bus.rx_last),
.CHNL_RX_LEN(chnl_bus.rx_len),
.CHNL_RX_OFF(chnl_bus.rx_off),
.CHNL_RX_DATA(chnl_bus.rx_data),
.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
.CHNL_TX_CLK(chnl_bus.tx_clk),
.CHNL_TX(chnl_bus.tx),
.CHNL_TX_ACK(chnl_bus.tx_ack),
.CHNL_TX_LAST(chnl_bus.tx_last),
.CHNL_TX_LEN(chnl_bus.tx_len),
.CHNL_TX_OFF(chnl_bus.tx_off),
.CHNL_TX_DATA(chnl_bus.tx_data),
.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren),
.*
);
 
 
// --------------------------------------------------------------------
//
tb_chnl_convolution_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/tests/tb_chnl_convolution/tb_chnl_convolution_pkg.sv
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_chnl_convolution_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam C_PCI_DATA_WIDTH = 64;
localparam N = C_PCI_DATA_WIDTH / 8;
 
// --------------------------------------------------------------------
//
class tb_chnl_convolution_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_chnl_convolution_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_chnl_convolution_pkg
 
 
 
 
 
/tests/tb_chnl_convolution/the_test.sv
0,0 → 1,105
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_chnl_convolution_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
// --------------------------------------------------------------------
//
task automatic send_frame;
riffa_transaction_class #(N) tr_h;
int width = 32;
int height = 16;
int len = (width * height) / 4;
tr_h = new(len, 0, 1);
tr_h.random(len, 0, 1);
tr_h.data[0] = 0;
tr_h.data[0][10:0] = width; // rFrameWidth
tr_h.data[0][42:32] = height; // rFrameHeight
$display("^^^ %16.t | %m | %d", $time, tr_h.data.size());
tb_top.a_h.queue_tx(tr_h);
endtask
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(500us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
send_frame();
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#1us;
send_frame();
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#1us;
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/tests/tb_chnl_convolution/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/tests/tb_chnl_tester/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_chnl_tester
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tests/tb_chnl_tester/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/tests/tb_chnl_tester/tb_chnl_tester.f
0,0 → 1,13
#
 
+incdir+${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${ROOT_DIR}/riffa_2.2.2/source/fpga/riffa_hdl/chnl_tester.v
 
 
 
/tests/tb_chnl_tester/tb_chnl_tester.sv
0,0 → 1,139
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_chnl_tester_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus();
 
 
// --------------------------------------------------------------------
//
wire CLK = tb_clk;
wire RST = tb_rst_s;
assign chnl_bus.rx_clk = CLK;
assign chnl_bus.tx_clk = CLK;
 
chnl_tester #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
dut
(
.CHNL_RX_CLK(chnl_bus.rx_clk),
.CHNL_RX(chnl_bus.rx),
.CHNL_RX_ACK(chnl_bus.rx_ack),
.CHNL_RX_LAST(chnl_bus.rx_last),
.CHNL_RX_LEN(chnl_bus.rx_len),
.CHNL_RX_OFF(chnl_bus.rx_off),
.CHNL_RX_DATA(chnl_bus.rx_data),
.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
.CHNL_TX_CLK(chnl_bus.tx_clk),
.CHNL_TX(chnl_bus.tx),
.CHNL_TX_ACK(chnl_bus.tx_ack),
.CHNL_TX_LAST(chnl_bus.tx_last),
.CHNL_TX_LEN(chnl_bus.tx_len),
.CHNL_TX_OFF(chnl_bus.tx_off),
.CHNL_TX_DATA(chnl_bus.tx_data),
.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren),
.*
);
 
 
// --------------------------------------------------------------------
//
tb_chnl_tester_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/tests/tb_chnl_tester/tb_chnl_tester_pkg.sv
0,0 → 1,83
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_chnl_tester_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
// localparam C_NUM_CHNL = 1;
// localparam C_NUM_LANES = 8;
localparam C_PCI_DATA_WIDTH = 128;
// localparam C_MAX_PAYLOAD_BYTES = 256;
// localparam C_LOG_NUM_TAGS = 5;
// localparam SIG_CFG_STS_W = 53;
// localparam SIG_CFG_CTL_W = 32;
// localparam SIG_CFG_ADD_W = 4;
// localparam SIG_KO_CPLD_W = 12;
// localparam SIG_KO_CPLH_W = 8;
// localparam SIG_CHNL_OFFSET_W = 31;
// localparam SIG_CHNL_LENGTH_W = 32;
 
localparam N = C_PCI_DATA_WIDTH / 8;
 
// --------------------------------------------------------------------
//
class tb_chnl_tester_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new
(
virtual riffa_chnl_if #(.N(N)) chnl_bus
);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_chnl_tester_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_chnl_tester_pkg
 
 
 
 
 
/tests/tb_chnl_tester/the_test.sv
0,0 → 1,76
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(50us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(24, 0, 1);
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(24, 0, 1);
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/tests/tb_chnl_tester/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/tests/tb_riffa_register_file/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tests/tb_riffa_register_file/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/tests/tb_riffa_register_file/tb_riffa_register_file.f
0,0 → 1,14
#
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/tests/tb_riffa_register_file/tb_riffa_register_file.sv
0,0 → 1,146
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_register_if #(.N(N), .MW(MW)) r_if(.*);
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.A(A), .N(N), .MW(MW))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < MI; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
// --------------------------------------------------------------------
//
tb_riffa_register_file_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
 
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_in.rx_data_valid & chnl_in.rx_data_ren;
 
always_ff @(posedge chnl_in.rx_clk)
if(chnl_in.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_in.tx_data_valid & chnl_in.tx_data_ren;
 
always_ff @(posedge chnl_in.tx_clk)
if(chnl_in.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_register_file_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 16; // width of the bus in bytes
localparam MW = 3; // mux select width
localparam MI = 2 ** MW; // mux inputs
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
class tb_riffa_register_file_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_register_file_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_register_file_pkg
 
 
 
 
 
/tests/tb_riffa_register_file/the_test.sv
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(5us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*MI, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*MI, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/tests/tb_riffa_register_file/wip.do
0,0 → 1,13
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 

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