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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/sim
    from Rev 39 to Rev 40
    Reverse comparison

Rev 39 → Rev 40

/tests/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern.sv
54,7 → 54,7
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_chnl_if #(.N(N)) chnl_bus(.*);
 
 
// --------------------------------------------------------------------
76,7 → 76,7
tb_riffa_axis_test_pattern_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
a_h = new(chnl_bus);
 
 
 
/tests/tb_riffa_register_file/tb_riffa_register_file.sv
52,7 → 52,7
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_chnl_if #(.N(N)) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
79,16 → 79,16
tb_riffa_register_file_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_in.rx_data_valid & chnl_in.rx_data_ren;
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
always_ff @(posedge chnl_in.rx_clk)
if(chnl_in.rx)
always_ff @(posedge chnl_bus.rx_clk)
if(chnl_bus.rx)
begin
if(rx_en)
rx_count++;
100,10 → 100,10
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_in.tx_data_valid & chnl_in.tx_data_ren;
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
always_ff @(posedge chnl_in.tx_clk)
if(chnl_in.tx)
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.tx)
begin
if(tx_en)
tx_count++;

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