OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/sim
    from Rev 40 to Rev 50
    Reverse comparison

Rev 40 → Rev 50

/src/RIFFA/riffa_agent.svh
0,0 → 1,65
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_agent #(N) extends uvm_agent;
`uvm_component_param_utils(riffa_agent #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
riffa_rp_tx_driver #(N) rp_tx_driver_h;
riffa_rp_rx_driver #(N) rp_rx_driver_h;
riffa_rp_tx_sequencer rp_tx_sequencer_h;
riffa_rp_rx_sequencer rp_rx_sequencer_h;
// fifo_monitor monitor_h;
 
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
rp_tx_driver_h = riffa_rp_tx_driver #(N)::type_id::create("rp_tx_driver_h", this);
rp_rx_driver_h = riffa_rp_rx_driver #(N)::type_id::create("rp_rx_driver_h", this);
rp_tx_sequencer_h = riffa_rp_tx_sequencer::type_id::create("rp_tx_sequencer_h", this);
rp_rx_sequencer_h = riffa_rp_rx_sequencer::type_id::create("rp_rx_sequencer_h", this);
// monitor_h = fifo_monitor ::type_id::create("monitor_h", this);
endfunction
 
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
rp_tx_driver_h.vif = vif;
rp_rx_driver_h.vif = vif;
// monitor_h.vif = vif;
rp_tx_driver_h.seq_item_port.connect(rp_tx_sequencer_h.seq_item_export);
rp_rx_driver_h.seq_item_port.connect(rp_rx_sequencer_h.seq_item_export);
endfunction
 
// --------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/riffa_config.svh
0,0 → 1,49
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_config #(N);
 
virtual riffa_chnl_if #(N) vif;
 
// --------------------------------------------------------------------
uvm_active_passive_enum is_active;
 
function uvm_active_passive_enum get_is_active();
return is_active;
endfunction : get_is_active
 
// --------------------------------------------------------------------
function new
( virtual riffa_chnl_if #(N) vif
, uvm_active_passive_enum is_active = UVM_ACTIVE
);
this.vif = vif;
this.is_active = is_active;
endfunction : new
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/riffa_env.svh
0,0 → 1,54
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_env #(N) extends uvm_env;
`uvm_component_param_utils(riffa_env #(N));
 
// --------------------------------------------------------------------
riffa_config #(N) cfg_h;
// riffa_scoreboard scoreboard_h;
riffa_agent #(N) agent_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
agent_h = riffa_agent #(N)::type_id::create("agent_h", this);
agent_h.vif = cfg_h.vif;
// scoreboard_h = riffa_scoreboard::type_id::create("scoreboard_h", this);
endfunction : build_phase
 
// // --------------------------------------------------------------------
// function void connect_phase(uvm_phase phase);
// agent_h.monitor_h.ap.connect(scoreboard_h.analysis_export);
// endfunction : connect_phase
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/riffa_pkg.sv
0,0 → 1,50
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package riffa_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
typedef enum { RIFFA_TX_PAYLOAD // PCIe root RX from RIFFA
, RIFFA_RX_PAYLOAD // PCIe root TX to RIFFA
} riffa_transaction_t;
 
// --------------------------------------------------------------------
`include "riffa_config.svh"
`include "riffa_sequence_item.svh"
typedef uvm_sequencer #(riffa_sequence_item) riffa_rp_tx_sequencer;
typedef uvm_sequencer #(riffa_sequence_item) riffa_rp_rx_sequencer;
`include "riffa_rp_tx_driver.svh"
`include "riffa_rp_rx_driver.svh"
`include "riffa_agent.svh"
`include "riffa_env.svh"
`include "s_riffa_rp_tx_api.svh"
`include "s_riffa_rp_rx_api.svh"
 
// --------------------------------------------------------------------
endpackage
/src/RIFFA/riffa_rp_rx_driver.svh
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_rp_rx_driver #(N) extends uvm_driver #(riffa_sequence_item);
`uvm_component_param_utils(riffa_rp_rx_driver #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.cb_rp_rx.tx_ack <= 0;
vif.cb_rp_rx.tx_data_ren <= 0;
endfunction: set_default
 
//--------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
riffa_sequence_item item;
super.run_phase(phase);
 
set_default();
 
forever
begin
wait(~vif.tx_reset);
seq_item_port.get_next_item(item);
 
@(vif.cb_rp_rx iff vif.cb_rp_rx.tx);
 
item.init( N
, vif.cb_rp_rx.tx_len
, vif.cb_rp_rx.tx_off
, vif.cb_rp_rx.tx_last);
 
vif.cb_rp_rx.tx_ack <= 1;
vif.cb_rp_rx.tx_data_ren <= 1;
 
fork
@(vif.cb_rp_rx)
vif.cb_rp_rx.tx_ack <= 0;
join_none
 
for(int i = 0; i < item.beats; i++)
begin
@(vif.cb_rp_rx iff vif.cb_rp_rx.tx_data_valid)
{<<byte{item.data[i*N +: N]}} = vif.cb_rp_rx.tx_data;
 
// $display("^^^^^ %16.t | TX | %d | %h", $time, i, vif.cb_rp_rx.tx_data);
end
 
set_default();
seq_item_port.item_done();
end
endtask : run_phase
 
//--------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/riffa_rp_tx_driver.svh
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_rp_tx_driver #(N) extends uvm_driver #(riffa_sequence_item);
`uvm_component_param_utils(riffa_rp_tx_driver #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.cb_rp_tx.rx <= 0;
vif.cb_rp_tx.rx_last <= 'bx;
vif.cb_rp_tx.rx_len <= 'bx;
vif.cb_rp_tx.rx_off <= 'bx;
vif.cb_rp_tx.rx_data <= 'bx;
vif.cb_rp_tx.rx_data_valid <= 0;
endfunction: set_default
 
//--------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
riffa_sequence_item item;
reg [(8*N)-1:0] rx_data;
super.run_phase(phase);
 
set_default();
 
forever
begin
wait(~vif.rx_reset);
seq_item_port.get_next_item(item);
 
@(vif.cb_rp_tx);
vif.cb_rp_tx.rx_len <= item.len; // must be => 4
vif.cb_rp_tx.rx_off <= item.off;
vif.cb_rp_tx.rx_last <= item.last;
vif.cb_rp_tx.rx <= 1;
 
@(vif.cb_rp_tx iff vif.cb_rp_tx.rx_ack);
vif.cb_rp_tx.rx_data_valid <= 1;
 
for(int i = 0; i < item.beats; i++)
begin
{<<byte{rx_data}} = item.data[i*N +: N];
vif.cb_rp_tx.rx_data <= rx_data;
@(vif.cb_rp_tx iff vif.cb_rp_tx.rx_data_ren);
// $display("^^^^^ %16.t | RX | %d | %h", $time, i, vif.cb_rp_tx.rx_data);
end
 
set_default();
seq_item_port.item_done();
end
endtask : run_phase
 
//--------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/riffa_sequence_item.svh
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_sequence_item extends uvm_sequence_item;
`uvm_object_utils(riffa_sequence_item)
 
// --------------------------------------------------------------------
riffa_transaction_t tr;
int dwidth;
bit [31:0] len; // length in 4 byte words
bit [30:0] off;
bit last;
byte data[];
int beats;
 
// --------------------------------------------------------------------
int size;
int index = 0;
 
// --------------------------------------------------------------------
function void init(int dwidth, bit [31:0] len, bit [30:0] off, bit last);
this.dwidth = dwidth;
this.len = len;
this.size = len * 4;
this.data = new[size];
this.beats = ((size % dwidth) == 0) ? (size / dwidth) : (size / dwidth) + 1;
endfunction : init
 
// // --------------------------------------------------------------------
// function bit do_compare(uvm_object rhs, uvm_comparer comparer);
// riffa_sequence_item tested;
// bit same;
 
// if (rhs==null)
// `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer");
 
// if (!$cast(tested,rhs))
// same = 0;
// else
// same = super.do_compare(rhs, comparer);
 
// return same;
// endfunction : do_compare
 
// --------------------------------------------------------------------
function void do_copy(uvm_object rhs);
riffa_sequence_item item;
assert(rhs != null) else
`uvm_fatal(get_type_name(), "| %m | copy null transaction");
super.do_copy(rhs);
assert($cast(item,rhs)) else
`uvm_fatal(get_type_name(), "| %m | failed cast");
 
tr = item.tr ;
dwidth = item.dwidth;
len = item.len ;
off = item.off ;
last = item.last ;
data = item.data ;
beats = item.beats ;
size = item.size ;
index = item.index ;
endfunction : do_copy
 
// // --------------------------------------------------------------------
// function string convert2string();
// string s0, s1, s2, s3;
// s0 = $sformatf( "| %m | wr | rd | full | empty |\n");
// s1 = $sformatf( "| %m | %1h | %1h | %1h | %1h |\n"
// , (command == FIFO_WR) || (command == FIFO_BOTH)
// , (command == FIFO_RD) || (command == FIFO_BOTH)
// , wr_full
// , rd_empty
// );
// s2 = $sformatf("| %m | wr_data: %h\n" , wr_data);
// s3 = $sformatf("| %m | rd_data: %h\n" , rd_data);
 
// if(command == FIFO_NULL)
// return {s1, s0};
// else if(command == FIFO_BOTH)
// return {s3, s2, s1, s0};
// else if(command == FIFO_WR)
// return {s2, s1, s0};
// else if(command == FIFO_RD)
// return {s3, s1, s0};
// endfunction : convert2string
 
// --------------------------------------------------------------------
function new(string name = "");
super.new(name);
endfunction : new
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/s_riffa_rp_rx_api.svh
0,0 → 1,50
// --------------------------------------------------------------------
class s_riffa_rp_rx_api extends uvm_sequence #(riffa_sequence_item);
`uvm_object_utils(s_riffa_rp_rx_api)
 
// --------------------------------------------------------------------
riffa_sequence_item item;
int dwidth;
// mailbox #(riffa_sequence_item) q;
 
// --------------------------------------------------------------------
uvm_sequencer_base o_seqr;
uvm_sequence_base o_parent;
 
function void init(uvm_sequencer_base o_seqr, uvm_sequence_base o_parent, int dwidth);
this.o_seqr = o_seqr;
this.o_parent = o_parent;
this.dwidth = dwidth;
endfunction : init
 
// --------------------------------------------------------------------
task display(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_TX_PAYLOAD;
this.start(o_seqr, o_parent);
 
foreach(item.data[i])
$display("##### %d | 0x%h", i, item.data[i]);
endtask
 
// --------------------------------------------------------------------
task get(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_TX_PAYLOAD;
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task body();
start_item(item);
finish_item(item);
endtask
 
// --------------------------------------------------------------------
function new(string name = "s_riffa_rp_rx_api");
super.new(name);
// q = new;
endfunction
 
// --------------------------------------------------------------------
endclass
/src/RIFFA/s_riffa_rp_tx_api.svh
0,0 → 1,66
// --------------------------------------------------------------------
class s_riffa_rp_tx_api extends uvm_sequence #(riffa_sequence_item);
`uvm_object_utils(s_riffa_rp_tx_api)
 
// --------------------------------------------------------------------
riffa_sequence_item item;
int dwidth;
// mailbox #(riffa_sequence_item) q;
 
// --------------------------------------------------------------------
uvm_sequencer_base o_seqr;
uvm_sequence_base o_parent;
 
function void init(uvm_sequencer_base o_seqr, uvm_sequence_base o_parent, int dwidth);
this.o_seqr = o_seqr;
this.o_parent = o_parent;
this.dwidth = dwidth;
endfunction : init
 
// --------------------------------------------------------------------
task counting(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_RX_PAYLOAD;
item.init(dwidth, len, off, last);
 
foreach(item.data[i])
item.data[i] = i + 1;
 
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task binary_file
( string file_name
, bit [31:0] len
, bit [30:0] off
, bit last=1);
 
integer fd;
integer code;
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_RX_PAYLOAD;
item.init(dwidth, len, off, last);
 
fd = $fopen(file_name, "rb");
code = $fread(item.data, fd);
$display("##### code = %x #####", code);
$fclose(fd);
 
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task body();
start_item(item);
finish_item(item);
endtask
 
// --------------------------------------------------------------------
function new(string name = "s_riffa_rp_tx_api");
super.new(name);
// q = new;
endfunction
 
// --------------------------------------------------------------------
endclass
/src/tb_riffa_debug/t_debug.svh
0,0 → 1,59
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class t_debug extends t_top_base;
`uvm_component_utils(t_debug)
 
// --------------------------------------------------------------------
function new(string name = "t_debug", uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
function void end_of_elaboration_phase(uvm_phase phase);
uvm_phase run_phase = uvm_run_phase::get();
run_phase.phase_done.set_drain_time(this, 100ns);
endfunction
 
// --------------------------------------------------------------------
function void final_phase(uvm_phase phase);
super.final_phase(phase);
$display("^^^ %16.t | %m | Test Done!!!", $time);
$stop;
endfunction : final_phase
 
// --------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
vs_debug vseq = vs_debug::type_id::create("vseq");
phase.raise_objection(this);
vseq.init(env_h.riffa_env_h);
vseq.start(null);
phase.drop_objection(this);
endtask : run_phase
 
// --------------------------------------------------------------------
endclass
/src/tb_riffa_debug/t_top_base.svh
0,0 → 1,43
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
virtual class t_top_base extends uvm_test;
`uvm_component_utils(t_top_base);
tb_env env_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
env_h = tb_env::type_id::create("env_h",this);
endfunction : build_phase
 
// --------------------------------------------------------------------
endclass
/src/tb_riffa_debug/tb_env.svh
0,0 → 1,50
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class tb_env extends uvm_env;
`uvm_component_utils(tb_env);
 
// --------------------------------------------------------------------
riffa_env #(N) riffa_env_h;
riffa_config #(N) cfg_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
if (!uvm_config_db#(riffa_config #(N))::get(this, "", "riffa_config", cfg_h))
`uvm_fatal(get_name(), "Couldn't get config object!")
 
riffa_env_h = riffa_env #(N)::type_id::create("riffa_env_h", this);
riffa_env_h.cfg_h = cfg_h;
endfunction : build_phase
 
// --------------------------------------------------------------------
endclass
/src/tb_riffa_debug/vs_top_base.svh
0,0 → 1,26
// --------------------------------------------------------------------
class vs_top_base
extends uvm_sequence #(uvm_sequence_item);
`uvm_object_utils(vs_top_base)
 
// --------------------------------------------------------------------
riffa_rp_tx_sequencer tx_h;
riffa_rp_rx_sequencer rx_h;
s_riffa_rp_rx_api rx_api_h;
s_riffa_rp_tx_api tx_api_h;
 
// --------------------------------------------------------------------
task init(riffa_env #(N) env_h);
this.tx_h = env_h.agent_h.rp_tx_sequencer_h;
this.rx_h = env_h.agent_h.rp_rx_sequencer_h;
this.rx_api_h = s_riffa_rp_rx_api::type_id::create("rx_api_h");
this.tx_api_h = s_riffa_rp_tx_api::type_id::create("tx_api_h");
endtask: init
 
// --------------------------------------------------------------------
function new(string name = "vs_top_base");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
endclass
/tests/tb_riffa_register_file/files.f
0,0 → 1,14
#
 
# ${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
# ${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/tests/tb_riffa_register_file/init_test.do
7,7 → 7,6
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
19,18 → 18,8
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
vlog -f ./tb_files.f
vlog -f ./files.f
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tests/tb_riffa_register_file/sim.do
3,9 → 3,8
 
quit -sim
 
vsim -novopt work.tb_top
# vsim -suppress 12110 -novopt work.tb_top
vsim -f ./sim.f work.tb_top
 
# log all signals
log -r *
 
 
log /* -r
/tests/tb_riffa_register_file/sim.f
0,0 → 1,10
#
#
 
# +UVM_VERBOSITY=UVM_DEBUG
+UVM_VERBOSITY=UVM_HIGH
 
-voptargs=+acc=npr+/tb_top
-voptargs=+acc=npr+/tb_top/dut
 
 
/tests/tb_riffa_register_file/tb_files.f
0,0 → 1,9
#
 
# +incdir+../../src/RIFFA
 
../../src/RIFFA/riffa_pkg.sv
 
./tb_top_pkg.sv
 
./tb_top.sv
/tests/tb_riffa_register_file/tb_top.sv
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module tb_top;
import uvm_pkg::*;
import tb_top_pkg::*;
import riffa_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire clk_1000mhz;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire clk = clk_100mhz;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
// --------------------------------------------------------------------
riffa_chnl_if #(N) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
// --------------------------------------------------------------------
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
// --------------------------------------------------------------------
riffa_config #(N) cfg_h = new(chnl_bus);
 
initial
begin
uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
run_test("t_debug");
end
 
// --------------------------------------------------------------------
endmodule
/tests/tb_riffa_register_file/tb_top_pkg.sv
0,0 → 1,47
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package tb_top_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import riffa_pkg::*;
 
// --------------------------------------------------------------------
localparam N = 16; // width of the bus in bytes
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
// --------------------------------------------------------------------
`include "../../src/tb_riffa_debug/vs_top_base.svh"
`include "vs_debug.svh"
`include "../../src/tb_riffa_debug/tb_env.svh"
`include "../../src/tb_riffa_debug/t_top_base.svh"
`include "../../src/tb_riffa_debug/t_debug.svh"
 
 
// --------------------------------------------------------------------
endpackage
/tests/tb_riffa_register_file/vs_debug.svh
0,0 → 1,22
// --------------------------------------------------------------------
class vs_debug extends vs_top_base;
`uvm_object_utils(vs_debug)
 
// --------------------------------------------------------------------
function new(string name = "vs_debug");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
task body();
int size = B * (N / 4);
tx_api_h.init(tx_h, this, N);
rx_api_h.init(rx_h, this, N);
 
tx_api_h.counting(N , size, 0);
// rx_api_h.display(N , size, 0);
rx_api_h.get(N , size, 0);
endtask: body
 
// --------------------------------------------------------------------
endclass
/tests/tb_riffa_register_file/wip.do
1,13 → 1,5
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
vlog -f ./tb_files.f
vlog -f ./files.f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.