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    /qaz_libs/trunk/PCIe/sim
    from Rev 50 to Rev 40
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Rev 50 → Rev 40

/tests/tb_riffa_register_file/tb_files.f File deleted
/tests/tb_riffa_register_file/files.f File deleted
/tests/tb_riffa_register_file/tb_top_pkg.sv File deleted
/tests/tb_riffa_register_file/vs_debug.svh File deleted
/tests/tb_riffa_register_file/sim.f File deleted
/tests/tb_riffa_register_file/tb_top.sv File deleted
/tests/tb_riffa_register_file/tb_riffa_register_file.sv
0,0 → 1,146
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
// --------------------------------------------------------------------
//
tb_riffa_register_file_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_bus);
 
 
// --------------------------------------------------------------------
//
int rx_count = 0;
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
always_ff @(posedge chnl_bus.rx_clk)
if(chnl_bus.rx)
begin
if(rx_en)
rx_count++;
end
else
rx_count = 0;
 
 
// --------------------------------------------------------------------
//
int tx_count = 0;
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
always_ff @(posedge chnl_bus.tx_clk)
if(chnl_bus.tx)
begin
if(tx_en)
tx_count++;
end
else
tx_count = 0;
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/tests/tb_riffa_register_file/the_test.sv
0,0 → 1,92
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_register_file_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(5us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*B, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*B, 0, 1);
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.tr_h = new(RW, 0, 1);
tb_top.a_h.tr_h.constant(RW, 0, 1, 1);
tb_top.a_h.queue_tx(tb_top.a_h.tr_h);
tb_top.a_h.wait_for_tx();
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.tx_q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
0,0 → 1,70
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_register_file_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam N = 16; // width of the bus in bytes
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
 
// --------------------------------------------------------------------
//
class tb_riffa_register_file_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_register_file_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_register_file_pkg
 
 
 
 
 
/tests/tb_riffa_register_file/init_test.do
7,6 → 7,7
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
18,8 → 19,18
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
vlog -f ./tb_files.f
vlog -f ./files.f
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tests/tb_riffa_register_file/sim.do
3,8 → 3,9
 
quit -sim
 
# vsim -suppress 12110 -novopt work.tb_top
vsim -f ./sim.f work.tb_top
vsim -novopt work.tb_top
 
# log all signals
log /* -r
log -r *
 
 
/tests/tb_riffa_register_file/tb_riffa_register_file.f
0,0 → 1,14
#
 
${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/tests/tb_riffa_register_file/wip.do
1,5 → 1,13
#
 
vlog -f ./tb_files.f
vlog -f ./files.f
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/src/RIFFA/riffa_agent.svh File deleted
/src/RIFFA/riffa_config.svh File deleted
/src/RIFFA/s_riffa_rp_rx_api.svh File deleted
/src/RIFFA/riffa_rp_rx_driver.svh File deleted
/src/RIFFA/riffa_sequence_item.svh File deleted
/src/RIFFA/s_riffa_rp_tx_api.svh File deleted
/src/RIFFA/riffa_rp_tx_driver.svh File deleted
/src/RIFFA/riffa_env.svh File deleted
/src/RIFFA/riffa_pkg.sv File deleted
/src/tb_riffa_debug/t_debug.svh File deleted
/src/tb_riffa_debug/tb_env.svh File deleted
/src/tb_riffa_debug/t_top_base.svh File deleted
/src/tb_riffa_debug/vs_top_base.svh File deleted

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