URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/PCIe/src
- from Rev 50 to Rev 43
- ↔ Reverse comparison
Rev 50 → Rev 43
/RIFFA/riffa_chnl_downsizer.sv
0,0 → 1,99
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_downsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size divisor |
) |
( |
riffa_chnl_if chnl_in, |
riffa_chnl_if chnl_out |
); |
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_xx_downsizer #(.N(N), .S(S)) |
riffa_chnl_xx_downsizer_i |
( |
.xx_in(chnl_in.rx), |
.ack_in(chnl_in.rx_ack), |
.last_in(chnl_in.rx_last), |
.len_in(chnl_in.rx_len), |
.off_in(chnl_in.rx_off), |
.data_in(chnl_in.rx_data), |
.data_valid_in(chnl_in.rx_data_valid), |
.data_ren_in(chnl_in.rx_data_ren), |
|
.last_out(chnl_out.rx_last), |
.len_out(chnl_out.rx_len), |
.off_out(chnl_out.rx_off), |
.data_out(chnl_out.rx_data), |
.data_valid_out(chnl_out.rx_data_valid), |
.data_ren_out(chnl_out.rx_data_ren), |
|
.reset(chnl_in.rx_reset), |
.clk(chnl_in.rx_clk) |
); |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_xx_upsizer #(.N(N/S), .S(S)) |
riffa_chnl_xx_upsizer_i |
( |
.xx_in(chnl_in.tx), |
.ack_in(chnl_in.tx_ack), |
.last_in(chnl_out.tx_last), |
.len_in(chnl_out.tx_len), |
.off_in(chnl_out.tx_off), |
.data_in(chnl_out.tx_data), |
.data_valid_in(chnl_out.tx_data_valid), |
.data_ren_in(chnl_out.tx_data_ren), |
|
.last_out(chnl_in.tx_last), |
.len_out(chnl_in.tx_len), |
.off_out(chnl_in.tx_off), |
.data_out(chnl_in.tx_data), |
.data_valid_out(chnl_in.tx_data_valid), |
.data_ren_out(chnl_in.tx_data_ren), |
|
.reset(chnl_in.tx_reset), |
.clk(chnl_in.tx_clk) |
); |
|
|
|
// -------------------------------------------------------------------- |
// |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/RIFFA/riffa_chnl_xx_downsizer.sv
0,0 → 1,137
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_downsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size divisor |
) |
( |
input xx_in, |
output ack_in, |
input last_in, |
input [31:0] len_in, |
input [30:0] off_in, |
input [(8*N)-1:0] data_in, |
input data_valid_in, |
output data_ren_in, |
|
output last_out, |
output reg [31:0] len_out, |
output reg [30:0] off_out, |
output [(8*N/S)-1:0] data_out, |
output data_valid_out, |
input data_ren_out, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_divisor: assert(S > 1) else $fatal; |
a_data_mod: assert(N % S == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
wire [(8*N)-1:0] wr_data = data_in; |
wire wr_full; |
wire wr_en = data_ren_in & data_valid_in; |
wire rd_empty; |
wire [(8*N)-1:0] rd_data; |
wire rd_en; |
|
tiny_sync_fifo #(.W((8*N))) |
tiny_sync_fifo_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
localparam M_A = $clog2(S); |
localparam M_D = 2 ** M_A; |
localparam M_NW = (N*8)/ S; |
|
wire [M_A-1:0] select; |
|
riffa_chnl_xx_downsizer_fsm #(.N(N), .S(S), .M_A(M_A)) |
riffa_chnl_xx_downsizer_fsm_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
wire [M_NW-1:0] mux_in [M_D-1:0]; |
|
recursive_mux #(.A(M_A), .W(M_NW)) |
tdata_mux_i(.data_in(mux_in), .data_out(data_out), .*); |
|
|
// -------------------------------------------------------------------- |
// |
generate |
begin: rd_data_gen |
for(genvar j = 0; j < M_D; j++) |
assign mux_in[j] = rd_data[j*M_NW +: M_NW]; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
reg last_in_r; |
|
always_ff @(posedge clk) |
if(xx_in & ack_in) |
begin |
last_in_r <= last_in; |
len_out <= len_in; |
off_out <= off_in; |
end |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_fsm |
riffa_chnl_fsm_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
assign last_out = (select == S - 1) ? last_in_r : 0; // need to fix |
assign data_ren_in = ~wr_full; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/RIFFA/riffa_chnl_xx_downsizer_fsm.sv
0,0 → 1,118
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_downsizer_fsm |
#( |
N, // PCIe IP data in width in bytes |
S, // data out size divisor |
M_A |
) |
( |
input rd_empty, |
input data_ren_out, |
|
output rd_en, |
output data_valid_out, |
output reg [M_A-1:0] select, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// |
wire almost_last_word; |
|
|
//--------------------------------------------------- |
// state machine binary definitions |
enum reg [2:0] |
{ |
GET_WORD_IN = 3'b001, |
MUX_WORD_OUT = 3'b010, |
LAST_WORD_OUT = 3'b100 |
} state, next_state; |
|
|
//--------------------------------------------------- |
// state machine flop |
always_ff @(posedge clk) |
if(reset) |
state <= GET_WORD_IN; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always_comb |
case(state) |
GET_WORD_IN: if(~rd_empty) |
next_state <= MUX_WORD_OUT; |
else |
next_state <= GET_WORD_IN; |
|
MUX_WORD_OUT: if(rd_empty) |
next_state <= GET_WORD_IN; |
else if(almost_last_word & data_ren_out) |
next_state <= LAST_WORD_OUT; |
else |
next_state <= MUX_WORD_OUT; |
|
LAST_WORD_OUT: if(~data_ren_out) |
next_state <= LAST_WORD_OUT; |
else |
next_state <= MUX_WORD_OUT; |
|
default: next_state <= GET_WORD_IN; |
|
endcase |
|
|
// -------------------------------------------------------------------- |
// |
assign almost_last_word = (select == S - 2); |
|
always_ff @(posedge clk) |
if(reset | (state == GET_WORD_IN)) |
select <= 0; |
else if(data_valid_out & data_ren_out) |
select <= select + 1; |
|
|
// -------------------------------------------------------------------- |
// |
wire changing_state = (state != next_state); |
assign rd_en = (state == LAST_WORD_OUT) & changing_state; |
assign data_valid_out = (state != GET_WORD_IN) & ~rd_empty; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/RIFFA/riffa_chnl_xx_upsizer.sv
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_upsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size multiplier |
) |
( |
input xx_in, |
output ack_in, |
input last_in, |
input [31:0] len_in, |
input [30:0] off_in, |
input [(8*N)-1:0] data_in, |
input data_valid_in, |
output data_ren_in, |
|
output last_out, |
output [31:0] len_out, |
output [30:0] off_out, |
output [(8*N*S)-1:0] data_out, |
output data_valid_out, |
input data_ren_out, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_multiplier: assert((S > 1) & (S % 2 == 0))else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
|
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|