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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe
    from Rev 32 to Rev 33
    Reverse comparison

Rev 32 → Rev 33

/sim/src/pcie_bfm_pkg.sv
36,27 → 36,148
 
 
// --------------------------------------------------------------------
//
//
class altera_pcie_transaction;
 
tlp_header_class hd_h;
byte packet[];
byte data[];
bit tlp_always_packed;
 
 
//--------------------------------------------------------------------
//
function new(tlp_header_class hd_h, bit qword_aligned);
function bit is_qword_aligned;
is_qword_aligned = ~hd_h.address[2];
endfunction: is_qword_aligned
 
 
//--------------------------------------------------------------------
//
function bit is_tlp_packed;
if(tlp_always_packed)
return(1);
if(hd_h.is_3_dw)
if(is_qword_aligned)
return(0);
else
return(1);
else // is_4_dw
if(is_qword_aligned)
return(1);
else
return(0);
endfunction: is_tlp_packed
 
 
//--------------------------------------------------------------------
//
function void init(tlp_header_class hd_h);
this.hd_h = hd_h;
if(qword_aligned & hd_h.fmt_type[5] == 0)
if(hd_h.length == 0)
this.packet = new[1024 + 1];
else
this.packet = new[hd_h.length + 1];
endfunction: init
 
 
// --------------------------------------------------------------------
// Memory Read Request
function void make_MRd
(
logic [63:0] address,
logic [9:0] length,
bit use_64_addr = 0
);
hd_h = new(use_64_addr ? DW_4_NO_DATA : DW_3_NO_DATA, MRd, length);
hd_h.set_address(address);
init(hd_h);
data.delete();
endfunction: make_MRd
 
 
// --------------------------------------------------------------------
// Memory Write Request
function void make_MWr
(
logic [63:0] address,
byte data[],
bit use_64_addr = 0
);
logic [9:0] length = (data.size() > 1023) ? 0 : data.size();
hd_h = new(use_64_addr ? DW_4_DATA : DW_3_DATA, MWr, length);
init(hd_h);
this.data = data;
hd_h.set_address(address);
endfunction: make_MWr
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t make_packet;
byte h0[4] = {<<byte{hd_h.header[0:3]}}; // reverse bytes
byte h1[4] = {<<byte{hd_h.header[4:7]}};
byte h2[4] = {<<byte{hd_h.header[8:11]}};
byte h3[4] = {<<byte{hd_h.header[12:15]}};
byte pad[4] = '{8'hxx, 8'hxx, 8'hxx, 8'hxx};
byte header[];
if(hd_h.is_4_dw)
begin
h3 = {<<byte{hd_h.header[12:15]}};
header = {h0, h1, h2, h3};
end
else
if(hd_h.length == 0)
this.packet = new[1024];
else
this.packet = new[hd_h.length];
header = {h0, h1, h2};
if(data.size() == 0)
make_packet = header;
else if(is_tlp_packed)
make_packet = {header, data};
else
make_packet = {header, pad, data};
// else if(hd_h.is_3_dw)
// if(is_qword_aligned)
// make_packet = {header, pad, data};
// else
// make_packet = {header, data};
// else // is_4_dw
// if(is_qword_aligned)
// make_packet = {header, data};
// else
// make_packet = {header, pad, data};
endfunction: make_packet
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t get_MRd
(
logic [63:0] address,
logic [9:0] length,
bit use_64_addr = 0
);
make_MRd(address, length, use_64_addr);
return(make_packet());
endfunction: get_MRd
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t get_counting_MWr
(
logic [63:0] address,
int size,
bit use_64_addr = 0
);
byte data[];
data = new[size];
foreach(data[i])
data[i] = i;
make_MWr(address, data, use_64_addr);
return(make_packet());
endfunction: get_counting_MWr
 
 
//--------------------------------------------------------------------
//
function new(bit tlp_always_packed = 0);
this.tlp_always_packed = tlp_always_packed;
endfunction: new
 
 
63,8 → 184,8
// --------------------------------------------------------------------
//
endclass: altera_pcie_transaction
 
 
// // --------------------------------------------------------------------
// //
// class base_tlp_packet_class;
120,12 → 241,12
// endcase
 
// endfunction: get_tlp_type
 
 
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
 
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
153,12 → 274,12
// endcase
 
// endfunction: get_tlp_routing
 
 
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
 
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
186,27 → 307,27
// endcase
 
// endfunction: get_tlp_transaction
 
 
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_type_t tlp_type);
 
// logic [5:0] Register_Number = header[11][7:2];
// logic [3:0] Extended_Register_Number = header[10][3:0];
 
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
 
// endfunction: display_tlp_cfg
 
 
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
 
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
234,14 → 355,14
// endcase
 
// endfunction: display_tlp_type
 
 
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
 
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
249,7 → 370,7
// end
 
// header_is_4_dw = data[5];
 
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
256,7 → 377,7
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
 
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
264,7 → 385,7
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
 
// endfunction: set_little_endian_header
 
 
276,21 → 397,21
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
 
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
301,12 → 422,12
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
 
// display_tlp_type(header_type);
 
// $display("??? %16.t | ---------------------", $time);
 
// endfunction: display_header
/sim/src/pcie_common_pkg.sv
59,6 → 59,16
 
typedef enum
{
DW_3_NO_DATA,
DW_4_NO_DATA,
DW_3_DATA,
DW_4_DATA,
TPL_PREFIX,
RESERVED
} tlp_fmt_t;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
72,12 → 82,15
COMPLETER
} tlp_transaction_t;
 
typedef byte tpl_packet_t[];
 
 
// --------------------------------------------------------------------
//
class tlp_header_class;
 
tlp_type_t header_type;
tlp_fmt_t tlp_fmt;
tlp_type_t tlp_type;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
85,44 → 98,134
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header[16];
logic header_is_4_dw;
logic [63:0] address;
logic [1:0] ph;
byte header[];
 
 
// --------------------------------------------------------------------
//
// function logic [7:0] get_fmt_type(tlp_type_t header_type);
function bit is_3_dw;
return(~this.fmt_type[5]);
endfunction: is_3_dw
 
 
// --------------------------------------------------------------------
//
function bit is_4_dw;
return(this.fmt_type[5]);
endfunction: is_4_dw
 
 
// --------------------------------------------------------------------
//
function void set_tc(logic [2:0] tc);
this.tc = tc;
header[1][6:4] = tc;
endfunction: set_tc
 
 
// --------------------------------------------------------------------
//
function void set_th(logic th);
this.th = th;
header[1][0] = th;
endfunction: set_th
 
 
// --------------------------------------------------------------------
//
function void set_attr(logic [2:0] attr);
this.attr = attr;
{header[1][2], header[2][5:4]} = attr;
endfunction: set_attr
 
 
// --------------------------------------------------------------------
//
function void set_td(logic td);
this.td = td;
header[2][7] = td;
endfunction: set_td
 
 
// --------------------------------------------------------------------
//
function void set_ep(logic ep);
this.ep = ep;
header[2][6] = ep;
endfunction: set_ep
 
 
// --------------------------------------------------------------------
//
function void set_address(logic [63:0] address);
this.address = address;
if(is_3_dw)
begin
header[8] = this.address[31:24];
header[9] = this.address[23:16];
header[10] = this.address[15:8];
header[11][7:2] = this.address[7:2];
end
else
begin
header[8] = this.address[63:56];
header[9] = this.address[55:48];
header[10] = this.address[47:40];
header[11] = this.address[39:32];
header[12] = this.address[31:24];
header[13] = this.address[23:16];
header[14] = this.address[15:8];
header[15][7:2] = this.address[7:2];
end
endfunction: set_address
 
 
// --------------------------------------------------------------------
//
function void set_ph(logic [1:0] ph);
this.ph = ph;
if(is_3_dw)
header[11][1:0] = ph;
else
header[15][1:0] = ph;
endfunction: set_ph
 
 
// --------------------------------------------------------------------
//
function logic [7:0] get_fmt_type;
casez(header_type)
MRd: get_fmt_type = 8'b000_00000;
MRd: get_fmt_type = 8'b001_00000;
MRdLk: get_fmt_type = 8'b000_00001;
MRdLk: get_fmt_type = 8'b001_00001;
MWr: get_fmt_type = 8'b010_00000;
MWr: get_fmt_type = 8'b011_00000;
IORd: get_fmt_type = 8'b000_00010;
IOWr: get_fmt_type = 8'b010_00010;
CfgRd0: get_fmt_type = 8'b000_00100;
CfgWr0: get_fmt_type = 8'b010_00100;
CfgRd1: get_fmt_type = 8'b000_00101;
CfgWr1: get_fmt_type = 8'b010_00101;
TCfgRd: get_fmt_type = 8'b000_11011;
TCfgWr: get_fmt_type = 8'b010_11011;
Msg: get_fmt_type = 8'b001_10xxx;
MsgD: get_fmt_type = 8'b011_10xxx;
Cpl: get_fmt_type = 8'b000_01010;
CplD: get_fmt_type = 8'b010_01010;
CplLk: get_fmt_type = 8'b000_01011;
CplDLk: get_fmt_type = 8'b010_01011;
FetchAdd: get_fmt_type = 8'b010_01100;
FetchAdd: get_fmt_type = 8'b011_01100;
Swap: get_fmt_type = 8'b010_01101;
Swap: get_fmt_type = 8'b011_01101;
CAS: get_fmt_type = 8'b010_01110;
CAS: get_fmt_type = 8'b011_01110;
LPrfx: get_fmt_type = 8'b100_0xxxx;
EPrfx: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
casez({tlp_fmt, tlp_type})
{DW_3_NO_DATA, MRd}: get_fmt_type = 8'b000_00000;
{DW_4_NO_DATA, MRd}: get_fmt_type = 8'b001_00000;
{DW_3_NO_DATA, MRdLk}: get_fmt_type = 8'b000_00001;
{DW_4_NO_DATA, MRdLk}: get_fmt_type = 8'b001_00001;
{DW_3_DATA, MWr}: get_fmt_type = 8'b010_00000;
{DW_4_DATA, MWr}: get_fmt_type = 8'b011_00000;
{DW_3_NO_DATA, IORd}: get_fmt_type = 8'b000_00010;
{DW_3_DATA, IOWr}: get_fmt_type = 8'b010_00010;
{DW_3_NO_DATA, CfgRd0}: get_fmt_type = 8'b000_00100;
{DW_3_DATA, CfgWr0}: get_fmt_type = 8'b010_00100;
{DW_3_NO_DATA, CfgRd1}: get_fmt_type = 8'b000_00101;
{DW_3_DATA, CfgWr1}: get_fmt_type = 8'b010_00101;
{DW_3_NO_DATA, TCfgRd}: get_fmt_type = 8'b000_11011;
{DW_3_DATA, TCfgWr}: get_fmt_type = 8'b010_11011;
{DW_4_NO_DATA, Msg}: get_fmt_type = 8'b001_10xxx;
{DW_4_DATA, MsgD}: get_fmt_type = 8'b011_10xxx;
{DW_3_NO_DATA, Cpl}: get_fmt_type = 8'b000_01010;
{DW_3_DATA, CplD}: get_fmt_type = 8'b010_01010;
{DW_3_NO_DATA, CplLk}: get_fmt_type = 8'b000_01011;
{DW_3_DATA, CplDLk}: get_fmt_type = 8'b010_01011;
{DW_3_DATA, FetchAdd}: get_fmt_type = 8'b010_01100;
{DW_4_DATA, FetchAdd}: get_fmt_type = 8'b011_01100;
{DW_3_DATA, Swap}: get_fmt_type = 8'b010_01101;
{DW_4_DATA, Swap}: get_fmt_type = 8'b011_01101;
{DW_3_DATA, CAS}: get_fmt_type = 8'b010_01110;
{DW_4_DATA, CAS}: get_fmt_type = 8'b011_01110;
{TPL_PREFIX, LPrfx}: get_fmt_type = 8'b100_0xxxx;
{TPL_PREFIX, EPrfx}: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
endcase
endfunction: get_fmt_type
 
129,7 → 232,7
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
function tlp_type_t get_tlp_type;
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
166,10 → 269,9
 
// --------------------------------------------------------------------
//
// function tlp_routing_t get_tlp_routing(tlp_type_t header_type);
function tlp_routing_t get_tlp_routing;
 
case(header_type)
case(tlp_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
200,10 → 302,9
 
// --------------------------------------------------------------------
//
// function tlp_transaction_t get_tlp_transaction(tlp_type_t header_type);
function tlp_transaction_t get_tlp_transaction;
 
case(header_type)
case(tlp_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
234,12 → 335,12
 
// --------------------------------------------------------------------
//
function void display_header(string str);
tlp_routing_t routing_type = get_tlp_routing;
function void display_header(string str = "");
tlp_routing_t routing_type = get_tlp_routing();
tlp_transaction_t transaction_type = get_tlp_transaction;
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
$display("??? %16.t | %s | TLP type | %s", $time, str, tlp_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
246,7 → 347,7
$time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(header_is_4_dw)
if(is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
271,7 → 372,7
$time, header[7][7:4], header[7][3:0]);
end
 
// display_tlp_type(header_type);
// display_tlp_type(tlp_type);
 
$display("??? %16.t | ---------------------", $time);
 
280,11 → 381,15
 
//--------------------------------------------------------------------
//
function new(tlp_type_t header_type, logic [9:0] length);
this.header_type = header_type;
this.fmt_type = get_fmt_type;
function new(tlp_fmt_t tlp_fmt, tlp_type_t tlp_type, logic [9:0] length);
this.tlp_fmt = tlp_fmt;
this.tlp_type = tlp_type;
this.fmt_type = get_fmt_type();
this.length = length;
this.header_is_4_dw = fmt_type[5];
if(is_3_dw)
this.header = new[12];
else
this.header = new[16];
this.header[0] = fmt_type;
this.header[3] = length[7:0];
this.header[2][1:0] = length[9:8];
/src/PCIe_debug.sv
0,0 → 1,83
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
PCIe_debug
(
PCIe_debug_if dbg_bus,
input [31:0] h0,
input [31:0] h1,
input [31:0] h2,
input [31:0] h3,
input enable,
input reset,
input clk
);
 
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
begin
dbg_bus.h0_r <= h0;
dbg_bus.h1_r <= h1;
dbg_bus.h2_r <= h2;
dbg_bus.h3_r <= h3;
dbg_bus.enable_r <= enable;
end
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(dbg_bus.enable_r)
begin
dbg_bus.tlp_fmt <= dbg_bus.h0_r[31:29];
dbg_bus.tlp_type <= dbg_bus.h0_r[28:24];
dbg_bus.tlp_tc <= dbg_bus.h0_r[22:20];
dbg_bus.tlp_th <= dbg_bus.h0_r[16];
dbg_bus.tlp_td <= dbg_bus.h0_r[15];
dbg_bus.tlp_ep <= dbg_bus.h0_r[14];
dbg_bus.tlp_attr <= {dbg_bus.h0_r[18], dbg_bus.h0_r[13:12]};
dbg_bus.tlp_at <= dbg_bus.h0_r[11:10];
dbg_bus.tlp_length <= dbg_bus.h0_r[9:0];
end
// --------------------------------------------------------------------
//
assign dbg_bus.tlp_is_3dw = ~dbg_bus.h0_r[29];
assign dbg_bus.tlp_is_4dw = dbg_bus.h0_r[29];
assign dbg_bus.tlp_address = dbg_bus.tlp_is_4dw
? {dbg_bus.h2_r, dbg_bus.h3_r}
: {32'h0, dbg_bus.h2_r};
// --------------------------------------------------------------------
//
endmodule
 
/src/PCIe_debug_if.sv
0,0 → 1,61
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
PCIe_debug_if
(
input reset,
input clk
);
 
logic [2:0] tlp_fmt;
logic [4:0] tlp_type;
logic [2:0] tlp_tc;
logic tlp_th;
logic tlp_td;
logic tlp_ep;
logic [2:0] tlp_attr;
logic tlp_at;
logic [9:0] tlp_length;
logic [1:0] tlp_ph;
logic enable_r;
logic [31:0] h0_r;
logic [31:0] h1_r;
logic [31:0] h2_r;
logic [31:0] h3_r;
logic tlp_is_3dw;
logic tlp_is_4dw;
logic [63:0] tlp_address;
 
 
// --------------------------------------------------------------------
//
endinterface
 
/src/RIFFA/riffa_register_file.sv
28,7 → 28,7
module
riffa_register_file
#(
A, // address bus width
// A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
)

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