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https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lib/sim/src
- from Rev 31 to Rev 29
- ↔ Reverse comparison
Rev 31 → Rev 29
/axi4_bfm_pkg.sv
File deleted
/tb_axi4_memory.sv
File deleted
/tb_axi4_to_axis_agent_class_pkg.sv
File deleted
/axi4_models/axi4_models_pkg.sv
File deleted
/axi4_models/axi4_arbiter_pkg.sv
File deleted
/axi4_models/axi4_memory_pkg.sv
File deleted
/axi4_models/tb_axi4_multi_port_memory.sv
File deleted
/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv
38,7 → 38,8
MAXWAITS = 16, |
RecommendOn = 1'b1, |
RecMaxWaitOn = 1'b1, |
EXMON_WIDTH = 4 |
EXMON_WIDTH = 4, |
PROTOCOL = 2'b00 |
) |
( |
axi4_if axi4_in |
164,7 → 165,11
.RecMaxWaitOn(RecMaxWaitOn), // = 1'b1; |
|
// Set the protocol - used to disable some AXI4 checks for ACE |
// .PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4; |
//PROTOCOL define the protocol |
// `define AXI4PC_AMBA_AXI4 2'b00 |
// `define AXI4PC_AMBA_ACE 2'b01 |
// `define AXI4PC_AMBA_ACE_LITE 2'b10 |
.PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4; |
|
// Set ADDR_WIDTH to the address-bus width required |
.ADDR_WIDTH(A), // = 32; // address bus width, default = 32-bit |