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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_lib
    from Rev 29 to Rev 24
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Rev 29 → Rev 24

/sim/tests/debug_register_slice/wip.do File deleted
/sim/tests/debug_register_slice/init_test.do File deleted
/sim/tests/debug_register_slice/the_test.sv File deleted
/sim/tests/debug_register_slice/sim.do File deleted
/sim/tests/debug_bfm/wip.do File deleted
/sim/tests/debug_bfm/init_test.do File deleted
/sim/tests/debug_bfm/the_test.sv File deleted
/sim/tests/debug_bfm/sim.do File deleted
/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv File deleted
/sim/src/axi4_bfm/axi4_slave_bfm_if.sv File deleted
/sim/src/axi4_bfm/axi4_master_bfm_if.sv File deleted
/sim/src/axi4_bfm/axi4_transaction_pkg.sv File deleted
/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv File deleted
/sim/src/tb_register_slice.sv File deleted
/sim/src/tb_bfm.sv File deleted
/sim/libs/axi4_lib_verilog/tiny_fifo.f File deleted
/sim/libs/axi4_lib_verilog/axi4_stream_lib.f File deleted
/sim/libs/axi4_lib_verilog/axi4_base.f File deleted
/sim/libs/packages_verilog/tb_lib.f File deleted
/sim/libs/sim_verilog/tb_lib.f File deleted
/sim/libs/sim_verilog/axi4_bfm.f File deleted
/src/axi4_to_write_fifos.sv File deleted
/src/axi4_register_slice.sv File deleted
/src/axi4_to_read_fifos.sv File deleted
/src/axi4_if.sv
29,60 → 29,146
interface
axi4_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
DATA_WIDTH = 64
)
(
input aresetn,
input aclk
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
wire arready;
wire arregion;
wire awready;
wire awregion;
wire bvalid;
wire rlast;
wire rvalid;
wire wready;
wire [1:0] bresp;
wire [1:0] rresp;
wire [5:0] bid;
wire [5:0] rid;
wire [DATA_WIDTH-1:0] rdata;
wire [7:0] rcount;
wire [7:0] wcount;
wire [2:0] racount;
wire [5:0] wacount;
wire arvalid;
wire awvalid;
wire bready;
wire rready;
wire wlast;
wire wvalid;
wire [1:0] arburst;
wire [1:0] arlock;
wire [2:0] arsize;
wire [1:0] awburst;
wire [1:0] awlock;
wire [2:0] awsize;
wire [2:0] arprot;
wire [2:0] awprot;
wire [31:0] araddr;
wire [31:0] awaddr;
wire [3:0] arcache;
wire [7:0] arlen;
wire [3:0] arqos;
wire [3:0] awcache;
wire [3:0] awlen;
wire [3:0] awqos;
wire [5:0] arid;
wire [5:0] awid;
wire [5:0] wid;
wire [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH/8-1:0] wstrb;
// --------------------------------------------------------------------
//
modport
master
(
output arid,
output araddr,
output arburst,
output arcache,
output arlen,
output arlock,
output arprot,
output arqos,
input arready,
output arregion,
output arsize,
output arvalid,
output awaddr,
output awburst,
output awcache,
output awlen,
output awlock,
output awprot,
output awqos,
input awready,
output awregion,
output awsize,
output awvalid,
output bready,
input bresp,
input bvalid,
input rdata,
input rlast,
output rready,
input rresp,
input rvalid,
output wdata,
output wlast,
input wready,
output wstrb,
output wvalid,
input aresetn,
input aclk
);
modport
slave
(
input arid,
input araddr,
input arburst,
input arcache,
input arlen,
input arlock,
input arprot,
input arqos,
output arready,
input arregion,
input arsize,
input arvalid,
input awaddr,
input awburst,
input awcache,
input awlen,
input awlock,
input awprot,
input awqos,
output awready,
input awregion,
input awsize,
input awvalid,
input bready,
output bresp,
output bvalid,
output rdata,
output rlast,
input rready,
output rresp,
output rvalid,
input wdata,
input wlast,
output wready,
input wstrb,
input wvalid,
input aresetn,
input aclk
);
endinterface: axi4_if
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 

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