URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lib
- from Rev 31 to Rev 30
- ↔ Reverse comparison
Rev 31 → Rev 30
/sim/libs/axi4_lib_verilog/axi4_stream_lib.f
0,0 → 1,9
# |
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${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_if.sv |
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_video_debug.sv |
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/data_to_axis_fsm.sv |
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${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_register_slice.sv |
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/sim/libs/axi4_lib_verilog/axi4_base.f
0,0 → 1,12
# |
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${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_if.sv |
# ${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_read_fsm.sv |
# ${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_write_fsm.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_read_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_write_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_register_slice.sv |
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/sim/libs/axi4_lib_verilog/tiny_fifo.f
0,0 → 1,9
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# ${ROOT_DIR}/qaz_libs/FIFOs/src/tiny_sync_fifo.sv |
# ${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_read_if.sv |
# ${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_write_if.sv |
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${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_witout_if/tiny_sync_fifo.sv |
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/sim/libs/packages_verilog/tb_lib.f
0,0 → 1,7
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${ROOT_DIR}/qaz_libs/tb_class/src/tb_bfm_pkg.sv |
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/sim/libs/sim_verilog/axi4_bfm.f
0,0 → 1,19
# |
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+incdir+${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva |
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${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva/Axi4PC_ace.sv |
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${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv |
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# ${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/qaz_axi4_bfm_pkg.sv |
# ${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/tb_axi4lite_bfm_if.sv |
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/sim/libs/sim_verilog/tb_lib.f
0,0 → 1,16
# |
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-mfcu |
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${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk_class.sv |
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${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk.sv |
${ROOT_DIR}/qaz_libs/tb_class/src/tb_base.sv |
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/sim/src/axi4_bfm_pkg.sv
File deleted
/sim/src/tb_axi4_memory.sv
File deleted
/sim/src/tb_axi4_to_axis_agent_class_pkg.sv
File deleted
/sim/src/axi4_models/axi4_arbiter_pkg.sv
File deleted
/sim/src/axi4_models/axi4_memory_pkg.sv
File deleted
/sim/src/axi4_models/tb_axi4_multi_port_memory.sv
File deleted
/sim/src/axi4_models/axi4_models_pkg.sv
File deleted
/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv
38,7 → 38,8
MAXWAITS = 16, |
RecommendOn = 1'b1, |
RecMaxWaitOn = 1'b1, |
EXMON_WIDTH = 4 |
EXMON_WIDTH = 4, |
PROTOCOL = 2'b00 |
) |
( |
axi4_if axi4_in |
164,7 → 165,11
.RecMaxWaitOn(RecMaxWaitOn), // = 1'b1; |
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// Set the protocol - used to disable some AXI4 checks for ACE |
// .PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4; |
//PROTOCOL define the protocol |
// `define AXI4PC_AMBA_AXI4 2'b00 |
// `define AXI4PC_AMBA_ACE 2'b01 |
// `define AXI4PC_AMBA_ACE_LITE 2'b10 |
.PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4; |
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// Set ADDR_WIDTH to the address-bus width required |
.ADDR_WIDTH(A), // = 32; // address bus width, default = 32-bit |
/sim/tests/debug_axi4_memory/sim.f
File deleted
\ No newline at end of file
/sim/tests/debug_axi4_memory/wip.do
File deleted
/sim/tests/debug_axi4_memory/init_test.do
File deleted
/sim/tests/debug_axi4_memory/the_test.sv
File deleted
/sim/tests/debug_axi4_memory/sim.do
File deleted
/sim/tests/tb_axi4_to_axis_basic_dma/wip.do
File deleted
/sim/tests/tb_axi4_to_axis_basic_dma/init_test.do
File deleted
/sim/tests/tb_axi4_to_axis_basic_dma/the_test.sv
File deleted
/sim/tests/tb_axi4_to_axis_basic_dma/sim.do
File deleted
/src/axi4_to_axis_basic_dma.sv
File deleted
/src/axi4_m_to_read_fifos.sv
File deleted
/src/axi4_s_to_read_fifos.sv
File deleted
/src/axi4_m_to_write_fifos.sv
File deleted
/src/axi4_s_to_write_fifos.sv
File deleted
/src/axi4_if.sv
38,273 → 38,51
input aclk |
); |
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wire [(A-1):0] araddr; |
wire [1:0] arburst; |
wire [3:0] arcache; |
wire [(I-1):0] arid; |
wire [7:0] arlen; |
wire arlock; |
wire [2:0] arprot; |
wire [3:0] arqos; |
wire arready; |
wire [3:0] arregion; |
wire [2:0] arsize; |
wire arvalid; |
wire [(A-1):0] awaddr; |
wire [1:0] awburst; |
wire [3:0] awcache; |
wire [(I-1):0] awid; |
wire [7:0] awlen; |
wire awlock; |
wire [2:0] awprot; |
wire [3:0] awqos; |
wire awready; |
wire [3:0] awregion; |
wire [2:0] awsize; |
wire awvalid; |
wire [(I-1):0] bid; |
wire bready; |
wire [1:0] bresp; |
wire bvalid; |
wire [(8*N)-1:0] rdata; |
wire [(I-1):0] rid; |
wire rlast; |
wire rready; |
wire [1:0] rresp; |
wire rvalid; |
wire [(8*N)-1:0] wdata; |
wire [(I-1):0] wid; |
wire wlast; |
wire wready; |
wire [N-1:0] wstrb; |
wire wvalid; |
logic [(A-1):0] araddr; |
logic [1:0] arburst; |
logic [3:0] arcache; |
logic [(I-1):0] arid; |
logic [7:0] arlen; |
logic arlock; |
logic [2:0] arprot; |
logic [3:0] arqos; |
logic arready; |
logic [3:0] arregion; |
logic [2:0] arsize; |
logic arvalid; |
logic [(A-1):0] awaddr; |
logic [1:0] awburst; |
logic [3:0] awcache; |
logic [(I-1):0] awid; |
logic [7:0] awlen; |
logic awlock; |
logic [2:0] awprot; |
logic [3:0] awqos; |
logic awready; |
logic [3:0] awregion; |
logic [2:0] awsize; |
logic awvalid; |
logic [(I-1):0] bid; |
logic bready; |
logic [1:0] bresp; |
logic bvalid; |
logic [(8*N)-1:0] rdata; |
logic [(I-1):0] rid; |
logic rlast; |
logic rready; |
logic [1:0] rresp; |
logic rvalid; |
logic [(8*N)-1:0] wdata; |
logic [(I-1):0] wid; |
logic wlast; |
logic wready; |
logic [N-1:0] wstrb; |
logic wvalid; |
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// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_s @(posedge aclk); |
input arid; |
input araddr; |
input arburst; |
input arcache; |
input awid; |
input arlen; |
input arlock; |
input arprot; |
input arqos; |
output arready; |
input arregion; |
input arsize; |
input arvalid; |
input awaddr; |
input awburst; |
input awcache; |
input awlen; |
input awlock; |
input awprot; |
input awqos; |
output awready; |
input awregion; |
input awsize; |
input awvalid; |
input bready; |
output bid; |
output bresp; |
output bvalid; |
output rdata; |
output rid; |
output rlast; |
input rready; |
output rresp; |
output rvalid; |
input wdata; |
input wid; |
input wlast; |
output wready; |
input wstrb; |
input wvalid; |
input aresetn; |
input aclk; |
endclocking |
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// -------------------------------------------------------------------- |
// |
default clocking cb_m @(posedge aclk); |
output arid; |
output araddr; |
output arburst; |
output arcache; |
output awid; |
output arlen; |
output arlock; |
output arprot; |
output arqos; |
input arready; |
output arregion; |
output arsize; |
output arvalid; |
output awaddr; |
output awburst; |
output awcache; |
output awlen; |
output awlock; |
output awprot; |
output awqos; |
input awready; |
output awregion; |
output awsize; |
output awvalid; |
output bready; |
input bid; |
input bresp; |
input bvalid; |
input rdata; |
input rid; |
input rlast; |
output rready; |
input rresp; |
input rvalid; |
output wdata; |
output wid; |
output wlast; |
input wready; |
output wstrb; |
output wvalid; |
input aresetn; |
input aclk; |
endclocking |
// synthesis translate_on |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// |
`ifdef USE_MOD_PORTS |
// -------------------------------------------------------------------- |
// |
modport |
slave |
( |
// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_s, |
// synthesis translate_on |
// -------------------------------------------------------------------- |
input arid, |
input araddr, |
input arburst, |
input arcache, |
input awid, |
input arlen, |
input arlock, |
input arprot, |
input arqos, |
output arready, |
input arregion, |
input arsize, |
input arvalid, |
input awaddr, |
input awburst, |
input awcache, |
input awlen, |
input awlock, |
input awprot, |
input awqos, |
output awready, |
input awregion, |
input awsize, |
input awvalid, |
input bready, |
output bid, |
output bresp, |
output bvalid, |
output rdata, |
output rid, |
output rlast, |
input rready, |
output rresp, |
output rvalid, |
input wdata, |
input wid, |
input wlast, |
output wready, |
input wstrb, |
input wvalid, |
input aresetn, |
input aclk |
); |
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// -------------------------------------------------------------------- |
// |
modport |
master |
( |
// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_m, |
// synthesis translate_on |
// -------------------------------------------------------------------- |
output arid, |
output araddr, |
output arburst, |
output arcache, |
output awid, |
output arlen, |
output arlock, |
output arprot, |
output arqos, |
input arready, |
output arregion, |
output arsize, |
output arvalid, |
output awaddr, |
output awburst, |
output awcache, |
output awlen, |
output awlock, |
output awprot, |
output awqos, |
input awready, |
output awregion, |
output awsize, |
output awvalid, |
output bready, |
input bid, |
input bresp, |
input bvalid, |
input rdata, |
input rid, |
input rlast, |
output rready, |
input rresp, |
input rvalid, |
output wdata, |
output wlast, |
input wready, |
output wstrb, |
output wvalid, |
input aresetn, |
input aclk |
); |
`endif |
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// -------------------------------------------------------------------- |
// synthesis translate_off |
task |
zero_cycle_delay; |
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##0; |
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endtask: zero_cycle_delay |
// synthesis translate_on |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// |
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endinterface |
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/src/axi4_register_slice.sv
53,16 → 53,14
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// -------------------------------------------------------------------- |
// |
axi4_s_to_read_fifos |
axi4_to_read_fifos |
#( |
.A(A), |
.N(N), |
.I(I), |
.R_D(2), |
.AR_D(2), |
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL) |
) |
axi4_s_to_read_fifos_i(.*); |
axi4_to_read_fifos_i(.*); |
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// -------------------------------------------------------------------- |
120,17 → 118,14
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// -------------------------------------------------------------------- |
// |
axi4_s_to_write_fifos |
axi4_to_write_fifos |
#( |
.A(A), |
.N(N), |
.I(I), |
.W_D(2), |
.B_D(2), |
.AW_D(2), |
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL) |
) |
axi4_s_to_write_fifos_i(.*); |
axi4_to_write_fifos_i(.*); |
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// -------------------------------------------------------------------- |