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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/axi4_lite_lib
    from Rev 37 to Rev 43
    Reverse comparison

Rev 37 → Rev 43

/sim/src/tb_axi4_lite_register_file.sv
74,7 → 74,8
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10))
// axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10))
axi4_checker #(.A(A), .N(N))
axi4_s_check(.axi4_in(axi4_s));
 
 
/sim/tests/debug_axi4_lite_register_file/init_test.do
4,30 → 4,30
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_recursive_axis_mux
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all packages
sim_compile_all sim
sim_compile_all axi4_lib
sim_compile_all axi4_lite_lib
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
# simulation $root
vlog $env(LIB_BASE_DIR)/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv
vlog $env(LIB_BASE_DIR)/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv
vlog $env(PROJECT_DIR)/sim/src/axi4_lite_agent_pkg.sv
vlog $env(PROJECT_DIR)/sim/src/tb_axi4_lite_register_file.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
/src/axi4_lite_register_file.sv
28,10 → 28,10
module
axi4_lite_register_file
#(
A = 32, // address bus width, must be 32 or greater for axi lite
N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
I = 1, // ID width
MW = 3 // mux select width
A, // address bus width, must be 32 or greater for axi lite
N, // data bus width in bytes, must be 4 or 8 for axi lite
I = 1, // ID width
MW // mux select width
)
(
axi4_if axi4_s,
/src/axi4_lite_register_if.sv
32,10 → 32,6
N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
MW = 3, // mux select width
MI = 2 ** MW // mux inputs
)
(
input aclk,
input aresetn
);
 
wire [(N*8)-1:0] register_in [MI-1:0];
42,13 → 38,10
reg [(N*8)-1:0] register_out [MI-1:0];
wire wr_en [MI-1:0];
 
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
 
 
// synthesis translate_on
// --------------------------------------------------------------------
 

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