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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_stream_lib/src
    from Rev 31 to Rev 30
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  •

Rev 31 → Rev 30

/axis_to_axi4_basic_dma.sv File deleted
/axis_synchronizer.sv File deleted
/axis_upsizer.sv File deleted
/axis_downsizer.sv File deleted
/axis_map_fifo.sv File deleted
/axis_alias.sv
27,6 → 27,14
 
module
axis_alias
#(
N = 8, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
axis_if axis_in,
axis_if axis_out
/axis_mux.sv
28,37 → 28,26
module
axis_mux
#(
N, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
N = 8, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
input mux_select,
axis_if axis_0_in,
axis_if axis_1_in,
axis_if axis_out,
input axis_en,
input aclk,
input aresetn
input mux_select,
axis_if.slave axis_0_in,
axis_if.slave axis_1_in,
axis_if.master axis_out,
input axis_en,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(1), .D(1), .U(U))
axis_if #(.N(N), .I(I), .D(D), .U(U))
axis_mux_out(.*);
 
assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
/axis_register_slice.sv
36,49 → 36,48
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
axis_if axis_in,
axis_if axis_out,
input aclk,
input aresetn
input axis_en,
axis_if.slave axis_in,
axis_if.master axis_out,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
fifo_write_if #(.W(W)) fifo_sink(aclk, ~aresetn);
fifo_read_if #(.W(W)) fifo_source(aclk, ~aresetn);
 
tiny_sync_fifo #(.W(W))
tiny_sync_fifo_i(.source(fifo_sink.fifo), .sink(fifo_source.fifo));
 
 
// --------------------------------------------------------------------
//
wire wr_full;
wire [W-1:0] wr_data;
wire wr_en;
wire data_to_axis_fsm_error;
 
wire rd_empty;
wire [W-1:0] rd_data;
wire rd_en;
data_to_axis_fsm
data_to_axis_fsm_i
(
.axis_tvalid(axis_out.tvalid),
.axis_tready(axis_out.tready),
.fifo_empty(fifo_source.empty),
.fifo_rd_en(fifo_source.rd_en),
.fifo_watermark(1'b1),
.*
);
 
tiny_sync_fifo #(.W(W))
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
 
// --------------------------------------------------------------------
//
generate
begin: assign_gen
 
if(USE_TSTRB & USE_TKEEP)
begin
assign wr_data =
assign fifo_sink.wr_data =
{
axis_in.tdata,
axis_in.tlast,
93,11 → 92,11
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
} = rd_data;
} = fifo_source.rd_data;
end
else if(USE_TSTRB)
begin
assign wr_data =
assign fifo_sink.wr_data =
{
axis_in.tdata,
axis_in.tlast,
110,11 → 109,11
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
} = rd_data;
} = fifo_source.rd_data;
end
else if(USE_TKEEP)
begin
assign wr_data =
assign fifo_sink.wr_data =
{
axis_in.tdata,
axis_in.tlast,
127,11 → 126,11
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
} = rd_data;
} = fifo_source.rd_data;
end
else
begin
assign wr_data =
assign fifo_sink.wr_data =
{
axis_in.tdata,
axis_in.tlast,
142,8 → 141,9
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
} = rd_data;
} = fifo_source.rd_data;
end
 
end
endgenerate
 
150,13 → 150,10
 
// --------------------------------------------------------------------
//
assign axis_in.tready = ~wr_full;
assign wr_en = axis_in.tvalid & ~wr_full;
assign axis_out.tvalid = ~rd_empty;
assign rd_en = axis_out.tready & ~rd_empty;
assign axis_in.tready = ~fifo_sink.full;
assign fifo_sink.wr_en = axis_in.tvalid & ~fifo_sink.full;
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/data_to_axis_fsm.sv
29,18 → 29,18
module
data_to_axis_fsm
(
input axis_en,
output axis_tvalid,
input axis_tready,
input axis_en,
output axis_tvalid,
input axis_tready,
 
input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also
input fifo_empty,
output fifo_rd_en,
input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also
input fifo_empty,
output fifo_rd_en,
 
output data_to_axis_fsm_error,
output data_to_axis_fsm_error,
 
input aclk,
input aresetn
input aclk,
input aresetn
);
 
//---------------------------------------------------
/axis_video_debug.sv
56,9 → 56,7
(* MARK_DEBUG = "TRUE" *) wire dbg_tvalid = axis_in.tvalid;
(* MARK_DEBUG = "TRUE" *) wire dbg_tready = axis_in.tready;
(* MARK_DEBUG = "TRUE" *) wire dbg_eol = axis_in.tlast;
(* MARK_DEBUG = "TRUE" *) wire dbg_sof = axis_in.tuser[0];
(* MARK_DEBUG = "TRUE" *) wire dbg_sol = axis_in.tuser[1];
(* MARK_DEBUG = "TRUE" *) wire dbg_eof = axis_in.tuser[2];
(* MARK_DEBUG = "TRUE" *) wire dbg_sof = axis_in.tuser;
 
 
endmodule
/axis_if.sv
29,7 → 29,7
interface
axis_if
#(
N = 0, // data bus width in bytes
N = 8, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1 // TUSER width
38,60 → 38,56
input aclk,
input aresetn
);
wire tvalid;
wire tready;
wire [(8*N)-1:0] tdata;
wire [N-1:0] tstrb;
wire [N-1:0] tkeep;
wire tlast;
wire [I-1:0] tid;
wire [D-1:0] tdest;
wire [U-1:0] tuser;
wire tvalid;
wire tready;
wire [(8*N)-1:0] tdata;
wire [N-1:0] tstrb;
wire [N-1:0] tkeep;
wire tlast;
wire [I-1:0] tid;
wire [D-1:0] tdest;
wire [U-1:0] tuser;
 
 
// --------------------------------------------------------------------
// synthesis translate_off
default clocking cb_m @(posedge aclk iff aresetn);
output tvalid;
input tready;
output tdata;
output tstrb;
output tkeep;
output tlast;
output tid;
output tdest;
output tuser;
endclocking
// --------------------------------------------------------------------
//
default clocking cb_m @(posedge aclk iff aresetn);
input aresetn;
input aclk;
output tvalid;
input tready;
output tdata;
output tstrb;
output tkeep;
output tlast;
output tid;
output tdest;
output tuser;
endclocking
 
 
// --------------------------------------------------------------------
//
clocking cb_s @(posedge aclk iff aresetn);
input tvalid;
output tready;
input tdata;
input tstrb;
input tkeep;
input tlast;
input tid;
input tdest;
input tuser;
endclocking
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
clocking cb_s @(posedge aclk iff aresetn);
input aresetn;
input aclk;
input tvalid;
output tready;
input tdata;
input tstrb;
input tkeep;
input tlast;
input tid;
input tdest;
input tuser;
endclocking
 
 
// --------------------------------------------------------------------
//
`ifdef USE_MOD_PORTS
// --------------------------------------------------------------------
//
modport
master
(
// --------------------------------------------------------------------
// synthesis translate_off
clocking cb_m,
// synthesis translate_on
// --------------------------------------------------------------------
input aresetn,
input aclk,
output tvalid,
102,7 → 98,8
output tlast,
output tid,
output tdest,
output tuser
output tuser,
clocking cb_m
);
 
 
111,11 → 108,6
modport
slave
(
// --------------------------------------------------------------------
// synthesis translate_off
clocking cb_s,
// synthesis translate_on
// --------------------------------------------------------------------
input aresetn,
input aclk,
input tvalid,
126,24 → 118,11
input tlast,
input tid,
input tdest,
input tuser
input tuser,
clocking cb_s
);
`endif
 
 
// --------------------------------------------------------------------
// synthesis translate_off
task
zero_cycle_delay;
endinterface: axis_if
 
##0;
 
endtask: zero_cycle_delay
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
endinterface: axis_if
 

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