OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/axi4_stream_lib/src
    from Rev 35 to Rev 36
    Reverse comparison

Rev 35 → Rev 36

/axis_alias.sv
27,6 → 27,10
 
module
axis_alias
#(
CONNECT_TREADY = 1,
CONNECT_TVALID = 1
)
(
axis_if axis_in,
axis_if axis_out
34,9 → 38,26
 
// --------------------------------------------------------------------
//
assign axis_in.tready = axis_out.tready;
generate
if(CONNECT_TREADY == 1)
begin: tready_gen
assign axis_in.tready = axis_out.tready;
end
endgenerate
 
assign axis_out.tvalid = axis_in.tvalid;
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TVALID == 1)
begin: tvalid_gen
assign axis_out.tvalid = axis_in.tvalid;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_out.tdata = axis_in.tdata;
assign axis_out.tstrb = axis_in.tstrb;
assign axis_out.tkeep = axis_in.tkeep;
48,7 → 69,6
 
// --------------------------------------------------------------------
//
 
endmodule
 
 
/axis_catenate.sv
0,0 → 1,112
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_catenate
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
U_IS_EOP = -1
)
(
axis_if axis_in [1:0],
axis_if axis_out,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
wire select;
wire axis_eop;
 
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules?
defparam axis_eop_mux_i.MA = 1;
axis_eop_mux
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))
axis_eop_mux_i(.axis_in(axis_in), .*);
 
 
// --------------------------------------------------------------------
// state machine binary definitions
enum reg [1:0]
{
HEAD = 2'b01,
TAIL = 2'b10
} state, next_state;
 
 
// --------------------------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= HEAD;
else
state <= next_state;
 
 
// --------------------------------------------------------------------
// state machine
always_comb
case(state)
HEAD: if(axis_eop)
next_state <= TAIL;
else
next_state <= HEAD;
 
TAIL: if(axis_eop)
next_state <= HEAD;
else
next_state <= TAIL;
 
default: next_state <= HEAD;
endcase
 
 
// --------------------------------------------------------------------
//
defparam axis_mux_i.N = N; // why are needed these for recursive modules?
defparam axis_mux_i.I = I;
defparam axis_mux_i.D = D;
defparam axis_mux_i.U = U;
axis_mux
// axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i(.axis_in(axis_in), .*);
 
 
// --------------------------------------------------------------------
//
assign select = (state == HEAD) ? 0 : 1;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axis_eop_mux.sv
0,0 → 1,74
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_eop_mux
#(
U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser
MA, // select width
MD = 2 ** MA
)
(
axis_if axis_in[MD-1:0],
input [MA-1:0] select,
output axis_eop,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
wire eop_out[MD-1:0];
genvar j;
 
generate
for(j = 0; j < MD; j++)
begin: eop_gen
axis_eop_set #(U_IS_EOP)
axis_eop_set_i
(
.axis_in(axis_in[j]),
.tready(axis_in[j].tready),
.tvalid(axis_in[j].tvalid),
.axis_eop(eop_out[j]),
.*
);
end
endgenerate
 
 
// --------------------------------------------------------------------
//
recursive_mux #(.A(MA), .W(1))
recursive_mux_i(select, eop_out, axis_eop);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axis_eop_set.sv
0,0 → 1,62
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_eop_set
#(
U_IS_EOP = -1 // set to -1 for tlast, else set to index of tuser
)
(
axis_if axis_in,
input tready,
input tvalid,
output axis_eop,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
genvar j;
 
generate
if(U_IS_EOP > -1)
begin: axis_eop_is_tuser_gen
assign axis_eop = tready & tvalid & axis_in.tuser[U_IS_EOP];
end
else
begin: axis_eop_is_tlast_gen
assign axis_eop = tready & tvalid & axis_in.tlast;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axis_map_fifo.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
28,7 → 28,7
module
axis_map_fifo
#(
N = 8, // data bus width in bytes
N, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
/axis_mux.sv
28,50 → 28,36
module
axis_mux
#(
N, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
input mux_select,
axis_if axis_0_in,
axis_if axis_1_in,
input select,
axis_if axis_in[1:0],
axis_if axis_out,
input axis_en,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(1), .D(1), .U(U))
axis_mux_out(.*);
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
 
assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0;
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready;
assign axis_in[1].tready = select ? axis_mux_out.tready : 0;
 
assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
assign axis_mux_out.tdata = mux_select ? axis_1_in.tdata : axis_0_in.tdata;
assign axis_mux_out.tstrb = mux_select ? axis_1_in.tstrb : axis_0_in.tstrb;
assign axis_mux_out.tkeep = mux_select ? axis_1_in.tkeep : axis_0_in.tkeep;
assign axis_mux_out.tlast = mux_select ? axis_1_in.tlast : axis_0_in.tlast;
assign axis_mux_out.tid = mux_select ? axis_1_in.tid : axis_0_in.tid;
assign axis_mux_out.tdest = mux_select ? axis_1_in.tdest : axis_0_in.tdest;
assign axis_mux_out.tuser = mux_select ? axis_1_in.tuser : axis_0_in.tuser;
assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid;
assign axis_mux_out.tdata = select ? axis_in[1].tdata : axis_in[0].tdata;
assign axis_mux_out.tstrb = select ? axis_in[1].tstrb : axis_in[0].tstrb;
assign axis_mux_out.tkeep = select ? axis_in[1].tkeep : axis_in[0].tkeep;
assign axis_mux_out.tlast = select ? axis_in[1].tlast : axis_in[0].tlast;
assign axis_mux_out.tid = select ? axis_in[1].tid : axis_in[0].tid;
assign axis_mux_out.tdest = select ? axis_in[1].tdest : axis_in[0].tdest;
assign axis_mux_out.tuser = select ? axis_in[1].tuser : axis_in[0].tuser;
 
 
// --------------------------------------------------------------------
82,21 → 68,19
.I(I),
.D(D),
.U(U),
.USE_TSTRB(USE_TSTRB),
.USE_TKEEP(USE_TKEEP)
.USE_TSTRB(0),
.USE_TKEEP(0)
)
axis_register_slice_i
(
.axis_in(axis_mux_out), // .slave
.axis_out(axis_out), // .master
.axis_in(axis_mux_out), // slave
.axis_out(axis_out), // master
.*
);
 
 
// --------------------------------------------------------------------
//
 
 
// --------------------------------------------------------------------
//
endmodule
 
 
/axis_register_slice.sv
28,9 → 28,9
module
axis_register_slice
#(
N = 8, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
42,17 → 42,6
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
68,7 → 57,9
wire [W-1:0] rd_data;
wire rd_en;
 
tiny_sync_fifo #(.W(W))
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
tiny_sync_fifo
// tiny_sync_fifo #(W)
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
 
/axis_switch.sv
0,0 → 1,137
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_switch
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1 // TUSER width
)
(
input select,
axis_if axis_in,
axis_if axis_out[1:0],
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_fanout[1:0](.*);
 
 
// --------------------------------------------------------------------
//
assign axis_fanout[0].tdata = axis_in.tdata;
assign axis_fanout[0].tstrb = axis_in.tstrb;
assign axis_fanout[0].tkeep = axis_in.tkeep;
assign axis_fanout[0].tlast = axis_in.tlast;
assign axis_fanout[0].tid = axis_in.tid;
assign axis_fanout[0].tdest = axis_in.tdest;
assign axis_fanout[0].tuser = axis_in.tuser;
 
 
// --------------------------------------------------------------------
//
assign axis_fanout[1].tdata = axis_in.tdata;
assign axis_fanout[1].tstrb = axis_in.tstrb;
assign axis_fanout[1].tkeep = axis_in.tkeep;
assign axis_fanout[1].tlast = axis_in.tlast;
assign axis_fanout[1].tid = axis_in.tid;
assign axis_fanout[1].tdest = axis_in.tdest;
assign axis_fanout[1].tuser = axis_in.tuser;
 
 
// --------------------------------------------------------------------
//
assign axis_in.tready = select ? axis_fanout[1].tready : axis_fanout[0].tready;
 
 
// --------------------------------------------------------------------
//
assign axis_fanout[0].tvalid = axis_in.tvalid & (select == 0);
assign axis_fanout[1].tvalid = axis_in.tvalid & (select == 1);
 
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_lo.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_lo.I = I;
defparam axis_register_slice_lo.D = D;
defparam axis_register_slice_lo.U = U;
defparam axis_register_slice_lo.USE_TSTRB = 0;
defparam axis_register_slice_lo.USE_TKEEP = 0;
axis_register_slice
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(0),
// .USE_TKEEP(0)
// )
axis_register_slice_lo
(
.axis_in(axis_fanout[0]),
.axis_out(axis_out[0]),
.*
);
 
 
// --------------------------------------------------------------------
//
// why does questasim need these for recursive modules?
defparam axis_register_slice_hi.N = N;
defparam axis_register_slice_hi.I = I;
defparam axis_register_slice_hi.D = D;
defparam axis_register_slice_hi.U = U;
defparam axis_register_slice_hi.USE_TSTRB = 0;
defparam axis_register_slice_hi.USE_TKEEP = 0;
axis_register_slice
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(0),
// .USE_TKEEP(0)
// )
axis_register_slice_hi
(
.axis_in(axis_fanout[1]),
.axis_out(axis_out[1]),
.*
);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axis_switch_allocator.sv
0,0 → 1,150
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_switch_allocator
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser
SA, // select width
SD = 2 ** SA
)
(
axis_if axis_in,
axis_if axis_out[SD-1:0],
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
wire eop_in;
 
axis_eop_set #(U_IS_EOP)
axis_eop_set_i
(
.axis_in(axis_in),
.tready(axis_switch_in.tready),
.tvalid(axis_in.tvalid),
.axis_eop(eop_in),
.*
);
 
 
// --------------------------------------------------------------------
//
wire eop_out_mux;
reg [SA-1:0] select;
 
axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(SA))
axis_eop_mux_i
(
.axis_in(axis_out),
.axis_eop(eop_out_mux),
.*
);
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_in(.*);
 
axis_alias #(.CONNECT_TREADY(0), .CONNECT_TVALID(0))
axis_alias_i(.axis_out(axis_switch_in), .*);
 
 
// --------------------------------------------------------------------
// state machine binary definitions
enum reg [3:0]
{
ALLOT = 4'b0001,
FLUSH = 4'b0010,
SWITCH = 4'b0100,
SETTLE = 4'b1000
} state, next_state;
 
 
// --------------------------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= ALLOT;
else
state <= next_state;
 
 
// --------------------------------------------------------------------
// state machine
always_comb
case(state)
ALLOT: if(eop_in)
next_state <= FLUSH;
else
next_state <= ALLOT;
 
FLUSH: if(eop_out_mux)
next_state <= SWITCH;
else
next_state <= FLUSH;
 
SWITCH: next_state <= SETTLE;
SETTLE: next_state <= ALLOT; // let select propagate to the switches
 
default: next_state <= ALLOT;
endcase
 
 
// --------------------------------------------------------------------
//
always_ff @(posedge aclk)
if(~aresetn)
select <= 0;
else if(state == SWITCH)
select <= select + 1;
 
 
// --------------------------------------------------------------------
//
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA))
recursive_axis_switch_i(.axis_in(axis_switch_in), .*);
 
 
// --------------------------------------------------------------------
//
assign axis_in.tready = (state == ALLOT) & axis_switch_in.tready;
assign axis_switch_in.tvalid = (state == ALLOT) & axis_in.tvalid;
 
 
// --------------------------------------------------------------------
//
endmodule
 
/recursive_axis_catenate.sv
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
recursive_axis_catenate
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
U_IS_EOP = -1,
MA, // mux select width
MD = 2 ** MA
)
(
axis_if axis_in [MD-1:0],
axis_if axis_out,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
generate
if(MA == 1)
begin: catenate_gen
axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
axis_catenate_i(.*);
end
else
begin: recursive_catenate_gen
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_catenate_out[1:0](.*);
 
recursive_axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP),
.MA(MA - 1)
)
catenate_lo
(
.axis_in(axis_in[(MD/2)-1:0]),
.axis_out(axis_catenate_out[0]),
.*
);
 
// --------------------------------------------------------------------
//
recursive_axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP),
.MA(MA - 1)
)
catenate_hi
(
.axis_in(axis_in[MD-1:(MD/2)]),
.axis_out(axis_catenate_out[1]),
.*
);
 
// --------------------------------------------------------------------
//
axis_catenate
#(
.N(N),
.I(I),
.D(D),
.U(U),
.U_IS_EOP(U_IS_EOP)
)
axis_catenate_i(.axis_in(axis_catenate_out), .*);
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 
/recursive_axis_mux.sv
0,0 → 1,91
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
recursive_axis_mux
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
MA, // mux select width
MD = 2 ** MA
)
(
input [MA-1:0] select,
axis_if axis_in [MD-1:0],
axis_if axis_out,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
generate
if(MA == 1)
begin: mux_gen
axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i(.*);
end
else
begin: recurse_mux_gen
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out[1:0](.*);
 
recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1))
mux_lo
(
.select(select[MA-2:0]),
.axis_in(axis_in[(MD/2)-1:0]),
.axis_out(axis_mux_out[0]),
.*
);
 
recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1))
mux_hi
(
.select(select[MA-2:0]),
.axis_in(axis_in[MD-1:(MD/2)]),
.axis_out(axis_mux_out[1]),
.*
);
 
axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i
(
.select(select[MA-1]),
.axis_in(axis_mux_out),
.*
);
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 
/recursive_axis_switch.sv
0,0 → 1,100
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
recursive_axis_switch
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
SA, // mux select width
SD = 2 ** SA
)
(
input [SA-1:0] select,
axis_if axis_in,
axis_if axis_out[SD-1:0],
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
generate
if(SA == 1)
begin: switch_gen
axis_switch #(.N(N), .I(I), .D(D), .U(U))
axis_switch_i(.*);
end
else
begin: recursive_switch_gen
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_out[1:0](.*);
 
axis_switch #(.N(N), .I(I), .D(D), .U(U))
axis_switch_i
(
.select(select[SA-1]),
.axis_out(axis_switch_out),
.*
);
 
 
// --------------------------------------------------------------------
//
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA - 1))
switch_lo
(
.select(select[SA-2:0]),
.axis_in(axis_switch_out[0]),
.axis_out(axis_out[(SD/2)-1:0]),
.*
);
 
 
// --------------------------------------------------------------------
//
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA - 1))
switch_hi
(
.select(select[SA-2:0]),
.axis_in(axis_switch_out[1]),
.axis_out(axis_out[SD-1:(SD/2)]),
.*
);
end
endgenerate
 
 
// --------------------------------------------------------------------
//
endmodule
 

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.