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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_stream_lib/src
    from Rev 36 to Rev 35
    ↔ Reverse comparison
  •

Rev 36 → Rev 35

/axis_switch.sv File deleted
/recursive_axis_catenate.sv File deleted
/recursive_axis_switch.sv File deleted
/axis_eop_set.sv File deleted
/axis_switch_allocator.sv File deleted
/axis_catenate.sv File deleted
/recursive_axis_mux.sv File deleted
/axis_eop_mux.sv File deleted
/axis_alias.sv
27,10 → 27,6
 
module
axis_alias
#(
CONNECT_TREADY = 1,
CONNECT_TVALID = 1
)
(
axis_if axis_in,
axis_if axis_out
38,26 → 34,9
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TREADY == 1)
begin: tready_gen
assign axis_in.tready = axis_out.tready;
end
endgenerate
assign axis_in.tready = axis_out.tready;
 
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TVALID == 1)
begin: tvalid_gen
assign axis_out.tvalid = axis_in.tvalid;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_out.tvalid = axis_in.tvalid;
assign axis_out.tdata = axis_in.tdata;
assign axis_out.tstrb = axis_in.tstrb;
assign axis_out.tkeep = axis_in.tkeep;
69,6 → 48,7
 
// --------------------------------------------------------------------
//
 
endmodule
 
 
/axis_map_fifo.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
28,7 → 28,7
module
axis_map_fifo
#(
N, // data bus width in bytes
N = 8, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
/axis_mux.sv
28,36 → 28,50
module
axis_mux
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
N, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
input select,
axis_if axis_in[1:0],
input mux_select,
axis_if axis_0_in,
axis_if axis_1_in,
axis_if axis_out,
input axis_en,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
axis_if #(.N(N), .I(1), .D(1), .U(U))
axis_mux_out(.*);
 
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready;
assign axis_in[1].tready = select ? axis_mux_out.tready : 0;
assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0;
 
assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid;
assign axis_mux_out.tdata = select ? axis_in[1].tdata : axis_in[0].tdata;
assign axis_mux_out.tstrb = select ? axis_in[1].tstrb : axis_in[0].tstrb;
assign axis_mux_out.tkeep = select ? axis_in[1].tkeep : axis_in[0].tkeep;
assign axis_mux_out.tlast = select ? axis_in[1].tlast : axis_in[0].tlast;
assign axis_mux_out.tid = select ? axis_in[1].tid : axis_in[0].tid;
assign axis_mux_out.tdest = select ? axis_in[1].tdest : axis_in[0].tdest;
assign axis_mux_out.tuser = select ? axis_in[1].tuser : axis_in[0].tuser;
assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
assign axis_mux_out.tdata = mux_select ? axis_1_in.tdata : axis_0_in.tdata;
assign axis_mux_out.tstrb = mux_select ? axis_1_in.tstrb : axis_0_in.tstrb;
assign axis_mux_out.tkeep = mux_select ? axis_1_in.tkeep : axis_0_in.tkeep;
assign axis_mux_out.tlast = mux_select ? axis_1_in.tlast : axis_0_in.tlast;
assign axis_mux_out.tid = mux_select ? axis_1_in.tid : axis_0_in.tid;
assign axis_mux_out.tdest = mux_select ? axis_1_in.tdest : axis_0_in.tdest;
assign axis_mux_out.tuser = mux_select ? axis_1_in.tuser : axis_0_in.tuser;
 
 
// --------------------------------------------------------------------
68,19 → 82,21
.I(I),
.D(D),
.U(U),
.USE_TSTRB(0),
.USE_TKEEP(0)
.USE_TSTRB(USE_TSTRB),
.USE_TKEEP(USE_TKEEP)
)
axis_register_slice_i
(
.axis_in(axis_mux_out), // slave
.axis_out(axis_out), // master
.axis_in(axis_mux_out), // .slave
.axis_out(axis_out), // .master
.*
);
 
 
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
//
 
 
endmodule
 
 
/axis_register_slice.sv
28,9 → 28,9
module
axis_register_slice
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
N = 8, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
42,6 → 42,17
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
57,9 → 68,7
wire [W-1:0] rd_data;
wire rd_en;
 
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
tiny_sync_fifo
// tiny_sync_fifo #(W)
tiny_sync_fifo #(.W(W))
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
 

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