OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/axi4_stream_lib
    from Rev 37 to Rev 38
    Reverse comparison

Rev 37 → Rev 38

/src/axis_alias.sv
28,8 → 28,10
module
axis_alias
#(
CONNECT_TREADY = 1,
CONNECT_TVALID = 1
CONNECT_TREADY = 1,
CONNECT_TVALID = 1,
CONNECT_TLAST = 1,
CONNECT_TUSER = 1
)
(
axis_if axis_in,
58,13 → 60,31
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TLAST == 1)
begin: tlast_gen
assign axis_out.tlast = axis_in.tlast;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TUSER == 1)
begin: tuser_gen
assign axis_out.tuser = axis_in.tuser;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_out.tdata = axis_in.tdata;
assign axis_out.tstrb = axis_in.tstrb;
assign axis_out.tkeep = axis_in.tkeep;
assign axis_out.tlast = axis_in.tlast;
assign axis_out.tid = axis_in.tid;
assign axis_out.tdest = axis_in.tdest;
assign axis_out.tuser = axis_in.tuser;
 
 
// --------------------------------------------------------------------
/src/axis_catenate.sv
47,7 → 47,7
wire select;
wire axis_eop;
 
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules?
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are these needed for recursive modules?
defparam axis_eop_mux_i.MA = 1;
axis_eop_mux
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))
141,7 → 141,7
 
// --------------------------------------------------------------------
//
defparam axis_mux_i.N = N; // why are needed these for recursive modules?
defparam axis_mux_i.N = N; // why are these needed for recursive modules?
defparam axis_mux_i.I = I;
defparam axis_mux_i.D = D;
defparam axis_mux_i.U = U;
/src/axis_interleave.sv
0,0 → 1,91
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_interleave
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1 // TUSER width
)
(
axis_if axis_in [1:0],
axis_if axis_out,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// state machine binary definitions
enum reg [1:0]
{
EVEN = 2'b01,
ODD = 2'b10
} state, next_state;
 
 
// --------------------------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= EVEN;
else
state <= next_state;
 
 
// --------------------------------------------------------------------
// state machine
always_comb
case(state)
EVEN: if(axis_in[0].tvalid)
next_state <= ODD;
else
next_state <= EVEN;
 
ODD: if(axis_in[1].tvalid)
next_state <= EVEN;
else
next_state <= ODD;
 
default: next_state <= EVEN;
endcase
 
 
// --------------------------------------------------------------------
//
wire select = (state == EVEN) ? 0 : 1;
 
axis_mux #(.N(N), .I(I), .D(D), .U(U))
axis_mux_i(.*);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/src/axis_map_fifo.sv
35,15 → 35,13
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0, // set to 1 to enable, 0 to disable
// USE_XID = 0, // set to 1 to enable, 0 to disable
W = 0
W
)
(
axis_if axis_in,
axis_if axis_out,
output [W-1:0] wr_data,
input [W-1:0] rd_data,
input aclk,
input aresetn
input [W-1:0] rd_data
);
 
// --------------------------------------------------------------------
/src/axis_mux.sv
45,7 → 45,7
 
// --------------------------------------------------------------------
//
defparam axis_mux_out.N = N; // why are needed these for recursive modules?
defparam axis_mux_out.N = N; // why are these needed for recursive modules?
defparam axis_mux_out.I = I;
defparam axis_mux_out.D = D;
defparam axis_mux_out.U = U;
67,7 → 67,7
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_i.N = N; // why are these needed for recursive modules?
defparam axis_register_slice_i.I = I;
defparam axis_register_slice_i.D = D;
defparam axis_register_slice_i.U = U;
/src/axis_register_slice.sv
57,7 → 57,7
wire [W-1:0] rd_data;
wire rd_en;
 
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
defparam tiny_sync_fifo_i.W=W; // why are these needed for recursive modules?
tiny_sync_fifo
// tiny_sync_fifo #(W)
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
65,78 → 65,24
 
// --------------------------------------------------------------------
//
generate
begin: assign_gen
if(USE_TSTRB & USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
} = rd_data;
end
else if(USE_TSTRB)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
} = rd_data;
end
else if(USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
} = rd_data;
end
else
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
} = rd_data;
end
end
endgenerate
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
defparam axis_map_fifo_i.I=I;
defparam axis_map_fifo_i.D=D;
defparam axis_map_fifo_i.U=U;
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
defparam axis_map_fifo_i.W=W;
axis_map_fifo
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(USE_TSTRB),
// .USE_TKEEP(USE_TKEEP),
// .W(W)
// )
axis_map_fifo_i(.*);
 
 
// --------------------------------------------------------------------
/src/axis_switch.sv
82,7 → 82,7
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_lo.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_lo.N = N; // why are these needed for recursive modules?
defparam axis_register_slice_lo.I = I;
defparam axis_register_slice_lo.D = D;
defparam axis_register_slice_lo.U = U;
/src/axis_synchronizer.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
28,33 → 28,23
module
axis_synchronizer
#(
N = 8, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
USE_TKEEP = 0, // set to 1 to enable, 0 to disable
FD
)
(
axis_if axis_in,
axis_if axis_out,
input wr_clk,
input wr_reset,
input aclk,
input aresetn
input aclk_in,
input aresetn_in,
input aclk_out,
input aresetn_out
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
68,94 → 58,50
 
wire rd_empty;
wire [W-1:0] rd_data;
wire rd_en;
tiny_async_fifo #(.W(W))
tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);
wire rd_en;
 
defparam async_fifo_i.W=W; // why are these needed for recursive modules?
defparam async_fifo_i.D=FD;
async_fifo
// async_fifo #(.W(W), .D(FD))
async_fifo_i
(
.wr_clk(aclk_in),
.wr_reset(~aresetn_in),
.rd_clk(aclk_out),
.rd_reset(~aresetn_out),
.*
);
 
 
// --------------------------------------------------------------------
//
generate
begin: assign_gen
if(USE_TSTRB & USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
} = rd_data;
end
else if(USE_TSTRB)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
} = rd_data;
end
else if(USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
} = rd_data;
end
else
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
} = rd_data;
end
end
endgenerate
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
defparam axis_map_fifo_i.I=I;
defparam axis_map_fifo_i.D=D;
defparam axis_map_fifo_i.U=U;
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
defparam axis_map_fifo_i.W=W;
axis_map_fifo
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(USE_TSTRB),
// .USE_TKEEP(USE_TKEEP),
// .W(W)
// )
axis_map_fifo_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axis_in.tready = ~wr_full;
assign wr_en = axis_in.tvalid & axis_in.tready;
assign wr_en = axis_in.tvalid & ~wr_full;
assign axis_out.tvalid = ~rd_empty;
assign rd_en = axis_out.tvalid & axis_out.tready;
assign rd_en = axis_out.tready & ~rd_empty;
 
 
// --------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.