URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/basal/src
- from Rev 50 to Rev 49
- ↔ Reverse comparison
Rev 50 → Rev 49
/FIFOs/sync_fifo.sv
25,6 → 25,7
//// //// |
////////////////////////////////////////////////////////////////////// |
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|
module |
sync_fifo |
#( |
36,9 → 37,11
output wr_full, |
input [W-1:0] wr_data, |
input wr_en, |
|
output rd_empty, |
output [W-1:0] rd_data, |
input rd_en, |
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output [UB:0] count, |
input clk, |
input reset |
45,21 → 48,12
); |
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// -------------------------------------------------------------------- |
// |
generate |
begin: fifo_gen |
if(D == 2) |
begin |
reg [UB:0] count_r; |
assign count = count_r; |
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always_comb |
case({wr_full, rd_empty}) |
2'b0_0: count_r = 1; |
2'b0_1: count_r = 0; |
2'b1_0: count_r = 2; |
2'b1_1: count_r = 'x; // should never happen |
endcase |
|
assign count = 0; |
tiny_sync_fifo #(.W(W)) |
tiny_sync_fifo_i(.*); |
end |
79,6 → 73,7
end |
endgenerate |
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// -------------------------------------------------------------------- |
// synthesis translate_off |
always_ff @(posedge clk) |
90,5 → 85,9
// synthesis translate_on |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// |
endmodule |
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/FIFOs/tiny_async_fifo.sv
0,0 → 1,189
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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module |
tiny_async_fifo |
#( |
parameter W = 8 |
) |
( |
output wr_full, |
input [W-1:0] wr_data, |
input wr_en, |
input wr_clk, |
input wr_reset, |
|
output rd_empty, |
output [W-1:0] rd_data, |
input rd_en, |
input rd_clk, |
input rd_reset |
); |
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// -------------------------------------------------------------------- |
// |
wire writing = wr_en && ~wr_full; |
wire reading = rd_en && ~rd_empty; |
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// -------------------------------------------------------------------- |
// |
function logic [1:0] |
grey_counter_2_bit |
( |
input logic [1:0] count |
); |
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case(count) |
2'b00: grey_counter_2_bit = 2'b00; |
2'b01: grey_counter_2_bit = 2'b01; |
2'b10: grey_counter_2_bit = 2'b11; |
2'b11: grey_counter_2_bit = 2'b10; |
endcase |
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endfunction |
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// -------------------------------------------------------------------- |
// sync grey_wr_ptr to rd clk domain |
reg [1:0] grey_wr_ptr; |
reg [1:0] grey_wr_ptr_r; |
reg [1:0] grey_wr_ptr_s; |
|
always_ff @(posedge rd_clk) |
if(rd_reset) |
{grey_wr_ptr_s, grey_wr_ptr_r} <= 0; |
else |
{grey_wr_ptr_s, grey_wr_ptr_r} <= {grey_wr_ptr_r, grey_wr_ptr}; |
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// -------------------------------------------------------------------- |
// sync grey_rd_ptr to wr clk domain |
reg [1:0] grey_rd_ptr; |
reg [1:0] grey_rd_ptr_r; |
reg [1:0] grey_rd_ptr_s; |
|
always_ff @(posedge wr_clk) |
if(rd_reset) |
{grey_rd_ptr_s, grey_rd_ptr_r} <= 0; |
else |
{grey_rd_ptr_s, grey_rd_ptr_r} <= {grey_rd_ptr_r, grey_rd_ptr}; |
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// -------------------------------------------------------------------- |
// |
reg [1:0] bin_rd_ptr; |
wire [1:0] bin_rd_ptr_next = bin_rd_ptr + reading; |
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always_ff @(posedge rd_clk) |
if(rd_reset) |
bin_rd_ptr <= 0; |
else |
bin_rd_ptr <= bin_rd_ptr_next; |
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// -------------------------------------------------------------------- |
// |
wire [1:0] grey_rd_ptr_next = grey_counter_2_bit(bin_rd_ptr_next); |
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always_ff @(posedge rd_clk) |
if(rd_reset) |
grey_rd_ptr <= 0; |
else |
grey_rd_ptr <= grey_rd_ptr_next; |
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// -------------------------------------------------------------------- |
// |
reg asf_empty_r; |
|
always_ff @(posedge rd_clk) |
if(rd_reset) |
asf_empty_r <= 1; |
else |
asf_empty_r <= (grey_rd_ptr_next == grey_wr_ptr_s); |
|
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// -------------------------------------------------------------------- |
// |
reg [1:0] bin_wr_ptr; |
wire [1:0] bin_wr_ptr_next = bin_wr_ptr + writing; |
|
always_ff @(posedge wr_clk) |
if(wr_reset) |
bin_wr_ptr <= 0; |
else |
bin_wr_ptr <= bin_wr_ptr_next; |
|
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// -------------------------------------------------------------------- |
// |
wire [1:0] grey_wr_ptr_next = grey_counter_2_bit(bin_wr_ptr_next); |
|
always_ff @(posedge wr_clk) |
if(wr_reset) |
grey_wr_ptr <= 0; |
else |
grey_wr_ptr <= grey_wr_ptr_next; |
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// -------------------------------------------------------------------- |
// |
reg asf_full_r; |
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always_ff @(posedge wr_clk) |
if(wr_reset) |
asf_full_r <= 1; |
else |
asf_full_r <= (grey_wr_ptr_next == ~grey_rd_ptr_s); |
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// -------------------------------------------------------------------- |
// |
reg [W-1:0] data_0_r; |
reg [W-1:0] data_1_r; |
wire [W-1:0] rd_data_mux = bin_rd_ptr[0] ? data_1_r : data_0_r; |
assign rd_data = rd_data_mux; |
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always_ff @(posedge wr_clk) |
if (writing) |
if(bin_wr_ptr[0]) |
data_1_r <= wr_data; |
else |
data_0_r <= wr_data; |
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// -------------------------------------------------------------------- |
// |
assign rd_empty = asf_empty_r; |
assign wr_full = asf_full_r; |
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endmodule |
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/misc/barrel_shifter.v
File deleted