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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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    /qaz_libs/trunk/basal
    from Rev 43 to Rev 44
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Rev 43 → Rev 44

/sim/tests/tb_fifo/fifo_agent.svh
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class fifo_agent
extends uvm_agent;
`uvm_component_utils(fifo_agent)
 
// --------------------------------------------------------------------
virtual fifo_if #(.W(W), .D(D)) vif;
fifo_driver driver_h;
fifo_sequencer sequencer_h;
fifo_monitor monitor_h;
 
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver_h = fifo_driver::type_id::create("driver_h", this);
monitor_h = fifo_monitor ::type_id::create("monitor_h", this);
sequencer_h = fifo_sequencer::type_id::create("sequencer_h", this);
 
endfunction
 
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
 
driver_h.vif = vif;
monitor_h.vif = vif;
 
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
 
// --------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass : fifo_agent
/sim/tests/tb_fifo/fifo_driver.svh
0,0 → 1,88
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class fifo_driver
extends uvm_driver #(fifo_sequence_item);
`uvm_component_utils(fifo_driver)
 
// --------------------------------------------------------------------
virtual fifo_if #(.W(W), .D(D)) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.cb.wr_en <= 0;
vif.cb.rd_en <= 0;
vif.cb.wr_data <= 'x;
endfunction: set_default
 
//--------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
fifo_sequence_item item;
super.run_phase(phase);
 
set_default();
 
forever
begin
wait(~vif.cb.reset);
vif.zero_cycle_delay();
seq_item_port.get_next_item(item);
 
repeat(item.delay) @(vif.cb);
 
if((item.command == FIFO_WR) || (item.command == FIFO_BOTH))
begin
if(vif.wr_full)
`uvm_error(get_name(), "writing to full FIFO!")
vif.cb.wr_data <= item.wr_data;
vif.cb.wr_en <= 1;
end
 
if((item.command == FIFO_RD) || (item.command == FIFO_BOTH))
begin
if(vif.rd_empty)
`uvm_error(get_name(), "reading empty FIFO!")
item.rd_data = vif.cb.rd_data;
vif.cb.rd_en <= 1;
end
 
@(vif.cb);
item.wr_full = vif.wr_full;
item.rd_empty = vif.rd_empty;
item.count = vif.count;
set_default();
seq_item_port.item_done();
end
endtask : run_phase
 
//--------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass : fifo_driver
/sim/tests/tb_fifo/fifo_if.sv
0,0 → 1,70
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
interface
fifo_if
#(
W,
D,
UB = $clog2(D)
)
(
input reset,
input clk
);
import uvm_pkg::*;
`include "uvm_macros.svh"
import tb_fifo_pkg::*;
 
// --------------------------------------------------------------------
wire wr_full;
wire [W-1:0] wr_data;
wire wr_en;
wire rd_empty;
wire [W-1:0] rd_data;
wire rd_en;
wire [UB:0] count;
 
// --------------------------------------------------------------------
default clocking cb @(posedge clk);
input reset;
input wr_full;
input rd_empty;
input rd_data;
input count;
inout rd_en;
inout wr_en;
inout wr_data;
endclocking
 
// --------------------------------------------------------------------
task zero_cycle_delay;
##0;
endtask: zero_cycle_delay
 
// --------------------------------------------------------------------
endinterface
/sim/tests/tb_fifo/fifo_monitor.svh
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class fifo_monitor extends uvm_component;
`uvm_component_utils(fifo_monitor);
 
virtual fifo_if #(.W(W), .D(D)) vif;
uvm_analysis_port #(fifo_sequence_item) ap;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
ap = new("ap", this);
endfunction : build_phase
 
// --------------------------------------------------------------------
task run_phase(uvm_phase phase);
fifo_sequence_item item;
fifo_sequence_item c_item;
item = fifo_sequence_item::type_id::create("item");
 
forever @(vif.cb iff vif.cb.reset === 0)
if(vif.cb.wr_en || vif.cb.rd_en)
begin
$cast(c_item, item.clone);
c_item.wr_full = vif.cb.wr_full;
c_item.wr_data = vif.cb.wr_data;
c_item.rd_empty = vif.cb.rd_empty;
c_item.rd_data = vif.cb.rd_data;
c_item.count = vif.cb.count;
 
if(vif.cb.wr_en && vif.cb.rd_en)
c_item.command = FIFO_BOTH;
else if(vif.cb.wr_en)
c_item.command = FIFO_WR;
else if(vif.cb.rd_en)
c_item.command = FIFO_RD;
 
ap.write(c_item);
end
endtask : run_phase
 
// --------------------------------------------------------------------
endclass : fifo_monitor
/sim/tests/tb_fifo/fifo_scoreboard.svh
0,0 → 1,75
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class fifo_scoreboard extends uvm_subscriber #(fifo_sequence_item);
`uvm_component_utils(fifo_scoreboard);
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
endfunction : build_phase
 
// --------------------------------------------------------------------
mailbox #(fifo_sequence_item) mb = new();
fifo_sequence_item c_t;
fifo_sequence_item item;
int m_matches = 0;
int m_mismatches = 0;
 
function void write(fifo_sequence_item t);
 
$cast(c_t, t.clone);
 
if((c_t.command = FIFO_WR) || (c_t.command = FIFO_BOTH))
mb.try_put(c_t);
 
if((c_t.command = FIFO_RD) || (c_t.command = FIFO_BOTH))
mb.try_get(item);
 
if(~c_t.compare(item))
begin
uvm_report_info(get_name(), $sformatf("^^^ %16.t | %m | MISMATCH!!! | %s", $time, {20{"-"}}));
uvm_report_info(get_name(), c_t.convert2string);
uvm_report_info(get_name(), item.convert2string);
m_mismatches++;
end
else
m_matches++;
endfunction : write
 
// --------------------------------------------------------------------
function void report_phase(uvm_phase phase);
uvm_report_info(get_name(), $sformatf("Matches : %0d", m_matches));
uvm_report_info(get_name(), $sformatf("Mismatches: %0d", m_mismatches));
endfunction
 
// --------------------------------------------------------------------
endclass : fifo_scoreboard
/sim/tests/tb_fifo/fifo_sequence_item.svh
0,0 → 1,111
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class fifo_sequence_item
extends uvm_sequence_item;
`uvm_object_utils(fifo_sequence_item)
 
// --------------------------------------------------------------------
rand int delay;
rand fifo_command_t command;
rand logic [W-1:0] wr_data;
 
// --------------------------------------------------------------------
logic wr_full;
logic rd_empty;
logic [W-1:0] rd_data;
logic [UB:0] count;
 
// --------------------------------------------------------------------
constraint delay_c
{
delay dist {0 := 90, [1:2] := 7, [3:7] := 3};
}
 
// --------------------------------------------------------------------
function new(string name = "");
super.new(name);
endfunction : new
 
// --------------------------------------------------------------------
function bit do_compare(uvm_object rhs, uvm_comparer comparer);
fifo_sequence_item tested;
bit same;
 
if (rhs==null)
`uvm_fatal(get_type_name(), "| %m | comparison to a null pointer");
 
if (!$cast(tested,rhs))
same = 0;
else
same = super.do_compare(rhs, comparer);
 
return same;
endfunction : do_compare
 
// --------------------------------------------------------------------
function void do_copy(uvm_object rhs);
fifo_sequence_item item;
assert(rhs != null) else
`uvm_fatal(get_type_name(), "| %m | copy null transaction");
super.do_copy(rhs);
assert($cast(item,rhs)) else
`uvm_fatal(get_type_name(), "| %m | failed cast");
delay = item.delay;
command = item.command;
wr_full = item.wr_full;
rd_empty = item.rd_empty;
wr_data = item.wr_data;
rd_data = item.rd_data;
count = item.count;
endfunction : do_copy
 
// --------------------------------------------------------------------
function string convert2string();
string s0, s1, s2, s3;
s0 = $sformatf( "| %m | wr | rd | full | empty |\n");
s1 = $sformatf( "| %m | %1h | %1h | %1h | %1h |\n"
, (command == FIFO_WR) || (command == FIFO_BOTH)
, (command == FIFO_RD) || (command == FIFO_BOTH)
, wr_full
, rd_empty
);
s2 = $sformatf("| %m | wr_data: %h\n" , wr_data);
s3 = $sformatf("| %m | rd_data: %h\n" , rd_data);
 
if(command == FIFO_NULL)
return {s1, s0};
else if(command == FIFO_BOTH)
return {s3, s2, s1, s0};
else if(command == FIFO_WR)
return {s2, s1, s0};
else if(command == FIFO_RD)
return {s3, s1, s0};
endfunction : convert2string
 
// --------------------------------------------------------------------
endclass : fifo_sequence_item
/sim/tests/tb_fifo/files.f
0,0 → 1,3
#
 
${PROJECT_DIR}/src/FIFOs/sync_fifo.sv
/sim/tests/tb_fifo/init_test.do
0,0 → 1,29
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
# compile simulation files
vlog -f ./tb_files.f
 
#
vlog -f ./files.f
 
# run the sim
sim_run_test
 
 
/sim/tests/tb_fifo/s_debug.svh
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class s_debug
extends uvm_sequence #(fifo_sequence_item);
`uvm_object_utils(s_debug)
 
// --------------------------------------------------------------------
function new(string name = "s_debug");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
task body();
logic wr_full = 0;
logic rd_empty = 1;
int count;
fifo_sequence_item item;
fifo_sequence_item c_item;
item = fifo_sequence_item::type_id::create("item");
 
repeat(64)
begin
$cast(c_item, item.clone);
start_item(c_item);
assert(c_item.randomize());
if(wr_full)
c_item.command = FIFO_RD;
else if(rd_empty)
c_item.command = FIFO_WR;
finish_item(c_item);
wr_full = c_item.wr_full;
rd_empty = c_item.rd_empty;
end
 
count = c_item.count;
repeat(count)
begin
$cast(c_item, item.clone);
start_item(c_item);
assert(c_item.randomize());
c_item.command = FIFO_RD;
finish_item(c_item);
end
endtask: body
 
// --------------------------------------------------------------------
endclass : s_debug
/sim/tests/tb_fifo/sim.do
0,0 → 1,10
#
#
 
quit -sim
 
vsim -suppress 12110 -novopt work.tb_top
# vsim -f ./sim.f work.tb_top
 
# log all signals
log /* -r
/sim/tests/tb_fifo/t_debug.svh
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class t_debug extends t_top_base;
`uvm_component_utils(t_debug)
 
// --------------------------------------------------------------------
tb_dut_config #(.W(W), .D(D)) cfg_h;
 
// --------------------------------------------------------------------
function new(string name = "t_debug", uvm_component parent);
super.new(name, parent);
if (!uvm_config_db#(tb_dut_config #(.W(W), .D(D)))::get(this, "", "tb_dut_config", cfg_h))
`uvm_fatal(get_name(), "Couldn't get config object!")
endfunction
 
// --------------------------------------------------------------------
function void end_of_elaboration_phase(uvm_phase phase);
uvm_phase run_phase = uvm_run_phase::get();
run_phase.phase_done.set_drain_time(this, 100ns);
endfunction
 
// --------------------------------------------------------------------
function void final_phase(uvm_phase phase);
super.final_phase(phase);
$display("^^^ %16.t | %m | Test Done!!!", $time);
$stop;
endfunction : final_phase
 
// --------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
s_debug seq = s_debug::type_id::create("seq");
phase.raise_objection(this);
seq.start(env_h.agent_h.sequencer_h);
phase.drop_objection(this);
endtask : run_phase
 
// --------------------------------------------------------------------
endclass : t_debug
/sim/tests/tb_fifo/t_top_base.svh
0,0 → 1,43
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
virtual class t_top_base extends uvm_test;
`uvm_component_utils(t_top_base);
tb_env env_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
env_h = tb_env::type_id::create("env_h",this);
endfunction : build_phase
 
// --------------------------------------------------------------------
endclass : t_top_base
/sim/tests/tb_fifo/tb_dut_config.svh
0,0 → 1,48
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class tb_dut_config #(W, D);
 
virtual fifo_if #(.W(W), .D(D)) vif;
protected uvm_active_passive_enum is_active; // UVM_ACTIVE or UVM_PASSIVE
 
// --------------------------------------------------------------------
function new
( virtual fifo_if #(.W(W), .D(D)) vif
, uvm_active_passive_enum is_active = UVM_ACTIVE
);
this.vif = vif;
this.is_active = is_active;
endfunction : new
 
// --------------------------------------------------------------------
function uvm_active_passive_enum get_is_active();
return is_active;
endfunction : get_is_active
 
// --------------------------------------------------------------------
endclass : tb_dut_config
/sim/tests/tb_fifo/tb_env.svh
0,0 → 1,58
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class tb_env extends uvm_env;
`uvm_component_utils(tb_env);
 
// --------------------------------------------------------------------
tb_dut_config #(.W(W), .D(D)) cfg_h;
// coverage coverage_h;
fifo_scoreboard scoreboard_h;
fifo_agent agent_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
if (!uvm_config_db#(tb_dut_config #(.W(W), .D(D)))::get(this, "", "tb_dut_config", cfg_h))
`uvm_fatal(get_name(), "Couldn't get config object!")
 
agent_h = fifo_agent::type_id::create("agent_h", this);
agent_h.vif = cfg_h.vif;
scoreboard_h = fifo_scoreboard::type_id::create("scoreboard_h", this);
endfunction : build_phase
 
// --------------------------------------------------------------------
function void connect_phase(uvm_phase phase);
agent_h.monitor_h.ap.connect(scoreboard_h.analysis_export);
endfunction : connect_phase
 
// --------------------------------------------------------------------
endclass : tb_env
/sim/tests/tb_fifo/tb_fifo_pkg.sv
0,0 → 1,55
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package tb_fifo_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import bfm_pkg::*;
 
// --------------------------------------------------------------------
localparam W = 16;
localparam D = 8;
localparam UB = $clog2(D);
 
// --------------------------------------------------------------------
typedef enum {FIFO_RD, FIFO_WR, FIFO_BOTH, FIFO_NULL} fifo_command_t;
 
// --------------------------------------------------------------------
`include "tb_dut_config.svh"
`include "fifo_sequence_item.svh"
typedef uvm_sequencer #(fifo_sequence_item) fifo_sequencer;
`include "fifo_driver.svh"
`include "fifo_monitor.svh"
`include "fifo_scoreboard.svh"
`include "fifo_agent.svh"
`include "tb_env.svh"
`include "s_debug.svh"
`include "t_top_base.svh"
`include "t_debug.svh"
 
// --------------------------------------------------------------------
endpackage : tb_fifo_pkg
/sim/tests/tb_fifo/tb_files.f
0,0 → 1,6
#
 
./tb_fifo_pkg.sv
 
./fifo_if.sv
./tb_top.sv
/sim/tests/tb_fifo/tb_top.sv
0,0 → 1,73
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module tb_top;
import uvm_pkg::*;
import tb_fifo_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire clk_1000mhz;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire clk = clk_100mhz;
wire reset = tb_rst;
 
// --------------------------------------------------------------------
fifo_if #(.W(W), .D(D)) dut_if(.*);
 
sync_fifo #(.W(W), .D(D))
dut
(
.wr_full(dut_if.wr_full),
.wr_data(dut_if.wr_data),
.wr_en(dut_if.wr_en),
.rd_empty(dut_if.rd_empty),
.rd_data(dut_if.rd_data),
.rd_en(dut_if.rd_en),
.count(dut_if.count),
.clk(dut_if.clk),
.reset(dut_if.reset)
);
 
 
// --------------------------------------------------------------------
tb_dut_config #(.W(W), .D(D)) cfg_h = new(dut_if);
 
initial
begin
uvm_config_db #(tb_dut_config #(.W(W), .D(D)))::set(null, "*", "tb_dut_config", cfg_h);
run_test("t_debug");
end
 
// --------------------------------------------------------------------
endmodule
/sim/tests/tb_fifo/wip.do
0,0 → 1,6
#
 
# compile test bench files
vlog -f ./tb_files.f
vlog -f ./files.f
 

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