OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/video_frame_class/src/video_frame_class.sv
65,6 → 65,13
input int max_mismatches,
ref video_frame_class to
);
extern virtual function void print_line
(
input int line,
input int pixel,
input int count
);
 
endclass: video_frame_class
 
77,9 → 84,15
input int lines_per_frame,
input int bits_per_pixel
);
$display("^^^ %16.t | %m", $time);
this.pixels_per_line = pixels_per_line;
this.lines_per_frame = lines_per_frame;
this.bits_per_pixel = bits_per_pixel;
this.make_constant( 0 );
endfunction: init
 
 
89,6 → 102,8
(
input int pixel
);
$display("^^^ %16.t | %m", $time);
 
this.lines = new[lines_per_frame];
 
108,6 → 123,8
// --------------------------------------------------------------------
//
function void video_frame_class::make_counting();
$display("^^^ %16.t | %m", $time);
 
this.lines = new[lines_per_frame];
 
127,6 → 144,8
// --------------------------------------------------------------------
//
function void video_frame_class::make_random();
$display("^^^ %16.t | %m", $time);
 
this.lines = new[lines_per_frame];
 
149,6 → 168,8
(
ref video_frame_class to
);
$display("^^^ %16.t | %m", $time);
 
to.frame_id = this.frame_id;
to.pixels_per_line = this.pixels_per_line;
177,45 → 198,64
ref video_frame_class to
);
 
int mismatch_count = 0;
int mismatch_count = 0;
$display("^^^ %16.t | %m", $time);
 
if( to.pixels_per_line != this.pixels_per_line )
begin
$display( "^^^ %16.t | to.pixels_per_line != this.pixels_per_line", $time );
return( -1 );
end
if( to.pixels_per_line != this.pixels_per_line )
begin
$display( "^^^ %16.t | to.pixels_per_line != this.pixels_per_line", $time );
return( -1 );
end
 
if( to.lines_per_frame != this.lines_per_frame )
begin
$display( "^^^ %16.t | to.lines_per_frame != this.lines_per_frame", $time );
return( -2 );
end
if( to.lines_per_frame != this.lines_per_frame )
begin
$display( "^^^ %16.t | to.lines_per_frame != this.lines_per_frame", $time );
return( -2 );
end
 
if( to.bits_per_pixel != this.bits_per_pixel )
begin
$display( "^^^ %16.t | to.bits_per_pixel != this.bits_per_pixel", $time );
return( -3 );
end
 
foreach( this.lines[l] )
if( to.bits_per_pixel != this.bits_per_pixel )
begin
foreach( this.lines[l].pixel[p] )
if( to.lines[l].pixel[p] != this.lines[l].pixel[p] )
begin
$display( "^^^ %16.t | to.bits_per_pixel != this.bits_per_pixel", $time );
return( -3 );
end
 
if( max_mismatches > 0 )
mismatch_count++;
foreach( this.lines[l] )
begin
foreach( this.lines[l].pixel[p] )
if( to.lines[l].pixel[p] != this.lines[l].pixel[p] )
begin
 
$display( "^^^ %16.t | mismatch @ frame[%4h][%4h] | to == %4h | this == %4h ", $time, l, p, to.lines[l].pixel[p], this.lines[l].pixel[p] );
if( max_mismatches > 0 )
mismatch_count++;
 
if( mismatch_count > max_mismatches )
return( -4 );
$display( "^^^ %16.t | mismatch @ frame[%4h][%4h] | to == %4h | this == %4h ", $time, l, p, to.lines[l].pixel[p], this.lines[l].pixel[p] );
 
end
end
if( mismatch_count > max_mismatches )
return( mismatch_count );
 
return( mismatch_count );
end
end
 
return( mismatch_count );
 
endfunction: compare
 
 
// --------------------------------------------------------------------
//
function void video_frame_class::print_line
(
input int line,
input int pixel,
input int count
);
 
$display("^^^ %16.t | %m", $time);
for( int i = 0; i < count; i++ )
$display( "^^^ %16.t | %4h @ frame[%4h][%4h]", $time, this.lines[line].pixel[(pixel + i)], line, pixel );
 
endfunction: print_line
 
 
/video_frame_class/sim/scripts/sim_procs.do
3,13 → 3,14
# ------------------------------------
 
 
# ------------------------------------
#
proc sim_compile_all { target } {
 
global env
# sim_make_version
 
set env(ROOT_DIR) ../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) $target
 
if {[file exists work/_info]} {
21,21 → 22,41
vlib work
}
 
vlog -O0 -f ../../libs/sim_files.txt
if { [file exists ../../libs/altera_sim.f] } {
vlog -O0 -f ../../libs/altera_sim.f
} elseif {[file exists ../../libs/xilinx_sim.f]} {
vlog -O0 -f ../../libs/xilinx_sim.f
}
 
if {[file exists ../../libs/libs_files.txt]} {
vlog -O0 -f ../../libs/libs_files.txt
foreach filename [glob -nocomplain -directory ../../libs/FPGA_verilog/ *.f] {
echo "INFO: compiling $filename"
vlog -O0 -f $filename
}
if {[file exists ../../libs/opencores_files.txt]} {
vlog -O0 -f ../../libs/opencores_files.txt
foreach filename [glob -nocomplain -directory ../../libs/FPGA_VHDL/ *.f] {
echo "INFO: compiling $filename"
vcom -explicit -O0 -f $filename
}
 
foreach filename [glob -nocomplain -directory ../../libs/sim_verilog/ *.f] {
echo "INFO: compiling $filename"
vlog -O0 -f $filename
}
foreach filename [glob -nocomplain -directory ../../libs/sim_VHDL/ *.f] {
echo "INFO: compiling $filename"
vcom -explicit -O0 -f $filename
}
switch $target {
 
"rtl" {
echo "INFO: compiling FPGA rtl"
vlog -O0 -f ../../libs/fpga_files.txt
foreach filename [glob -nocomplain -directory ../../libs/FPGA/ *.f] {
echo "INFO: compiling $filename"
# vlog -O0 -f $filename
vcom -93 -explicit -O0 -f $filename
}
}
 
default {
46,6 → 67,28
}
 
 
# ------------------------------------
#
proc sim_run_sim { } {
 
if {[file exists ./sim.do]} {
do ./sim.do
} elseif {[file exists ../../libs/sim.do]} {
do ../../libs/sim.do
} elseif {[file exists ../../libs/altera_sim.f]} {
vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top
} elseif {[file exists ../../libs/xilinx_sim.f]} {
vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl
}
if { [file exists ./wave.do] } {
do ./wave.do
}
}
 
 
# ------------------------------------
#
proc sim_run_test { } {
 
global env
56,8 → 99,6
vlib work
}
 
vlog ./the_test.sv
 
# unique setup
if { [file exists ./setup_test.do] } {
do ./setup_test.do
68,44 → 109,36
vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v
 
} else {
vlog ../../src/tb_top.v
 
vsim -novopt -t 1ps -f ../../libs/altera_sim_files.txt -l transcript.txt work.tb_top
 
if { [file exists ./wave.do] } {
do ./wave.do
}
sim_run_sim
}
 
radix -hexadecimal
 
run -all
 
}
 
 
# ------------------------------------
#
proc sim_restart { } {
 
global env
# unique setup
if { [file exists ./setup_test.do] } {
do ./setup_test.do
}
 
# work in progress files to compile
if { [file exists ./wip.do] } {
echo "INFO: found ./wip.do"
do ./wip.do
} else {
# sim_make_version
 
sim_compile_all $::env(SIM_TARGET)
vlog ./the_test.sv
vlog ../../src/tb_top.v
}
restart -force
if { [string equal nodesign [runStatus]] } {
sim_run_sim
} else {
restart -force
}
 
run -all
 
}
/video_frame_class/sim/scripts/sim_debug_init.do
8,9 → 8,11
 
set env(SIM_TARGET) rtl
 
 
radix -hexadecimal
 
sim_compile_all rtl
# do ./setup_test.do
# sim_compile_all rtl
sim_run_test
 
 
/tb_class/sim/tests/debug/the_test.sv
0,0 → 1,38
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module the_test(
input tb_clk,
input tb_rst
);
 
 
// --------------------------------------------------------------------
//
task run_the_test;
begin
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
 
repeat(1000) @(posedge tb_clk);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
end
endtask
 
 
endmodule
 
/tb_class/sim/scripts/sim_procs.do
0,0 → 1,146
# ------------------------------------
#
# ------------------------------------
 
 
# ------------------------------------
#
proc sim_compile_all { target } {
 
global env
 
set env(ROOT_DIR) ../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) $target
 
if {[file exists work/_info]} {
echo "INFO: Simulation library work already exists"
echo "INFO: deleting ./work and recompiling all"
file delete -force ./work
vlib work
} else {
vlib work
}
 
if { [file exists ../../libs/altera_sim.f] } {
vlog -O0 -f ../../libs/altera_sim.f
} elseif {[file exists ../../libs/xilinx_sim.f]} {
vlog -O0 -f ../../libs/xilinx_sim.f
}
 
foreach filename [glob -nocomplain -directory ../../libs/FPGA_verilog/ *.f] {
echo "INFO: compiling $filename"
vlog -O0 -f $filename
}
foreach filename [glob -nocomplain -directory ../../libs/FPGA_VHDL/ *.f] {
echo "INFO: compiling $filename"
vcom -explicit -O0 -f $filename
}
foreach filename [glob -nocomplain -directory ../../libs/sim_verilog/ *.f] {
echo "INFO: compiling $filename"
vlog -O0 -f $filename
}
foreach filename [glob -nocomplain -directory ../../libs/sim_VHDL/ *.f] {
echo "INFO: compiling $filename"
vcom -explicit -O0 -f $filename
}
switch $target {
 
"rtl" {
echo "INFO: compiling FPGA rtl"
foreach filename [glob -nocomplain -directory ../../libs/FPGA/ *.f] {
echo "INFO: compiling $filename"
# vlog -O0 -f $filename
vcom -93 -explicit -O0 -f $filename
}
}
 
default {
echo "ERROR: <$target> Target not suported!!!"
}
}
 
}
 
 
# ------------------------------------
#
proc sim_run_sim { } {
 
if {[file exists ./sim.do]} {
do ./sim.do
} elseif {[file exists ../../libs/sim.do]} {
do ../../libs/sim.do
} elseif {[file exists ../../libs/altera_sim.f]} {
vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top
} elseif {[file exists ../../libs/xilinx_sim.f]} {
vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl
}
if { [file exists ./wave.do] } {
do ./wave.do
}
}
 
 
# ------------------------------------
#
proc sim_run_test { } {
 
global env
 
if { [file exists work/_info] } {
echo "INFO: Simulation library work already exists"
} else {
vlib work
}
 
# unique setup
if { [file exists ./setup_test.do] } {
do ./setup_test.do
}
 
if { [info exists env(MAKEFILE_TEST_RUN)] } {
 
vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v
 
} else {
 
sim_run_sim
}
 
run -all
 
}
 
 
# ------------------------------------
#
proc sim_restart { } {
 
global env
 
# work in progress files to compile
if { [file exists ./wip.do] } {
echo "INFO: found ./wip.do"
do ./wip.do
} else {
 
sim_compile_all $::env(SIM_TARGET)
}
if { [string equal nodesign [runStatus]] } {
sim_run_sim
} else {
restart -force
}
 
run -all
 
}
 
 
/tb_class/sim/scripts/sim_debug_init.do
0,0 → 1,19
# ------------------------------------
#
# ------------------------------------
 
do ../../scripts/sim_procs.do
 
global env
 
set env(SIM_TARGET) rtl
 
 
radix -hexadecimal
 
# do ./setup_test.do
# sim_compile_all rtl
sim_run_test
 
 
 
/tb_class/sim/scripts/sim_run_test.do
0,0 → 1,13
# ------------------------------------
#
# ------------------------------------
 
do ../../scripts/sim_procs.do
 
 
sim_run_test
 
quit
 
 
 
/tb_class/sim/src/tb_top.v
0,0 → 1,100
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`timescale 1ps/1ps
 
 
module tb_top();
 
// --------------------------------------------------------------------
// system wires
wire CLK_20;
wire CLK_50;
wire CLK_100;
wire CLK_125;
wire CLK_156_25;
 
wire tb_clk = CLK_50;
 
wire tb_rst;
 
 
// --------------------------------------------------------------------
// clock & reset
parameter CLK_PERIOD = 2000;
 
tb_clk #( .CLK_PERIOD(5000) ) i_CLK_20 ( CLK_20 );
tb_clk #( .CLK_PERIOD(2000) ) i_CLK_50 ( CLK_50 );
tb_clk #( .CLK_PERIOD(1000) ) i_CLK_100 ( CLK_100 );
tb_clk #( .CLK_PERIOD(640) ) i_CLK_156_25 ( CLK_156_25 );
tb_clk #( .CLK_PERIOD(800) ) i_CLK_125 ( CLK_125 );
 
tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst );
 
initial
begin
$display("\n^^^---------------------------------");
i_tb_rst.assert_delayed_reset(CLK_PERIOD/3);
end
 
// --------------------------------------------------------------------
//
 
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
 
 
// --------------------------------------------------------------------
//
tb_log log();
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
log.log_fail_count();
$display("^^^---------------------------------");
 
`ifdef MAKEFILE_TEST_RUN
$finish();
`else
$stop();
`endif
 
end
 
endmodule
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.