URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk
- from Rev 27 to Rev 26
- ↔ Reverse comparison
Rev 27 → Rev 26
/synchronize/src/synchronizer.v
File deleted
/synchronize/src/sync_reset.v
File deleted
/synchronize/src/debounce_high.v
File deleted
/synchronize/src/debounce.v
File deleted
/synchronize/src/debounce_low.v
File deleted
/tb_class/sim/tests/debug/the_test.sv
0,0 → 1,38
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module the_test( |
input tb_clk, |
input tb_rst |
); |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
begin |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
|
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repeat(1000) @(posedge tb_clk); |
|
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
end |
endtask |
|
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endmodule |
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/tb_class/sim/scripts/sim_procs.do
0,0 → 1,146
# ------------------------------------ |
# |
# ------------------------------------ |
|
|
# ------------------------------------ |
# |
proc sim_compile_all { target } { |
|
global env |
|
set env(ROOT_DIR) ../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) $target |
|
if {[file exists work/_info]} { |
echo "INFO: Simulation library work already exists" |
echo "INFO: deleting ./work and recompiling all" |
file delete -force ./work |
vlib work |
} else { |
vlib work |
} |
|
if { [file exists ../../libs/altera_sim.f] } { |
vlog -O0 -f ../../libs/altera_sim.f |
} elseif {[file exists ../../libs/xilinx_sim.f]} { |
vlog -O0 -f ../../libs/xilinx_sim.f |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/FPGA_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/FPGA_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/sim_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -O0 -f $filename |
} |
|
foreach filename [glob -nocomplain -directory ../../libs/sim_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -O0 -f $filename |
} |
|
switch $target { |
|
"rtl" { |
echo "INFO: compiling FPGA rtl" |
foreach filename [glob -nocomplain -directory ../../libs/FPGA/ *.f] { |
echo "INFO: compiling $filename" |
# vlog -O0 -f $filename |
vcom -93 -explicit -O0 -f $filename |
} |
} |
|
default { |
echo "ERROR: <$target> Target not suported!!!" |
} |
} |
|
} |
|
|
# ------------------------------------ |
# |
proc sim_run_sim { } { |
|
if {[file exists ./sim.do]} { |
do ./sim.do |
} elseif {[file exists ../../libs/sim.do]} { |
do ../../libs/sim.do |
} elseif {[file exists ../../libs/altera_sim.f]} { |
vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top |
} elseif {[file exists ../../libs/xilinx_sim.f]} { |
vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl |
} |
|
if { [file exists ./wave.do] } { |
do ./wave.do |
} |
} |
|
|
# ------------------------------------ |
# |
proc sim_run_test { } { |
|
global env |
|
if { [file exists work/_info] } { |
echo "INFO: Simulation library work already exists" |
} else { |
vlib work |
} |
|
# unique setup |
if { [file exists ./setup_test.do] } { |
do ./setup_test.do |
} |
|
if { [info exists env(MAKEFILE_TEST_RUN)] } { |
|
vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v |
|
} else { |
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sim_run_sim |
} |
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run -all |
|
} |
|
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# ------------------------------------ |
# |
proc sim_restart { } { |
|
global env |
|
# work in progress files to compile |
if { [file exists ./wip.do] } { |
echo "INFO: found ./wip.do" |
do ./wip.do |
} else { |
|
sim_compile_all $::env(SIM_TARGET) |
} |
|
if { [string equal nodesign [runStatus]] } { |
sim_run_sim |
} else { |
restart -force |
} |
|
run -all |
|
} |
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/tb_class/sim/scripts/sim_debug_init.do
0,0 → 1,19
# ------------------------------------ |
# |
# ------------------------------------ |
|
do ../../scripts/sim_procs.do |
|
global env |
|
set env(SIM_TARGET) rtl |
|
|
radix -hexadecimal |
|
# do ./setup_test.do |
# sim_compile_all rtl |
sim_run_test |
|
|
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/tb_class/sim/scripts/sim_run_test.do
0,0 → 1,13
# ------------------------------------ |
# |
# ------------------------------------ |
|
do ../../scripts/sim_procs.do |
|
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sim_run_test |
|
quit |
|
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/tb_class/sim/src/tb_top.v
0,0 → 1,100
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
`timescale 1ps/1ps |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// system wires |
wire CLK_20; |
wire CLK_50; |
wire CLK_100; |
wire CLK_125; |
wire CLK_156_25; |
|
wire tb_clk = CLK_50; |
|
wire tb_rst; |
|
|
// -------------------------------------------------------------------- |
// clock & reset |
parameter CLK_PERIOD = 2000; |
|
tb_clk #( .CLK_PERIOD(5000) ) i_CLK_20 ( CLK_20 ); |
tb_clk #( .CLK_PERIOD(2000) ) i_CLK_50 ( CLK_50 ); |
tb_clk #( .CLK_PERIOD(1000) ) i_CLK_100 ( CLK_100 ); |
tb_clk #( .CLK_PERIOD(640) ) i_CLK_156_25 ( CLK_156_25 ); |
tb_clk #( .CLK_PERIOD(800) ) i_CLK_125 ( CLK_125 ); |
|
tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst ); |
|
initial |
begin |
$display("\n^^^---------------------------------"); |
i_tb_rst.assert_delayed_reset(CLK_PERIOD/3); |
end |
|
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// -------------------------------------------------------------------- |
// |
|
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
|
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// -------------------------------------------------------------------- |
// |
tb_log log(); |
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// debug wires |
|
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
log.log_fail_count(); |
$display("^^^---------------------------------"); |
|
`ifdef MAKEFILE_TEST_RUN |
$finish(); |
`else |
$stop(); |
`endif |
|
end |
|
endmodule |
|
|
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/FIFOs/syn/tiny_async_fifo/tiny_async_fifo.xpr
File deleted
/FIFOs/src/zedboard_tiny_async_fifo/top.v
File deleted
/FIFOs/src/tiny_async_fifo.sv
File deleted
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/wptr_full.v
2,49 → 2,32
// |
|
|
module |
wptr_full |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg wfull, |
output [ADDRSIZE-1:0] waddr, |
output reg [ADDRSIZE :0] wptr, |
input [ADDRSIZE :0] wq2_rptr, |
input winc, |
input wclk, |
input wrst_n |
); |
|
reg [ADDRSIZE:0] wbin; |
wire [ADDRSIZE:0] wgraynext, wbinnext; |
|
// GRAYSTYLE2 pointer |
always @(posedge wclk or negedge wrst_n) |
if(!wrst_n) |
{wbin, wptr} <= 0; |
else |
{wbin, wptr} <= {wbinnext, wgraynext}; |
|
// Memory write-address pointer (okay to use binary to address memory) |
assign waddr = wbin[ADDRSIZE-1:0]; |
assign wbinnext = wbin + (winc & ~wfull); |
assign wgraynext = (wbinnext>>1) ^ wbinnext; |
|
//------------------------------------------------------------------ |
// Simplified version of the three necessary full-tests: |
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && |
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && |
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); |
//------------------------------------------------------------------ |
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]}); |
|
always @(posedge wclk or negedge wrst_n) |
if(!wrst_n) |
wfull <= 1'b0; |
else |
wfull <= wfull_val; |
|
module wptr_full #(parameter ADDRSIZE = 4) |
(output reg wfull, |
output [ADDRSIZE-1:0] waddr, |
output reg [ADDRSIZE :0] wptr, |
input [ADDRSIZE :0] wq2_rptr, |
input winc, wclk, wrst_n); |
reg [ADDRSIZE:0] wbin; |
wire [ADDRSIZE:0] wgraynext, wbinnext; |
// GRAYSTYLE2 pointer |
always @(posedge wclk or negedge wrst_n) |
if (!wrst_n) {wbin, wptr} <= 0; |
else {wbin, wptr} <= {wbinnext, wgraynext}; |
// Memory write-address pointer (okay to use binary to address memory) |
assign waddr = wbin[ADDRSIZE-1:0]; |
assign wbinnext = wbin + (winc & ~wfull); |
assign wgraynext = (wbinnext>>1) ^ wbinnext; |
//------------------------------------------------------------------ |
// Simplified version of the three necessary full-tests: |
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && |
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && |
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); |
//------------------------------------------------------------------ |
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], |
wq2_rptr[ADDRSIZE-2:0]}); |
always @(posedge wclk or negedge wrst_n) |
if (!wrst_n) wfull <= 1'b0; |
else wfull <= wfull_val; |
endmodule |
|
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifomem.v
2,46 → 2,25
// |
|
|
module |
fifomem |
#( |
parameter DATASIZE = 8, // Memory data word width |
parameter ADDRSIZE = 4 // Number of mem address bits |
) |
( |
output [DATASIZE-1:0] rdata, |
input [DATASIZE-1:0] wdata, |
input [ADDRSIZE-1:0] waddr, |
input [ADDRSIZE-1:0] raddr, |
input wclken, |
input wfull, |
input wclk |
); |
|
module fifomem #(parameter DATASIZE = 8, // Memory data word width |
parameter ADDRSIZE = 4) // Number of mem address bits |
(output [DATASIZE-1:0] rdata, |
input [DATASIZE-1:0] wdata, |
input [ADDRSIZE-1:0] waddr, raddr, |
input wclken, wfull, wclk); |
`ifdef VENDORRAM |
// instantiation of a vendor's dual-port RAM |
vendor_ram |
mem |
( |
.dout(rdata), |
.din(wdata), |
.waddr(waddr), |
.raddr(raddr), |
.wclken(wclken), |
.wclken_n(wfull), |
.clk(wclk) |
); |
// instantiation of a vendor's dual-port RAM |
vendor_ram mem (.dout(rdata), .din(wdata), |
.waddr(waddr), .raddr(raddr), |
.wclken(wclken), |
.wclken_n(wfull), .clk(wclk)); |
`else |
// RTL Verilog memory model |
localparam DEPTH = 1<<ADDRSIZE; |
reg [DATASIZE-1:0] mem [0:DEPTH-1]; |
assign rdata = mem[raddr]; |
|
always @(posedge wclk) |
if(wclken && !wfull) |
mem[waddr] <= wdata; |
|
// RTL Verilog memory model |
localparam DEPTH = 1<<ADDRSIZE; |
reg [DATASIZE-1:0] mem [0:DEPTH-1]; |
assign rdata = mem[raddr]; |
always @(posedge wclk) |
if (wclken && !wfull) mem[waddr] <= wdata; |
`endif |
|
endmodule |
|
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/fifo1.v
2,52 → 2,35
// |
|
|
module |
fifo1 |
#( |
parameter DSIZE = 8, |
parameter ASIZE = 4 |
) |
( |
output [DSIZE-1:0] rdata, |
output wfull, |
output rempty, |
input [DSIZE-1:0] wdata, |
input winc, |
input wclk, |
input wrst_n, |
input rinc, |
input rclk, |
input rrst_n |
); |
|
wire [ASIZE-1:0] waddr, raddr; |
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; |
|
sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr), |
.wclk(wclk), .wrst_n(wrst_n)); |
|
sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr), |
.rclk(rclk), .rrst_n(rrst_n)); |
|
fifomem #(DSIZE, ASIZE) fifomem |
(.rdata(rdata), .wdata(wdata), |
.waddr(waddr), .raddr(raddr), |
.wclken(winc), .wfull(wfull), |
.wclk(wclk)); |
|
rptr_empty #(ASIZE) rptr_empty |
(.rempty(rempty), |
.raddr(raddr), |
.rptr(rptr), .rq2_wptr(rq2_wptr), |
.rinc(rinc), .rclk(rclk), |
.rrst_n(rrst_n)); |
|
wptr_full #(ASIZE) wptr_full |
(.wfull(wfull), .waddr(waddr), |
.wptr(wptr), .wq2_rptr(wq2_rptr), |
.winc(winc), .wclk(wclk), |
.wrst_n(wrst_n)); |
|
module fifo1 #(parameter DSIZE = 8, |
parameter ASIZE = 4) |
(output [DSIZE-1:0] rdata, |
output wfull, |
output rempty, |
input [DSIZE-1:0] wdata, |
input winc, wclk, wrst_n, |
input rinc, rclk, rrst_n); |
wire [ASIZE-1:0] waddr, raddr; |
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; |
sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr), |
.wclk(wclk), .wrst_n(wrst_n)); |
sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr), |
.rclk(rclk), .rrst_n(rrst_n)); |
fifomem #(DSIZE, ASIZE) fifomem |
(.rdata(rdata), .wdata(wdata), |
.waddr(waddr), .raddr(raddr), |
.wclken(winc), .wfull(wfull), |
.wclk(wclk)); |
rptr_empty #(ASIZE) rptr_empty |
(.rempty(rempty), |
.raddr(raddr), |
.rptr(rptr), .rq2_wptr(rq2_wptr), |
.rinc(rinc), .rclk(rclk), |
.rrst_n(rrst_n)); |
wptr_full #(ASIZE) wptr_full |
(.wfull(wfull), .waddr(waddr), |
.wptr(wptr), .wq2_rptr(wq2_rptr), |
.winc(winc), .wclk(wclk), |
.wrst_n(wrst_n)); |
endmodule |
|
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/rptr_empty.v
2,48 → 2,30
// |
|
|
module |
rptr_empty |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg rempty, |
output [ADDRSIZE-1:0] raddr, |
output reg [ADDRSIZE :0] rptr, |
input [ADDRSIZE :0] rq2_wptr, |
input rinc, |
input rclk, |
input rrst_n |
); |
|
reg [ADDRSIZE:0] rbin; |
wire [ADDRSIZE:0] rgraynext, rbinnext; |
|
//------------------- |
// GRAYSTYLE2 pointer |
//------------------- |
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
{rbin, rptr} <= 0; |
else |
{rbin, rptr} <= {rbinnext, rgraynext}; |
|
// Memory read-address pointer (okay to use binary to address memory) |
assign raddr = rbin[ADDRSIZE-1:0]; |
assign rbinnext = rbin + (rinc & ~rempty); |
assign rgraynext = (rbinnext>>1) ^ rbinnext; |
|
//--------------------------------------------------------------- |
// FIFO empty when the next rptr == synchronized wptr or on reset |
//--------------------------------------------------------------- |
assign rempty_val = (rgraynext == rq2_wptr); |
|
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
rempty <= 1'b1; |
else |
rempty <= rempty_val; |
|
module rptr_empty #(parameter ADDRSIZE = 4) |
(output reg rempty, |
output [ADDRSIZE-1:0] raddr, |
output reg [ADDRSIZE :0] rptr, |
input [ADDRSIZE :0] rq2_wptr, |
input rinc, rclk, rrst_n); |
reg [ADDRSIZE:0] rbin; |
wire [ADDRSIZE:0] rgraynext, rbinnext; |
//------------------- |
// GRAYSTYLE2 pointer |
//------------------- |
always @(posedge rclk or negedge rrst_n) |
if (!rrst_n) {rbin, rptr} <= 0; |
else {rbin, rptr} <= {rbinnext, rgraynext}; |
// Memory read-address pointer (okay to use binary to address memory) |
assign raddr = rbin[ADDRSIZE-1:0]; |
assign rbinnext = rbin + (rinc & ~rempty); |
assign rgraynext = (rbinnext>>1) ^ rbinnext; |
//--------------------------------------------------------------- |
// FIFO empty when the next rptr == synchronized wptr or on reset |
//--------------------------------------------------------------- |
assign rempty_val = (rgraynext == rq2_wptr); |
always @(posedge rclk or negedge rrst_n) |
if (!rrst_n) rempty <= 1'b1; |
else rempty <= rempty_val; |
endmodule |
|
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_w2r.v
2,25 → 2,13
// |
|
|
module |
sync_w2r |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg [ADDRSIZE:0] rq2_wptr, |
input [ADDRSIZE:0] wptr, |
input rclk, |
input rrst_n |
); |
|
reg [ADDRSIZE:0] rq1_wptr; |
|
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
{rq2_wptr,rq1_wptr} <= 0; |
else |
{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; |
|
module sync_w2r #(parameter ADDRSIZE = 4) |
(output reg [ADDRSIZE:0] rq2_wptr, |
input [ADDRSIZE:0] wptr, |
input rclk, rrst_n); |
reg [ADDRSIZE:0] rq1_wptr; |
always @(posedge rclk or negedge rrst_n) |
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0; |
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; |
endmodule |
|
/FIFOs/src/CummingsSNUG2002SJ_FIFO1/sync_r2w.v
2,25 → 2,13
// |
|
|
module |
sync_r2w |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg [ADDRSIZE:0] wq2_rptr, |
input [ADDRSIZE:0] rptr, |
input wclk, |
input wrst_n |
); |
|
reg [ADDRSIZE:0] wq1_rptr; |
|
always @(posedge wclk or negedge wrst_n) |
if (!wrst_n) |
{wq2_rptr,wq1_rptr} <= 0; |
else |
{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; |
|
module sync_r2w #(parameter ADDRSIZE = 4) |
(output reg [ADDRSIZE:0] wq2_rptr, |
input [ADDRSIZE:0] rptr, |
input wclk, wrst_n); |
reg [ADDRSIZE:0] wq1_rptr; |
always @(posedge wclk or negedge wrst_n) |
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0; |
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; |
endmodule |
|
/FIFOs/src/tiny_sync_fifo.sv
80,12 → 80,12
// |
reg [W - 1:0] data_0_r; |
reg [W - 1:0] data_1_r; |
wire [W - 1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r; |
wire [W - 1:0] wr_data_mux = rd_ptr_r ? data_1_r : data_0_r; |
assign sink.rd_data = wr_data_mux; |
|
always_ff @(posedge source.clk) |
if (writing) |
if(wr_ptr_r[0]) |
if(wr_ptr_r) |
data_1_r <= source.wr_data; |
else |
data_0_r <= source.wr_data; |
93,8 → 93,8
|
// -------------------------------------------------------------------- |
// |
assign sink.empty = empty_r; |
assign source.full = full_r; |
assign sink.empty = empty_r; |
assign source.full = full_r; |
|
|
endmodule |
/FIFOs/sim/tests/tiny_async_fifo/wip.do
File deleted
/FIFOs/sim/tests/tiny_async_fifo/init_test.do
File deleted
/FIFOs/sim/tests/tiny_async_fifo/the_test.sv
File deleted
/FIFOs/sim/tests/tiny_async_fifo/sim.do
File deleted
/FIFOs/sim/src/tb_tiny_async_fifo.sv
File deleted
/FIFOs/sim/libs/async_fifo_verilog/tiny_async_fifo.f
File deleted
/video_frame_class/src/video_frame_pkg.sv
101,22 → 101,19
( |
input frame_coordinate_t coordinate, |
input int pixel |
); |
); |
|
extern virtual function int read_pixel |
( |
input frame_coordinate_t coordinate |
); |
); |
|
extern virtual function void make_constant |
( |
input int pixel |
); |
); |
|
extern virtual function void make_counting |
( |
input int offset = 0 |
); |
extern virtual function void make_counting(); |
|
extern virtual function void make_horizontal(); |
|
127,7 → 124,7
extern virtual function void copy |
( |
ref video_frame_class from |
); |
); |
|
extern virtual function video_frame_class clone(); |
|
203,10 → 200,7
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// -------------------------------------------------------------------- |
// |
function void video_frame_class::make_counting |
( |
input int offset = 0 |
); |
function void video_frame_class::make_counting(); |
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$display("^^^ %16.t | %m", $time); |
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218,7 → 212,7
this.lines[l].pixel = new[pixels_per_line]; |
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foreach(this.lines[l].pixel[p]) |
this.lines[l].pixel[p] = (pixels_per_line * l) + p + offset; |
this.lines[l].pixel[p] = (pixels_per_line * l) + p; |
|
end |
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301,7 → 295,7
function void video_frame_class::copy |
( |
ref video_frame_class from |
); |
); |
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$display("^^^ %16.t | %m", $time); |
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/camera_link/src/camera_link.v
File deleted
/camera_link/src/channel_link.v
File deleted
/camera_link/src/channel_link_if.sv
File deleted
/camera_link/src/camera_link_if.sv
File deleted
/camera_link/sim/src/cl_util.v
File deleted
/camera_link/sim/src/cl_line_scan_checker.v
File deleted
/camera_link/sim/src/cl_area_scan_checker.v
File deleted
/camera_link/sim/src/camera_link_clk.v
File deleted
/camera_link/sim/src/tb_channel_link_rx_if.sv
File deleted
/axis_video_frame_bfm_class/sim/src/tb_1_tile_4_outputs.sv
85,6 → 85,9
); |
|
avf_agent_config_h.tile[0].direction = RIGHT_DOWN; |
avf_agent_config_h.tile[1].direction = RIGHT_UP; |
avf_agent_config_h.tile[2].direction = LEFT_DOWN; |
avf_agent_config_h.tile[3].direction = LEFT_UP; |
|
avf_agent_h = new |
( |
/misc/src/pulse_stretcher.v
File deleted
/misc/src/sr_latch.v
File deleted
/misc/src/bit_connect_little_to_big.v
File deleted
/misc/src/bit_connect_big_to_little.v
File deleted
/misc/src/bit_swap_big_to_little.v
File deleted
/misc/src/bit_swap_little_to_big.v
File deleted
/cli/cli/sys_cmd.h
33,7 → 33,7
#define MAX_CMD_LENGTH 20 |
#define MAX_CLI_ARGC 6 |
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#include <xil_printf.h> |
// #include <xil_printf.h> |
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// #define ANSI_ESCAPE_CODE |
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/cli/util/uboot_lib.h
37,8 → 37,6
#include <stdio.h> |
#include <ctype.h> |
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#include "xil_printf.h" |
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#undef CONFIG_ARCH_MAP_SYSMEM |
#include "mapmem.h" |
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/cli/util/types.h
31,17 → 31,17
// /* |
// * These aren't exported outside the kernel to avoid name space clashes |
// */ |
// typedef signed char s8; |
// typedef unsigned char u8; |
typedef signed char s8; |
typedef unsigned char u8; |
|
// typedef signed short s16; |
// typedef unsigned short u16; |
typedef signed short s16; |
typedef unsigned short u16; |
|
// typedef signed int s32; |
// typedef unsigned int u32; |
typedef signed int s32; |
typedef unsigned int u32; |
|
// typedef signed long long s64; |
// typedef unsigned long long u64; |
typedef signed long long s64; |
typedef unsigned long long u64; |
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// #define BITS_PER_LONG 32 |
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/zed_board/block_diagrams/zync_bd_14_4.tcl
File deleted
/zed_board/block_diagrams/zync_bd_16_2.tcl
File deleted
/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.xpr
File deleted
/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.tcl
File deleted
/zed_board/syn/vivado_14_4/vivado_14_4.xpr
File deleted
/zed_board/syn/vivado_16_2/vivado_16_2.xpr
File deleted
/zed_board/syn/axi_lite_to_wbl.tcl
68,10 → 68,10
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# Create 'synth_1' run (if not found) |
if {[string equal [get_runs -quiet synth_1] ""]} { |
create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 |
create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 |
} else { |
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] |
set_property flow "Vivado Synthesis 2016" [get_runs synth_1] |
set_property flow "Vivado Synthesis 2014" [get_runs synth_1] |
} |
set obj [get_runs synth_1] |
|
80,10 → 80,10
|
# Create 'impl_1' run (if not found) |
if {[string equal [get_runs -quiet impl_1] ""]} { |
create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 |
create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 |
} else { |
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] |
set_property flow "Vivado Implementation 2016" [get_runs impl_1] |
set_property flow "Vivado Implementation 2014" [get_runs impl_1] |
} |
set obj [get_runs impl_1] |
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91,7 → 91,7
current_run -implementation [get_runs impl_1] |
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# regenerate block diagrams |
source $origin_dir/../block_diagrams/zync_bd_16_2.tcl |
source $origin_dir/../block_diagrams/zync.tcl |
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close_project -quiet |
|