OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk
    from Rev 29 to Rev 28
    Reverse comparison

Rev 29 → Rev 28

/avalon_lib/docs/mnl_avalon_spec_1_3.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
avalon_lib/docs/mnl_avalon_spec_1_3.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: avalon_lib/src/amm_if.sv =================================================================== --- avalon_lib/src/amm_if.sv (revision 29) +++ avalon_lib/src/amm_if.sv (nonexistent) @@ -1,63 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -interface - amm_if - #( - A = 32, // address bus width - N = 8, // data bus width in bytes - B = 7 // burstcount width - ) - ( - input reset, - input clk - ); - - logic [(A-1):0] address; - logic read; - logic [(8*N)-1:0] readdata; - logic write; - logic [(8*N)-1:0] writedata; - logic [N-1:0] byteenable; - logic begintransfer; - logic waitrequest; - logic arbiterlock; - logic readdatavalid; - logic [B-1:0] burstcount; - logic beginbursttransfer; - logic readyfordata; - logic dataavailable; - logic resetrequest; - - -// -------------------------------------------------------------------- -// - -endinterface - - Index: FIFOs/src/fifo_witout_if/tiny_sync_fifo.sv =================================================================== --- FIFOs/src/fifo_witout_if/tiny_sync_fifo.sv (revision 29) +++ FIFOs/src/fifo_witout_if/tiny_sync_fifo.sv (nonexistent) @@ -1,136 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module - tiny_sync_fifo - #( - parameter W = 8 - ) - ( - output wr_full, - input [W-1:0] wr_data, - input wr_en, - - output rd_empty, - output [W-1:0] rd_data, - input rd_en, - - input clk, - input reset - ); - - // -------------------------------------------------------------------- - // - reg empty_r; - reg full_r; - wire writing = wr_en & (rd_en | ~full_r); - wire reading = rd_en & ~empty_r; - - - // -------------------------------------------------------------------- - // - reg rd_ptr_r; - reg next_rd_ptr_r; - - always_comb - if(reset) - next_rd_ptr_r = 0; - else if(reading) - next_rd_ptr_r = ~rd_ptr_r; - else - next_rd_ptr_r = rd_ptr_r; - - always_ff @(posedge clk) - rd_ptr_r <= next_rd_ptr_r; - - - // -------------------------------------------------------------------- - // - reg wr_ptr_r; - reg next_wr_ptr_r; - - always_comb - if (reset) - next_wr_ptr_r = 0; - else if(writing) - next_wr_ptr_r = ~wr_ptr_r; - else - next_wr_ptr_r = wr_ptr_r; - - always_ff @(posedge clk) - wr_ptr_r <= next_wr_ptr_r; - - - // -------------------------------------------------------------------- - // - always_ff @(posedge clk) - if (reset) - empty_r <= 1; - else if (reading & (next_wr_ptr_r == next_rd_ptr_r) & ~full_r) - empty_r <= 1; - else if (writing & ~reading) - empty_r <= 0; - else - empty_r <= empty_r; - - - // -------------------------------------------------------------------- - // - always_ff @(posedge clk) - if (reset) - full_r <= 0; - else if (writing & (next_wr_ptr_r == next_rd_ptr_r)) - full_r <= 1; - else if (reading & ~writing) - full_r <= 0; - - - // -------------------------------------------------------------------- - // - reg [W - 1:0] data_0_r; - reg [W - 1:0] data_1_r; - wire [W - 1:0] wr_data_mux = rd_ptr_r ? data_1_r : data_0_r; - assign rd_data = wr_data_mux; - - always_ff @(posedge clk) - if (writing) - if(wr_ptr_r) - data_1_r <= wr_data; - else - data_0_r <= wr_data; - - - // -------------------------------------------------------------------- - // - assign rd_empty = empty_r; - assign wr_full = full_r; - - -endmodule - - Index: FIFOs/src/Beyond_Circuits/sync_fifo.v =================================================================== --- FIFOs/src/Beyond_Circuits/sync_fifo.v (revision 29) +++ FIFOs/src/Beyond_Circuits/sync_fifo.v (revision 28) @@ -149,10 +149,12 @@ // the FIFO is empty the write data can flow through to // the read side and be available the next clock cycle. reg [width-1:0] mem [depth-1:0]; - always @(posedge clk) - if (writing) - mem[wr_ptr] <= wr_data; + begin + if (writing) + mem[wr_ptr] <= wr_data; + rd_ptr <= next_rd_ptr; + end assign rd_data = mem[rd_ptr];
/cli/cli/sys_cli.c
219,12 → 219,11
 
cli_init();
 
// PRINTF_MACRO("\r\n");
PRINTF_MACRO("\r\n");
 
for(;;)
{
// PRINTF_MACRO("%d > ", last_return_value);
PRINTF_MACRO("\r\n# > ");
PRINTF_MACRO("%d > ", last_return_value);
 
cli_argc = 0;
last_return_value = EXIT_SUCCESS;
250,7 → 249,7
 
if (cli_cmd == NULL)
{
PRINTF_MACRO("\r\n! > Command not found!!!");
PRINTF_MACRO("\r\n Command not found!\r\n");
last_return_value = EXIT_FAILURE;
break;
}
270,7 → 269,7
}
}
 
// PRINTF_MACRO("\r\n");
PRINTF_MACRO("\r\n");
 
last_return_value = cli_cmd->func(cli_argc, (const char **)cli_argv);
break;
/cli/cli/sys_cmd_table.h
26,9 → 26,11
//////////////////////////////////////////////////////////////////////
 
#include "sys_cmd.h"
#include "util_mem.h"
 
extern char func_mw( const unsigned char argc, const char *argv[] );
extern char func_md( const unsigned char argc, const char *argv[] );
 
 
/*-----------------------------------------------------------*/
// command table
 
36,7 → 38,6
/* put in alphabetical order by command name */
struct cli_cmd_tab_t cli_commands[] =
{
{ "#", func_comment, " # comment is ingored\r" },
{ "help", func_help, " help ~ print help message\r" },
{ "md", func_md, " md address [# of objects] ~ memory display\r" },
{ "md.b", func_md, " md.b address [# of objects] ~ memory display\r" },
/cli/cli/sys_cmd.h
33,13 → 33,12
#define MAX_CMD_LENGTH 20
#define MAX_CLI_ARGC 6
 
// #include <xil_printf.h>
#include <xil_printf.h>
 
// #define ANSI_ESCAPE_CODE
 
// #define PRINTF_MACRO xil_printf
#define PRINTF_MACRO xil_printf
// #define PRINTF_MACRO iprintf
#define PRINTF_MACRO printf
 
typedef char (*cli_cmd_func)( const unsigned char argc, const char * argv[] );
 
55,10 → 54,10
 
/*-----------------------------------------------------------*/
extern void sys_cli_task(void);
extern cli_cmd_tab_t *cli_find_command( cli_cmd_tab_t *cmd_to_check);
extern void cli_init(void);
extern char func_mw(const unsigned char argc, const char *argv[]);
extern char func_md(const unsigned char argc, const char *argv[]);
extern cli_cmd_tab_t *cli_find_command( cli_cmd_tab_t *cmd_to_check );
extern void cli_init( void );
extern char func_mw( const unsigned char argc, const char *argv[] );
extern char func_md( const unsigned char argc, const char *argv[] );
 
 
/*-----------------------------------------------------------*/
/axi4_lib/src/axi4_if.sv
29,60 → 29,146
interface
axi4_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
DATA_WIDTH = 64
)
(
input aresetn,
input aclk
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
wire arready;
wire arregion;
wire awready;
wire awregion;
wire bvalid;
wire rlast;
wire rvalid;
wire wready;
wire [1:0] bresp;
wire [1:0] rresp;
wire [5:0] bid;
wire [5:0] rid;
wire [DATA_WIDTH-1:0] rdata;
wire [7:0] rcount;
wire [7:0] wcount;
wire [2:0] racount;
wire [5:0] wacount;
wire arvalid;
wire awvalid;
wire bready;
wire rready;
wire wlast;
wire wvalid;
wire [1:0] arburst;
wire [1:0] arlock;
wire [2:0] arsize;
wire [1:0] awburst;
wire [1:0] awlock;
wire [2:0] awsize;
wire [2:0] arprot;
wire [2:0] awprot;
wire [31:0] araddr;
wire [31:0] awaddr;
wire [3:0] arcache;
wire [7:0] arlen;
wire [3:0] arqos;
wire [3:0] awcache;
wire [3:0] awlen;
wire [3:0] awqos;
wire [5:0] arid;
wire [5:0] awid;
wire [5:0] wid;
wire [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH/8-1:0] wstrb;
// --------------------------------------------------------------------
//
modport
master
(
output arid,
output araddr,
output arburst,
output arcache,
output arlen,
output arlock,
output arprot,
output arqos,
input arready,
output arregion,
output arsize,
output arvalid,
output awaddr,
output awburst,
output awcache,
output awlen,
output awlock,
output awprot,
output awqos,
input awready,
output awregion,
output awsize,
output awvalid,
output bready,
input bresp,
input bvalid,
input rdata,
input rlast,
output rready,
input rresp,
input rvalid,
output wdata,
output wlast,
input wready,
output wstrb,
output wvalid,
input aresetn,
input aclk
);
modport
slave
(
input arid,
input araddr,
input arburst,
input arcache,
input arlen,
input arlock,
input arprot,
input arqos,
output arready,
input arregion,
input arsize,
input arvalid,
input awaddr,
input awburst,
input awcache,
input awlen,
input awlock,
input awprot,
input awqos,
output awready,
input awregion,
input awsize,
input awvalid,
input bready,
output bresp,
output bvalid,
output rdata,
output rlast,
input rready,
output rresp,
output rvalid,
input wdata,
input wlast,
output wready,
input wstrb,
input wvalid,
input aresetn,
input aclk
);
endinterface: axi4_if
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.