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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk
    from Rev 35 to Rev 34
    Reverse comparison

Rev 35 → Rev 34

/PCIe/sim/src/riffa_agent_class_pkg.sv
40,8 → 40,7
riffa_transaction_class #(N) tr_h;
rp_tx_bfm_class #(N) tx_h;
rp_rx_bfm_class #(N) rx_h;
// mailbox #(riffa_transaction_class #(N)) tx_q, rx_q;
mailbox #(riffa_transaction_class #(N)) tx_q;
mailbox #(riffa_transaction_class #(N)) q;
 
 
// --------------------------------------------------------------------
48,37 → 47,17
//
task queue_tx(riffa_transaction_class #(N) tr_h);
tx_h.put(tr_h);
tx_q.put(tr_h);
q.put(tr_h);
endtask: queue_tx
 
 
// --------------------------------------------------------------------
//
task queue_tx_constant(int len, int off, bit last, logic [(8*N)-1:0] value);
tr_h = new(len, off, last);
tr_h.constant(len, off, last, value);
tx_h.put(tr_h);
tx_q.put(tr_h);
endtask: queue_tx_constant
 
 
// --------------------------------------------------------------------
//
task queue_tx_counting(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.counting(len, off, last);
tx_h.put(tr_h);
tx_q.put(tr_h);
endtask: queue_tx_counting
 
 
// --------------------------------------------------------------------
//
task queue_tx_random(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.random(len, off, last);
tx_h.put(tr_h);
tx_q.put(tr_h);
q.put(tr_h);
endtask: queue_tx_random
 
 
87,7 → 66,6
task queue_rx(int len, int off, bit last);
tr_h = new(len, off, last);
rx_h.put(tr_h);
// rx_q.put(tr_h);
endtask: queue_rx
 
 
110,8 → 88,7
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
tx_h = new(chnl_bus);
rx_h = new(chnl_bus);
this.tx_q = new;
// this.rx_q = new;
this.q = new;
endfunction: new
 
 
/PCIe/sim/src/riffa_bfm_class_pkg.sv
55,30 → 55,6
 
//--------------------------------------------------------------------
//
function void constant(int len, int off, bit last, logic [(8*N)-1:0] value);
this.data = new[get_data_size(len)];
this.len = len;
this.off = off;
this.last = last;
foreach(this.data[i])
this.data[i] = value;
endfunction: constant
 
 
//--------------------------------------------------------------------
//
function void counting(int len, int off, bit last);
this.data = new[get_data_size(len)];
this.len = len;
this.off = off;
this.last = last;
foreach(this.data[i])
this.data[i] = i;
endfunction: counting
 
 
//--------------------------------------------------------------------
//
function void random(int len, int off, bit last);
this.data = new[get_data_size(len)];
assert(this.randomize() with
93,33 → 69,6
endfunction: random
 
 
//--------------------------------------------------------------------
//
function void compare(riffa_transaction_class #(N) to, int max_mismatches = 8);
int error_count = 0;
$display("!!! %16.t | %m", $time);
if(this.len != to.len)
$display("!!! %16.t | ERROR! len mismatch", $time);
 
if(this.off != to.off)
$display("!!! %16.t | ERROR! off mismatch", $time);
 
if(this.last != to.last)
$display("!!! %16.t | ERROR! last mismatch", $time);
 
foreach(this.data[i])
begin
if(error_count > max_mismatches)
break;
if(this.data[i] != to.data[i])
begin
$display("!!! %16.t | ERROR! | 0x%x | this != to | 0x%x != 0x%x", $time, i, this.data[i], to.data[i]);
error_count++;
end
end
endfunction: compare
 
 
// // --------------------------------------------------------------------
// //
// function void copy(ref riffa_transaction_class #(N) from);
250,22 → 199,18
 
chnl_bus.cb_rp_rx.tx_ack <= 1;
chnl_bus.cb_rp_rx.tx_data_ren <= 1;
 
fork
@(chnl_bus.cb_rp_tx)
chnl_bus.cb_rp_rx.tx_ack <= 0;
join_none
 
// foreach(tr_h.data[i])
// @(chnl_bus.cb_rp_tx)
// if(~chnl_bus.cb_rp_rx.tx)
// break;
// else if(chnl_bus.cb_rp_rx.tx_data_valid)
// tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
 
foreach(tr_h.data[i])
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_rx.tx_data_valid)
tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
@(chnl_bus.cb_rp_tx)
if(~chnl_bus.cb_rp_rx.tx)
break;
else if(chnl_bus.cb_rp_rx.tx_data_valid)
tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
 
rx_q.put(tr_h);
set_default();
/PCIe/src/RIFFA/riffa_chnl_rx.sv
31,14 → 31,13
N // data bus width in bytes
)
(
riffa_chnl_if chnl_bus,
input rx_ready,
riffa_chnl_if chnl_in,
output rx_done,
output reg [30:0] rx_index,
output reg rx_last,
output reg [31:0] rx_len,
output reg [30:0] rx_off,
// output rx_data_ren, // shouldn't be here??
output rx_data_ren,
output rd_empty,
output [(8*N)-1:0] rd_data,
input rd_en,
52,9 → 51,9
riffa_chnl_rx_fsm
riffa_chnl_rx_fsm_i
(
.rx(chnl_bus.rx),
.rx_data_valid(chnl_bus.rx_data_valid),
.rx_ack(chnl_bus.rx_ack),
.rx(chnl_in.rx),
.rx_data_valid(chnl_in.rx_data_valid),
.rx_ack(chnl_in.rx_ack),
.*
);
 
62,19 → 61,19
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(chnl_bus.rx & chnl_bus.rx_ack)
if(chnl_in.rx & chnl_in.rx_ack)
begin
rx_last <= chnl_bus.rx_last;
rx_len <= chnl_bus.rx_len;
rx_off <= chnl_bus.rx_off;
rx_last <= chnl_in.rx_last;
rx_len <= chnl_in.rx_len;
rx_off <= chnl_in.rx_off;
end
 
 
// --------------------------------------------------------------------
//
wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;
wire [(8*N)-1:0] wr_data = chnl_in.rx_data;
wire wr_full;
wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;
wire wr_en = chnl_in.rx_data_ren & chnl_in.rx_data_valid;
 
tiny_sync_fifo #(.W((8*N)))
tiny_sync_fifo_i(.*);
91,8 → 90,7
 
// --------------------------------------------------------------------
//
// assign rx_data_ren = ~wr_full; // shouldn't be here??
assign chnl_bus.rx_data_ren = ~wr_full;
assign rx_data_ren = ~wr_full;
 
 
// --------------------------------------------------------------------
/PCIe/src/RIFFA/riffa_register_file.sv
28,8 → 28,9
module
riffa_register_file
#(
A, // address bus width
N, // data bus width in bytes
B // number of register banks
MW = 3 // mux select width
)
(
riffa_chnl_if chnl_in,
41,10 → 42,7
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_data_bus_mod: assert(N % 4 == 0) else $fatal;
a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
52,44 → 50,42
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
localparam RC = RW * B; // number of available registers
localparam MI = 2 ** MW; // mux inputs
localparam LB = $clog2(RW);
localparam UB = LB + MW;
 
 
// --------------------------------------------------------------------
//
wire rx_ready = ~reset;
wire rx_done;
wire [30:0] rx_index;
wire [31:0] rx_index;
wire rx_last;
wire [31:0] rx_len;
wire [30:0] rx_off; // offset ignored, always start from offset 0
// wire rx_data_ren;
wire [30:0] rx_off;
wire rx_data_ren;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
riffa_chn_rx_i(.*);
 
 
// --------------------------------------------------------------------
//
wire register_select [RC-1:0];
genvar j, k;
wire register_select [MI-1:0];
genvar j;
 
generate
for(j = 0; j < B; j = j + 1)
begin: register_j_gen
for(k = 0; k < RW; k = k + 1)
begin: register_k_gen
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
for(j = 0; j < MI; j = j + 1)
begin: decoder_gen
assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;
 
always_ff @(posedge clk)
if(reset)
r_if.register_out[(j*RW) + k] <= 0;
else if(rd_en & register_select[(j*RW) + k])
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
end
always_ff @(posedge clk)
if(reset)
r_if.register_out[j] <= 0;
else if(rd_en & register_select[j])
r_if.register_out[j] <= rd_data;
end
endgenerate
 
96,7 → 92,7
 
// --------------------------------------------------------------------
//
// assign chnl_in.rx_data_ren = rx_data_ren;
assign chnl_in.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
 
 
104,10 → 100,9
//
wire tx_ready = 1;
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
wire [31:0] tx_len = RW*MI;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire [31:0] tx_index;
wire tx_done = (tx_index >= chnl_in.tx_len - RW);
 
riffa_chn_tx #(.N(N))
116,27 → 111,12
 
// --------------------------------------------------------------------
//
wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
 
generate
for(j = 0; j < B; j = j + 1)
begin: data_in_j_gen
for(k = 0; k < RW; k = k + 1)
begin: data_in_k_gen
assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
recursive_mux #(.A($clog2(B)), .W(N*8))
recursive_mux #(.A(MW), .W(N*8))
recursive_mux_i
(
.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
.data_out(chnl_in.tx_data),
.*
.select(tx_index[UB:LB]),
.data_in(r_if.register_in),
.data_out(chnl_in.tx_data)
);
 
 
147,9 → 127,9
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = 1;
assign chnl_in.tx_len = RC;
assign chnl_in.tx_len = RW*MI;
assign chnl_in.tx_off = 0;
assign chnl_in.tx_data_valid = acked;
assign chnl_in.tx_data_valid = 1;
 
 
// --------------------------------------------------------------------
/PCIe/src/RIFFA/riffa_chnl_rx_fsm.sv
30,7 → 30,6
(
input rx,
input rx_data_valid,
input rx_ready,
output rx_ack,
output rx_done,
 
68,11 → 67,7
else
next_state <= IDLE;
 
// ACK: next_state <= RX;
ACK: if(rx_ready)
next_state <= RX;
else
next_state <= ACK;
ACK: next_state <= RX;
 
RX: if(rx)
next_state <= RX;
/axi4_stream_lib/src/axis_downsizer.sv
165,13 → 165,11
 
// --------------------------------------------------------------------
//
genvar j;
generate
for(j = 0; j < M_D; j++)
begin : tdata_gen
begin: tdata_gen
for(genvar j = 0; j < M_D; j++)
assign mux_in_tdata[j] = tdata_r[j*M_NW +: M_NW];
end
end
endgenerate
 
 
178,23 → 176,19
// --------------------------------------------------------------------
//
generate
begin : tuser_gen
begin: tuser_gen
if(BYTES_PER_TUSER != 0)
begin : tuser_tuser_0_gen
begin
wire [M_UW-1:0] mux_in_tuser [M_D-1:0];
 
recursive_mux #(.A(M_A), .W(M_UW))
tuser_mux_i(.data_in(mux_in_tuser), .data_out(axis_downsizer_bus.tuser), .*);
 
for(j = 0; j < M_D; j++)
begin : tuser_j_gen
for(genvar j = 0; j < M_D; j++)
assign mux_in_tuser[j] = tuser_r[j*M_UW +: M_UW] & {M_UW{axis_downsizer_bus.tvalid}};
end
end
else
begin : tuser_tuser_gen
assign axis_downsizer_bus.tuser = tuser_r & {U{axis_downsizer_bus.tvalid}};
end
end
endgenerate
 
/axi4_stream_lib/src/axis_if.sv
29,7 → 29,7
interface
axis_if
#(
N, // data bus width in bytes
N = 0, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
U = 1 // TUSER width
/axi4_stream_lib/src/axis_upsizer.sv
53,7 → 53,7
a_tstrb_unsuported: assert(USE_TSTRB == 0) else $fatal;
a_tkeep_unsuported: assert(USE_TKEEP == 0) else $fatal;
a_bytes_per_tuser: assert((BYTES_PER_TUSER == 0) | (N % BYTES_PER_TUSER == 0)) else $fatal;
// a_tuser: assert((BYTES_PER_TUSER == 0) | (U % S == 0)) else $fatal;
a_tuser: assert((BYTES_PER_TUSER == 0) | (U % S == 0)) else $fatal;
end
 
// synthesis translate_on
/sim/libs/qaz_lib_verilog/basal.f
4,7 → 4,9
${LIB_BASE_DIR}/basal/src/8b10b/encode_8b10b.v
 
${LIB_BASE_DIR}/basal/src/FIFOs/bc_sync_fifo.v
${LIB_BASE_DIR}/basal/src/FIFOs/fifo_write_if.sv
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.v
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_async_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_sync_fifo.sv
 
32,6 → 34,9
${LIB_BASE_DIR}/basal/src/RAM/read_mixed_width_ram.sv
${LIB_BASE_DIR}/basal/src/RAM/write_mixed_width_ram.sv
 
${LIB_BASE_DIR}/basal/src/synchronize/debounce.v
${LIB_BASE_DIR}/basal/src/synchronize/debounce_high.v
${LIB_BASE_DIR}/basal/src/synchronize/debounce_low.v
${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v
 
/sim/libs/sim_verilog/BFM.f
1,5 → 1,7
#
 
${LIB_BASE_DIR}/BFM/src/axis_video_frame/axis_video_frame_bfm_pkg.sv
${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_agent_class_pkg.sv
# ${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_agent.sv
# ${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_rx.sv
# ${LIB_BASE_DIR}/BFM/src/axis_video_frame/avf_tx.sv
7,9 → 9,11
# ${LIB_BASE_DIR}/BFM/src/clock/clock_checker.v
# ${LIB_BASE_DIR}/BFM/src/clock/clock_mult.v
# ${LIB_BASE_DIR}/BFM/src/clock/recover_clock.v
${LIB_BASE_DIR}/BFM/src/clock/tb_clk.v
# ${LIB_BASE_DIR}/BFM/src/clock/tb_programmable_clk.v
 
# ${LIB_BASE_DIR}/BFM/src/tb/rand_delays_c.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_base.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_bfm_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv
/sim/libs/tb_packages_verilog/BFM.f
1,8 → 1,8
#
 
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/q_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/bfm_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/logger_pkg.sv
${LIB_BASE_DIR}/tb_class/src/tb_clk_pkg.sv
${LIB_BASE_DIR}/tb_class/src/q_pkg.sv
${LIB_BASE_DIR}/tb_class/src/bfm_pkg.sv
${LIB_BASE_DIR}/tb_class/src/logger_pkg.sv
 
${LIB_BASE_DIR}/BFM/src/video_frame/video_frame_pkg.sv
${LIB_BASE_DIR}/video_frame_class/src/video_frame_pkg.sv
/sim/libs/avalon_lib_verilog/avalon_lib_base.f
2,5 → 2,4
 
 
${LIB_BASE_DIR}/avalon_lib/src/ast_if.sv
${LIB_BASE_DIR}/avalon_lib/src/fifo_to_ast.sv
 
/avalon_lib/docs/mnl_avalon_spec_1_3.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
avalon_lib/docs/mnl_avalon_spec_1_3.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: avalon_lib/src/fifo_to_ast.sv =================================================================== --- avalon_lib/src/fifo_to_ast.sv (revision 35) +++ avalon_lib/src/fifo_to_ast.sv (nonexistent) @@ -1,109 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module - fifo_to_ast - #( - READYLATENCY, - EW = 1, // error signal width in bits. - CW = 1, // channel width in bits. - SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces. - NSB, // Numbers of symbols per beat - NSB_L = (NSB == 1) ? 1 : $clog2(NSB), // empty width - D = 2, - UB = $clog2(D) - ) - ( - output wr_full, - input wr_en, - - ast_if ast_in, - ast_if ast_out, - input clk, - input reset - ); - - // -------------------------------------------------------------------- - // - reg [READYLATENCY:0] ready_r; - wire ready_cycle = ready_r[READYLATENCY]; - - always_ff @(posedge clk) - if(reset) - ready_r <= 0; - else - ready_r <= {ready_r[READYLATENCY-1:0], ast_out.ready}; - - - // -------------------------------------------------------------------- - // - localparam FW = (SW*NSB) + 1 + 1 + NSB_L + CW + EW; - - - // -------------------------------------------------------------------- - // - wire [FW-1:0] wr_data = - { ast_in.channel - , ast_in.error - , ast_in.data - , ast_in.empty - , ast_in.endofpacket - , ast_in.startofpacket - }; - - wire [FW-1:0] rd_data; - assign { ast_out.channel - , ast_out.error - , ast_out.data - , ast_out.empty - , ast_out.endofpacket - , ast_out.startofpacket - } = rd_data; - - - // -------------------------------------------------------------------- - // - wire rd_empty; - wire rd_en = ready_cycle & ~rd_empty; - wire [UB:0] count; - - - sync_fifo #(.W(FW), .D(D)) - sync_fifo_i(.*); - - - // -------------------------------------------------------------------- - // - assign ast_out.valid = rd_en; - - -// -------------------------------------------------------------------- -// -endmodule - - Index: zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== --- zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (nonexistent) +++ zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (revision 34)
zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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