Subversion Repositories qaz_libs

/trunk/zed_board/src/top.v File deleted

/trunk/zed_board/src/reg_file_v1_0_S00_AXI.v File deleted

/trunk/zed_board/src/zedboard_master_XDC_RevC_D_v2.xdc File deleted

/trunk/zed_board/syn/precompiled_elfs/u-boot.elf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/zed_board/syn/precompiled_elfs/u-boot.elf

trunk/zed_board/syn/precompiled_elfs/u-boot.elf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf =================================================================== --- trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (revision 15) +++ trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf (nonexistent)

trunk/zed_board/syn/precompiled_elfs/zynq_fsbl_0.elf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/zed_board/syn/axi_lite_to_wbl.tcl =================================================================== --- trunk/zed_board/syn/axi_lite_to_wbl.tcl (revision 15) +++ trunk/zed_board/syn/axi_lite_to_wbl.tcl (nonexistent) @@ -1,101 +0,0 @@ -# -#***************************************************************************************** -# -#***************************************************************************************** - -close_project -quiet - -# set variables for project -set PROJECT_NAME axi_lite_to_wb - -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir [file dirname [info script] ] - -# Create project -create_project -force $PROJECT_NAME $origin_dir/$PROJECT_NAME - -# Set project properties -set obj [get_projects $PROJECT_NAME] -set_property "board_part" "em.avnet.com:zed:part0:1.2" $obj -set_property "default_lib" "xil_defaultlib" $obj - -# Create 'sources_1' fileset (if not found) -if {[string equal [get_filesets -quiet sources_1] ""]} { - create_fileset -srcset sources_1 -} - -add_files -fileset sources_1 -norecurse $origin_dir/../src/top.v -add_files -fileset sources_1 -norecurse $origin_dir/../src/reg_file_v1_0_S00_AXI.v - -update_compile_order -fileset sources_1 - -# Set 'sources_1' fileset properties -set obj [get_filesets sources_1] -set_property "top" "top" $obj - -# Create 'constrs_1' fileset (if not found) -if {[string equal [get_filesets -quiet constrs_1] ""]} { - create_fileset -constrset constrs_1 -} - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc"]" -set file_added [add_files -norecurse -fileset $obj $file] -set file "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] -set_property "file_type" "XDC" $file_obj - -# Set 'constrs_1' fileset properties -set obj [get_filesets constrs_1] -set_property "target_constrs_file" "[file normalize "$origin_dir/../src/zedboard_master_XDC_RevC_D_v2.xdc"]" $obj - -# Create 'sim_1' fileset (if not found) -if {[string equal [get_filesets -quiet sim_1] ""]} { - create_fileset -simset sim_1 -} - -# Set 'sim_1' fileset object -set obj [get_filesets sim_1] -# Empty (no sources present) - -# Set 'sim_1' fileset properties -set obj [get_filesets sim_1] -set_property "top" "top" $obj - -# Create 'synth_1' run (if not found) -if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 -} else { - set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] - set_property flow "Vivado Synthesis 2014" [get_runs synth_1] -} -set obj [get_runs synth_1] - -# set the current synth run -current_run -synthesis [get_runs synth_1] - -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 -} else { - set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] - set_property flow "Vivado Implementation 2014" [get_runs impl_1] -} -set obj [get_runs impl_1] - -# set the current impl run -current_run -implementation [get_runs impl_1] - -# regenerate block diagrams -source $origin_dir/../block_diagrams/zync.tcl - -close_project -quiet - -puts "INFO: Project created:$PROJECT_NAME" - - - Index: trunk/zed_board/block_diagrams/zync.tcl =================================================================== --- trunk/zed_board/block_diagrams/zync.tcl (revision 15) +++ trunk/zed_board/block_diagrams/zync.tcl (nonexistent) @@ -1,198 +0,0 @@ - -################################################################ -# This is a generated script based on design: zync -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2014.4 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source zync_script.tcl - -# If you do not already have a project created, -# you can create a project using the following command: -# create_project project_1 myproj -part xc7z020clg484-1 -# set_property BOARD_PART em.avnet.com:zed:part0:1.2 [current_project] - - -# CHANGE DESIGN NAME HERE -set design_name zync - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# CHECKING IF PROJECT EXISTS -if { [get_projects -quiet] eq "" } { - puts "ERROR: Please open or create a project!" - return 1 -} - - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "ERROR: Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - puts "INFO: Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - puts "INFO: Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - puts "INFO: Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -puts "INFO: Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - puts $errMsg - return $nRet -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - puts "ERROR: Unable to find parent cell <$parentCell>!" - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] - set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] - set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] - set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.NUM_READ_OUTSTANDING {8} CONFIG.NUM_WRITE_OUTSTANDING {8} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI - - # Create ports - set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] - set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M00_AXI} ] $FCLK_CLK0 - set peripheral_aresetn [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_aresetn ] - - # Create instance: axi_interconnect_0, and set properties - set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] - set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_0 - - # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - - # Create instance: processing_system7_0, and set properties - set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] - set_property -dict [ list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} CONFIG.preset {ZedBoard*} ] $processing_system7_0 - - # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] - connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] - connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] - connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] - - # Create port connections - connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports peripheral_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] - - # Create address segments - create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg - - - # Restore current instance - current_bd_instance $oldCurInst - - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - -