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https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
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- This comparison shows the changes necessary to convert path
/qaz_libs
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/trunk/axi4_stream_lib/src/axis_alias.sv
28,8 → 28,10
module |
axis_alias |
#( |
CONNECT_TREADY = 1, |
CONNECT_TVALID = 1 |
CONNECT_TREADY = 1, |
CONNECT_TVALID = 1, |
CONNECT_TLAST = 1, |
CONNECT_TUSER = 1 |
) |
( |
axis_if axis_in, |
58,13 → 60,31
|
// -------------------------------------------------------------------- |
// |
generate |
if(CONNECT_TLAST == 1) |
begin: tlast_gen |
assign axis_out.tlast = axis_in.tlast; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
generate |
if(CONNECT_TUSER == 1) |
begin: tuser_gen |
assign axis_out.tuser = axis_in.tuser; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_out.tdata = axis_in.tdata; |
assign axis_out.tstrb = axis_in.tstrb; |
assign axis_out.tkeep = axis_in.tkeep; |
assign axis_out.tlast = axis_in.tlast; |
assign axis_out.tid = axis_in.tid; |
assign axis_out.tdest = axis_in.tdest; |
assign axis_out.tuser = axis_in.tuser; |
|
|
// -------------------------------------------------------------------- |
/trunk/axi4_stream_lib/src/axis_catenate.sv
47,7 → 47,7
wire select; |
wire axis_eop; |
|
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules? |
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are these needed for recursive modules? |
defparam axis_eop_mux_i.MA = 1; |
axis_eop_mux |
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1)) |
141,7 → 141,7
|
// -------------------------------------------------------------------- |
// |
defparam axis_mux_i.N = N; // why are needed these for recursive modules? |
defparam axis_mux_i.N = N; // why are these needed for recursive modules? |
defparam axis_mux_i.I = I; |
defparam axis_mux_i.D = D; |
defparam axis_mux_i.U = U; |
/trunk/axi4_stream_lib/src/axis_interleave.sv
0,0 → 1,91
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_interleave |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1 // TUSER width |
) |
( |
axis_if axis_in [1:0], |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// state machine binary definitions |
enum reg [1:0] |
{ |
EVEN = 2'b01, |
ODD = 2'b10 |
} state, next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine flop |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= EVEN; |
else |
state <= next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine |
always_comb |
case(state) |
EVEN: if(axis_in[0].tvalid) |
next_state <= ODD; |
else |
next_state <= EVEN; |
|
ODD: if(axis_in[1].tvalid) |
next_state <= EVEN; |
else |
next_state <= ODD; |
|
default: next_state <= EVEN; |
endcase |
|
|
// -------------------------------------------------------------------- |
// |
wire select = (state == EVEN) ? 0 : 1; |
|
axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/trunk/axi4_stream_lib/src/axis_map_fifo.sv
35,15 → 35,13
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0, // set to 1 to enable, 0 to disable |
// USE_XID = 0, // set to 1 to enable, 0 to disable |
W = 0 |
W |
) |
( |
axis_if axis_in, |
axis_if axis_out, |
output [W-1:0] wr_data, |
input [W-1:0] rd_data, |
input aclk, |
input aresetn |
input [W-1:0] rd_data |
); |
|
// -------------------------------------------------------------------- |
/trunk/axi4_stream_lib/src/axis_mux.sv
45,7 → 45,7
|
// -------------------------------------------------------------------- |
// |
defparam axis_mux_out.N = N; // why are needed these for recursive modules? |
defparam axis_mux_out.N = N; // why are these needed for recursive modules? |
defparam axis_mux_out.I = I; |
defparam axis_mux_out.D = D; |
defparam axis_mux_out.U = U; |
67,7 → 67,7
|
// -------------------------------------------------------------------- |
// |
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules? |
defparam axis_register_slice_i.N = N; // why are these needed for recursive modules? |
defparam axis_register_slice_i.I = I; |
defparam axis_register_slice_i.D = D; |
defparam axis_register_slice_i.U = U; |
/trunk/axi4_stream_lib/src/axis_register_slice.sv
57,7 → 57,7
wire [W-1:0] rd_data; |
wire rd_en; |
|
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules? |
defparam tiny_sync_fifo_i.W=W; // why are these needed for recursive modules? |
tiny_sync_fifo |
// tiny_sync_fifo #(W) |
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*); |
65,78 → 65,24
|
// -------------------------------------------------------------------- |
// |
generate |
begin: assign_gen |
if(USE_TSTRB & USE_TKEEP) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb, |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb, |
axis_out.tkeep |
} = rd_data; |
end |
else if(USE_TSTRB) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb |
} = rd_data; |
end |
else if(USE_TKEEP) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tkeep |
} = rd_data; |
end |
else |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser |
} = rd_data; |
end |
end |
endgenerate |
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules? |
defparam axis_map_fifo_i.I=I; |
defparam axis_map_fifo_i.D=D; |
defparam axis_map_fifo_i.U=U; |
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB; |
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP; |
defparam axis_map_fifo_i.W=W; |
axis_map_fifo |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(USE_TSTRB), |
// .USE_TKEEP(USE_TKEEP), |
// .W(W) |
// ) |
axis_map_fifo_i(.*); |
|
|
// -------------------------------------------------------------------- |
/trunk/axi4_stream_lib/src/axis_switch.sv
82,7 → 82,7
|
// -------------------------------------------------------------------- |
// |
defparam axis_register_slice_lo.N = N; // why are needed these for recursive modules? |
defparam axis_register_slice_lo.N = N; // why are these needed for recursive modules? |
defparam axis_register_slice_lo.I = I; |
defparam axis_register_slice_lo.D = D; |
defparam axis_register_slice_lo.U = U; |
/trunk/axi4_stream_lib/src/axis_synchronizer.sv
1,6 → 1,6
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// Copyright (C) 2016 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
28,33 → 28,23
module |
axis_synchronizer |
#( |
N = 8, // data bus width in bytes |
I = 0, // TID width |
D = 0, // TDEST width |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0 // set to 1 to enable, 0 to disable |
USE_TKEEP = 0, // set to 1 to enable, 0 to disable |
FD |
) |
( |
axis_if axis_in, |
axis_if axis_out, |
input wr_clk, |
input wr_reset, |
input aclk, |
input aresetn |
input aclk_in, |
input aresetn_in, |
input aclk_out, |
input aresetn_out |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_tid_unsuported: assert(I == 0) else $fatal; |
a_tdest_unsuported: assert(D == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1; |
68,94 → 58,50
|
wire rd_empty; |
wire [W-1:0] rd_data; |
wire rd_en; |
|
tiny_async_fifo #(.W(W)) |
tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*); |
wire rd_en; |
|
defparam async_fifo_i.W=W; // why are these needed for recursive modules? |
defparam async_fifo_i.D=FD; |
async_fifo |
// async_fifo #(.W(W), .D(FD)) |
async_fifo_i |
( |
.wr_clk(aclk_in), |
.wr_reset(~aresetn_in), |
.rd_clk(aclk_out), |
.rd_reset(~aresetn_out), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
generate |
begin: assign_gen |
if(USE_TSTRB & USE_TKEEP) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb, |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb, |
axis_out.tkeep |
} = rd_data; |
end |
else if(USE_TSTRB) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb |
} = rd_data; |
end |
else if(USE_TKEEP) |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tkeep |
} = rd_data; |
end |
else |
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser |
} = rd_data; |
end |
end |
endgenerate |
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules? |
defparam axis_map_fifo_i.I=I; |
defparam axis_map_fifo_i.D=D; |
defparam axis_map_fifo_i.U=U; |
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB; |
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP; |
defparam axis_map_fifo_i.W=W; |
axis_map_fifo |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(USE_TSTRB), |
// .USE_TKEEP(USE_TKEEP), |
// .W(W) |
// ) |
axis_map_fifo_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_in.tready = ~wr_full; |
assign wr_en = axis_in.tvalid & axis_in.tready; |
assign wr_en = axis_in.tvalid & ~wr_full; |
assign axis_out.tvalid = ~rd_empty; |
assign rd_en = axis_out.tvalid & axis_out.tready; |
assign rd_en = axis_out.tready & ~rd_empty; |
|
|
// -------------------------------------------------------------------- |
/trunk/basal/src/FIFOs/async_fifo.sv
0,0 → 1,319
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2016 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_sync_r2w |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg [ADDRSIZE:0] wq2_rptr, |
input [ADDRSIZE:0] rptr, |
input wclk, |
input wrst_n |
); |
|
reg [ADDRSIZE:0] wq1_rptr; |
|
always @(posedge wclk or negedge wrst_n) |
if (!wrst_n) |
{wq2_rptr,wq1_rptr} <= 0; |
else |
{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; |
|
endmodule |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_sync_w2r |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg [ADDRSIZE:0] rq2_wptr, |
input [ADDRSIZE:0] wptr, |
input rclk, |
input rrst_n |
); |
|
reg [ADDRSIZE:0] rq1_wptr; |
|
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
{rq2_wptr,rq1_wptr} <= 0; |
else |
{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; |
|
endmodule |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_fifomem |
#( |
parameter DATASIZE = 8, // Memory data word width |
parameter ADDRSIZE = 4 // Number of mem address bits |
) |
( |
output [DATASIZE-1:0] rdata, |
input [DATASIZE-1:0] wdata, |
input [ADDRSIZE-1:0] waddr, |
input [ADDRSIZE-1:0] raddr, |
input wclken, |
input wfull, |
input wclk |
); |
|
// RTL Verilog memory model |
localparam DEPTH = 1<<ADDRSIZE; |
reg [DATASIZE-1:0] mem [0:DEPTH-1]; |
assign rdata = mem[raddr]; |
|
always @(posedge wclk) |
if(wclken && !wfull) |
mem[waddr] <= wdata; |
|
endmodule |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_rptr_empty |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg rempty, |
output [ADDRSIZE-1:0] raddr, |
output reg [ADDRSIZE :0] rptr, |
input [ADDRSIZE :0] rq2_wptr, |
input rinc, |
input rclk, |
input rrst_n |
); |
|
reg [ADDRSIZE:0] rbin; |
wire [ADDRSIZE:0] rgraynext, rbinnext; |
|
//------------------- |
// GRAYSTYLE2 pointer |
//------------------- |
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
{rbin, rptr} <= 0; |
else |
{rbin, rptr} <= {rbinnext, rgraynext}; |
|
// Memory read-address pointer (okay to use binary to address memory) |
assign raddr = rbin[ADDRSIZE-1:0]; |
assign rbinnext = rbin + (rinc & ~rempty); |
assign rgraynext = (rbinnext>>1) ^ rbinnext; |
|
//--------------------------------------------------------------- |
// FIFO empty when the next rptr == synchronized wptr or on reset |
//--------------------------------------------------------------- |
assign rempty_val = (rgraynext == rq2_wptr); |
|
always @(posedge rclk or negedge rrst_n) |
if(!rrst_n) |
rempty <= 1'b1; |
else |
rempty <= rempty_val; |
|
endmodule |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_wptr_full |
#( |
parameter ADDRSIZE = 4 |
) |
( |
output reg wfull, |
output [ADDRSIZE-1:0] waddr, |
output reg [ADDRSIZE :0] wptr, |
input [ADDRSIZE :0] wq2_rptr, |
input winc, |
input wclk, |
input wrst_n |
); |
|
reg [ADDRSIZE:0] wbin; |
wire [ADDRSIZE:0] wgraynext, wbinnext; |
|
// GRAYSTYLE2 pointer |
always @(posedge wclk or negedge wrst_n) |
if(!wrst_n) |
{wbin, wptr} <= 0; |
else |
{wbin, wptr} <= {wbinnext, wgraynext}; |
|
// Memory write-address pointer (okay to use binary to address memory) |
assign waddr = wbin[ADDRSIZE-1:0]; |
assign wbinnext = wbin + (winc & ~wfull); |
assign wgraynext = (wbinnext>>1) ^ wbinnext; |
|
//------------------------------------------------------------------ |
// Simplified version of the three necessary full-tests: |
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && |
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && |
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); |
//------------------------------------------------------------------ |
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]}); |
|
always @(posedge wclk or negedge wrst_n) |
if(!wrst_n) |
wfull <= 1'b0; |
else |
wfull <= wfull_val; |
|
endmodule |
|
|
// -------------------------------------------------------------------- |
// |
module |
cummings_fifo1 |
#( |
parameter DSIZE = 8, |
parameter ASIZE = 4 |
) |
( |
output [DSIZE-1:0] rdata, |
output wfull, |
output rempty, |
input [DSIZE-1:0] wdata, |
input winc, |
input wclk, |
input wrst_n, |
input rinc, |
input rclk, |
input rrst_n |
); |
|
wire [ASIZE-1:0] waddr, raddr; |
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; |
|
cummings_sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr), |
.wclk(wclk), .wrst_n(wrst_n)); |
|
cummings_sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr), |
.rclk(rclk), .rrst_n(rrst_n)); |
|
cummings_fifomem #(DSIZE, ASIZE) fifomem |
(.rdata(rdata), .wdata(wdata), |
.waddr(waddr), .raddr(raddr), |
.wclken(winc), .wfull(wfull), |
.wclk(wclk)); |
|
cummings_rptr_empty #(ASIZE) rptr_empty |
(.rempty(rempty), |
.raddr(raddr), |
.rptr(rptr), .rq2_wptr(rq2_wptr), |
.rinc(rinc), .rclk(rclk), |
.rrst_n(rrst_n)); |
|
cummings_wptr_full #(ASIZE) wptr_full |
(.wfull(wfull), .waddr(waddr), |
.wptr(wptr), .wq2_rptr(wq2_rptr), |
.winc(winc), .wclk(wclk), |
.wrst_n(wrst_n)); |
|
endmodule |
// -------------------------------------------------------------------- |
// |
|
|
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
|
|
module |
async_fifo |
#( |
W, |
D |
) |
( |
output wr_full, |
input [W-1:0] wr_data, |
input wr_en, |
input wr_clk, |
input wr_reset, |
|
output rd_empty, |
output [W-1:0] rd_data, |
input rd_en, |
input rd_clk, |
input rd_reset |
); |
|
// -------------------------------------------------------------------- |
// |
cummings_fifo1 #(.DSIZE(W), .ASIZE($clog2(D))) |
cummings_fifo1_i |
( |
.rdata(rd_data), |
.wfull(wr_full), |
.rempty(rd_empty), |
.wdata(wr_data), |
.winc(wr_en), |
.wclk(wr_clk), |
.wrst_n(~wr_reset), |
.rinc(rd_en), |
.rclk(rd_clk), |
.rrst_n(~rd_reset) |
); |
|
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
always_ff @(posedge wr_clk) |
if(wr_en & wr_full) |
$stop; |
always_ff @(posedge rd_clk) |
if(rd_en & rd_empty) |
$stop; |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
|
/trunk/basal/src/FIFOs/sync_fifo.sv
73,8 → 73,20
end |
endgenerate |
|
|
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
always_ff @(posedge clk) |
if(wr_en & wr_full) |
$stop; |
always_ff @(posedge clk) |
if(rd_en & rd_empty) |
$stop; |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
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/trunk/basal/src/misc/one_hot_encoder.sv
46,11 → 46,11
// |
generate |
if(A == 1) |
begin: mux_gen |
begin: one_hot_encoder_gen |
assign encoded[1:0] = select[0] ? 2'b10 :2'b01; |
end |
else |
begin: recurse_mux_gen |
begin: recurse_one_hot_encoder_gen |
wire [W-1:0] encoder_out; |
|
one_hot_encoder #(.A(A - 1)) |