URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
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- ↔ Reverse comparison
Rev 35 → Rev 36
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv
73,7 → 73,7
#200ns; |
|
// -------------------------------------------------------------------- |
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.q.num()); |
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.tx_q.num()); |
|
// -------------------------------------------------------------------- |
// insert test above |
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
58,7 → 58,8
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); |
|
axis_test_patern #(.N(N), .W(W), .WPB(WPB)) |
// axis_test_patern #(.N(N), .W(W), .WPB(WPB)) |
axis_test_patern #(.W(W), .WPB(WPB)) |
axis_test_patern_i(.*); |
|
|
/qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
qaz_libs/trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip
Property changes :
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+application/octet-stream
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Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (revision 36)
@@ -0,0 +1,35 @@
+# ------------------------------------
+#
+# ------------------------------------
+
+global env
+
+# setup environment
+do ../../../../scripts/sim_env.do
+set env(SIM_TARGET) fpga
+set env(SIM_TB) tb_axis_switch_allocator
+
+radix -hexadecimal
+
+make_lib work 1
+
+sim_compile_lib $env(LIB_BASE_DIR) tb_packages
+sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
+sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
+sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
+sim_compile_lib $env(LIB_BASE_DIR) sim
+
+# compile simulation files
+vlog -f ./$env(SIM_TB).f
+
+# simulation $root
+vlog ./$env(SIM_TB)_pkg.sv
+vlog ./$env(SIM_TB).sv
+
+# compile test last
+vlog ./the_test.sv
+
+# run the sim
+sim_run_test
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (revision 36)
@@ -0,0 +1,11 @@
+#
+#
+
+quit -sim
+
+vsim -novopt work.tb_top
+# vsim -f ./sim.f work.tb_top
+
+# log all signals
+log -r *
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (revision 36)
@@ -0,0 +1,6 @@
+#
+
+${PROJECT_DIR}/src/axis_switch.sv
+${PROJECT_DIR}/src/recursive_axis_switch.sv
+
+${PROJECT_DIR}/src/axis_switch_allocator.sv
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (revision 36)
@@ -0,0 +1,118 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// ----------------------------------------------------------------------------
+
+
+module tb_top();
+
+ // --------------------------------------------------------------------
+ // test bench clock & reset
+ wire clk_100mhz;
+ wire tb_clk = clk_100mhz;
+ wire tb_rst;
+
+ tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire tb_rst_s;
+ wire aclk = tb_clk;
+ wire aresetn = ~tb_rst_s;
+ wire clk = tb_clk;
+ wire reset = tb_rst_s;
+
+ sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
+
+
+ // --------------------------------------------------------------------
+ //
+ import tb_axis_switch_allocator_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*);
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*);
+
+
+ // --------------------------------------------------------------------
+ //
+ axis_switch_allocator #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP), .SA(SA))
+ dut(.*);
+
+
+ // --------------------------------------------------------------------
+ // sim models
+ // | | | | | | | | | | | | | | | | |
+ // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+
+
+ // --------------------------------------------------------------------
+ //
+ tb_axis_switch_allocator_class a_h;
+
+ initial
+ a_h = new(axis_in, axis_out);
+
+
+
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+ // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
+ // | | | | | | | | | | | | | | | | |
+ // sim models
+ // --------------------------------------------------------------------
+
+
+ // --------------------------------------------------------------------
+ // debug wires
+
+
+ // --------------------------------------------------------------------
+ // test
+ the_test test(tb_clk, tb_rst);
+
+ initial
+ begin
+
+ test.run_the_test();
+
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench done.", $time);
+ $display("^^^---------------------------------");
+
+ $display("^^^---------------------------------");
+
+ $stop();
+
+ end
+
+endmodule
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (revision 36)
@@ -0,0 +1,143 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+package tb_axis_switch_allocator_pkg;
+
+ // --------------------------------------------------------------------
+ //
+ import video_frame_pkg::*;
+ import axis_video_frame_bfm_pkg::*;
+ import avf_agent_class_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ localparam AW = 32; // active width
+ localparam AH = 16; // active height
+ localparam B = 2; // bytes per pixel
+ localparam T = 1; // pixels per clock
+ localparam VERTICAL_BLANKING = AW * 4;
+ localparam N = B * T; // data bus width in bytes
+ localparam I = 1; // TID width
+ localparam D = 1; // TDEST width
+ localparam U = 3; // TUSER width
+ localparam U_IS_EOP = 2;
+ localparam SA = 3;
+ localparam SD = 2 ** SA;
+
+
+ // --------------------------------------------------------------------
+ //
+ class tb_axis_switch_allocator_class;
+
+ avf_config_class c_h;
+ avf_tile_config_t tile_config[];
+
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[];
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in;
+
+ avf_tx_class #(B, T, U) tx_h;
+ avf_rx_class #(B, T, U) rx_h;
+
+ // video_frame_class clone_h;
+ // video_frame_class sent_f_h;
+ // video_frame_class rx_f_h;
+
+ // mailbox #(video_frame_class) q[];
+
+
+ // --------------------------------------------------------------------
+ //
+ task automatic
+ queue_frame
+ (
+ string pattern = "",
+ int pixel = 0
+ );
+ video_frame_class clone_h;
+
+ if(pattern != "")
+ tx_h.make_frame(pattern, pixel);
+
+ foreach(tx_h.tx_bfm_h[i])
+ begin
+ clone_h = tx_h.tx_bfm_h[i].f_h.clone();
+ tx_h.tx_bfm_h[i].put(clone_h);
+ // q[i].put(clone_h);
+ end
+
+ $display("^^^ %16.t | %m | using %s pattern", $time, pattern);
+
+ endtask: queue_frame
+
+
+ //--------------------------------------------------------------------
+ //
+ function new
+ (
+ virtual axis_if #(.N(N), .U(U)) axis_in,
+ virtual axis_if #(.N(N), .U(U)) axis_out[]
+ );
+
+ this.axis_out = axis_out;
+ this.axis_in = axis_in;
+
+ this.tile_config = new[T];
+ this.tile_config[0].direction = RIGHT_DOWN;
+
+ this.c_h = new
+ (
+ .width(AW),
+ .height(AH),
+ .bytes_per_pixel(B),
+ .bits_per_pixel(B * 8),
+ .pixels_per_clk(T),
+ .name("AVR_"),
+ .vertical_blanking(VERTICAL_BLANKING),
+ .tile(tile_config)
+ );
+
+ rx_h = new(c_h, axis_out);
+ tx_h = new(c_h, '{axis_in});
+
+ endfunction: new
+
+
+ // --------------------------------------------------------------------
+ //
+ endclass: tb_axis_switch_allocator_class
+
+
+// --------------------------------------------------------------------
+//
+endpackage: tb_axis_switch_allocator_pkg
+
+
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (revision 36)
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+
+module the_test(input tb_clk, input tb_rst);
+
+ // --------------------------------------------------------------------
+ //
+ import tb_axis_switch_allocator_pkg::*;
+
+ // --------------------------------------------------------------------
+ //
+ int i = 0;
+
+ task automatic run_the_test;
+
+ // --------------------------------------------------------------------
+ // insert test below
+ // --------------------------------------------------------------------
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench begun.", $time);
+ $display("^^^---------------------------------");
+
+ // --------------------------------------------------------------------
+ tb_top.tb.timeout_stop(2ms);
+ wait(~tb_rst);
+
+ // --------------------------------------------------------------------
+ #1us;
+
+ // // --------------------------------------------------------------------
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+
+ // // --------------------------------------------------------------------
+ // repeat(1) tb_top.a_h.queue_frame("random");
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+ // repeat(3) tb_top.a_h.queue_frame("random");
+ // tb_top.a_h.queue_frame("constant", 16'habba);
+
+ // // --------------------------------------------------------------------
+ // for(i = 0; i < SD; i++)
+ // begin
+ // #1us;
+ // tb_top.a_h.queue_frame("counting");
+ // #8us;
+ // end
+
+ // --------------------------------------------------------------------
+ repeat(SD * 2) tb_top.a_h.queue_frame("counting");
+
+ // --------------------------------------------------------------------
+ #100us;
+
+ // --------------------------------------------------------------------
+ // insert test above
+ // --------------------------------------------------------------------
+
+ endtask
+
+
+endmodule
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (revision 36)
@@ -0,0 +1,35 @@
+# ------------------------------------
+#
+# ------------------------------------
+
+global env
+
+# setup environment
+do ../../../../scripts/sim_env.do
+set env(SIM_TARGET) fpga
+set env(SIM_TB) tb_recursive_axis_catenate
+
+radix -hexadecimal
+
+make_lib work 1
+
+sim_compile_lib $env(LIB_BASE_DIR) tb_packages
+sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
+sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
+sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
+sim_compile_lib $env(LIB_BASE_DIR) sim
+
+# compile simulation files
+vlog -f ./$env(SIM_TB).f
+
+# simulation $root
+vlog ./$env(SIM_TB)_pkg.sv
+vlog ./$env(SIM_TB).sv
+
+# compile test last
+vlog ./the_test.sv
+
+# run the sim
+sim_run_test
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (revision 36)
@@ -0,0 +1,11 @@
+#
+#
+
+quit -sim
+
+vsim -novopt work.tb_top
+# vsim -f ./sim.f work.tb_top
+
+# log all signals
+log -r *
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (revision 36)
@@ -0,0 +1,6 @@
+#
+
+${PROJECT_DIR}/src/recursive_axis_mux.sv
+${PROJECT_DIR}/src/axis_catenate.sv
+${PROJECT_DIR}/src/recursive_axis_catenate.sv
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (revision 36)
@@ -0,0 +1,126 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// ----------------------------------------------------------------------------
+
+
+module tb_top();
+
+ // --------------------------------------------------------------------
+ // test bench clock & reset
+ wire clk_100mhz;
+ wire tb_clk = clk_100mhz;
+ wire tb_rst;
+
+ tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire tb_rst_s;
+ wire aclk = tb_clk;
+ wire aresetn = ~tb_rst_s;
+ wire clk = tb_clk;
+ wire reset = tb_rst_s;
+
+ sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
+
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_catenate_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*);
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
+
+
+ // --------------------------------------------------------------------
+ //
+ recursive_axis_catenate
+ #(
+ .N(N),
+ .I(I),
+ .D(D),
+ .U(U),
+ .U_IS_EOP(U_IS_EOP),
+ .MA(MA)
+ )
+ dut(.*);
+
+
+ // --------------------------------------------------------------------
+ // sim models
+ // | | | | | | | | | | | | | | | | |
+ // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+
+
+ // --------------------------------------------------------------------
+ //
+ tb_recursive_axis_catenate_class a_h;
+
+ initial
+ a_h = new(axis_in, axis_out);
+
+
+
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+ // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
+ // | | | | | | | | | | | | | | | | |
+ // sim models
+ // --------------------------------------------------------------------
+
+
+ // --------------------------------------------------------------------
+ // debug wires
+
+
+ // --------------------------------------------------------------------
+ // test
+ the_test test(tb_clk, tb_rst);
+
+ initial
+ begin
+
+ test.run_the_test();
+
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench done.", $time);
+ $display("^^^---------------------------------");
+
+ $display("^^^---------------------------------");
+
+ $stop();
+
+ end
+
+endmodule
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (revision 36)
@@ -0,0 +1,144 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+package tb_recursive_axis_catenate_pkg;
+
+ // --------------------------------------------------------------------
+ //
+ import video_frame_pkg::*;
+ import axis_video_frame_bfm_pkg::*;
+ import avf_agent_class_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ localparam AW = 32; // active width
+ localparam AH = 16; // active height
+ localparam B = 2; // bytes per pixel
+ localparam T = 1; // pixels per clock
+ localparam VERTICAL_BLANKING = AW * 4;
+ localparam N = B * T; // data bus width in bytes
+ localparam I = 1; // TID width
+ localparam D = 1; // TDEST width
+ localparam U = 3; // TUSER width
+ // localparam U_IS_EOP = 2;
+ localparam U_IS_EOP = -1;
+ localparam MA = 2;
+ localparam MD = 2 ** MA;
+
+
+ // --------------------------------------------------------------------
+ //
+ class tb_recursive_axis_catenate_class;
+
+ avf_config_class c_h;
+ avf_tile_config_t tile_config[];
+
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out;
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[];
+
+ avf_tx_class #(B, T, U) tx_h;
+ avf_rx_class #(B, T, U) rx_h;
+
+ // video_frame_class clone_h;
+ // video_frame_class sent_f_h;
+ // video_frame_class rx_f_h;
+
+ // mailbox #(video_frame_class) q[];
+
+
+ // --------------------------------------------------------------------
+ //
+ task automatic
+ queue_frame
+ (
+ string pattern = "",
+ int pixel = 0
+ );
+ video_frame_class clone_h;
+
+ if(pattern != "")
+ tx_h.make_frame(pattern, pixel);
+
+ foreach(tx_h.tx_bfm_h[i])
+ begin
+ clone_h = tx_h.tx_bfm_h[i].f_h.clone();
+ tx_h.tx_bfm_h[i].put(clone_h);
+ // q[i].put(clone_h);
+ end
+
+ $display("^^^ %16.t | %m | using %s pattern", $time, pattern);
+
+ endtask: queue_frame
+
+
+ //--------------------------------------------------------------------
+ //
+ function new
+ (
+ virtual axis_if #(.N(N), .U(U)) axis_in[],
+ virtual axis_if #(.N(N), .U(U)) axis_out
+ );
+
+ this.axis_out = axis_out;
+ this.axis_in = axis_in;
+
+ this.tile_config = new[T];
+ this.tile_config[0].direction = RIGHT_DOWN;
+
+ this.c_h = new
+ (
+ .width(AW),
+ .height(AH),
+ .bytes_per_pixel(B),
+ .bits_per_pixel(B * 8),
+ .pixels_per_clk(T),
+ .name("AVR_"),
+ .vertical_blanking(VERTICAL_BLANKING),
+ .tile(tile_config)
+ );
+
+ rx_h = new(c_h, '{axis_out});
+ tx_h = new(c_h, axis_in);
+
+ endfunction: new
+
+
+ // --------------------------------------------------------------------
+ //
+ endclass: tb_recursive_axis_catenate_class
+
+
+// --------------------------------------------------------------------
+//
+endpackage: tb_recursive_axis_catenate_pkg
+
+
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (revision 36)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+
+module the_test(input tb_clk, input tb_rst);
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_catenate_pkg::*;
+
+ // --------------------------------------------------------------------
+ //
+ int i = 0;
+
+ task automatic run_the_test;
+
+ // --------------------------------------------------------------------
+ // insert test below
+ // --------------------------------------------------------------------
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench begun.", $time);
+ $display("^^^---------------------------------");
+
+ // --------------------------------------------------------------------
+ tb_top.tb.timeout_stop(2ms);
+ wait(~tb_rst);
+
+ // --------------------------------------------------------------------
+ #1us;
+
+ // --------------------------------------------------------------------
+ repeat(10)tb_top.a_h.queue_frame("counting");
+
+ // // --------------------------------------------------------------------
+ // repeat(1) tb_top.a_h.queue_frame("random");
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+ // repeat(3) tb_top.a_h.queue_frame("random");
+ // tb_top.a_h.queue_frame("constant", 16'habba);
+
+ // // --------------------------------------------------------------------
+ // for(i = 0; i < MD; i++)
+ // begin
+ // force tb_top.select = i;
+ // #20us;
+ // end
+
+ // --------------------------------------------------------------------
+ #100us;
+
+ // --------------------------------------------------------------------
+ // insert test above
+ // --------------------------------------------------------------------
+
+ endtask
+
+
+endmodule
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (revision 36)
@@ -0,0 +1,35 @@
+# ------------------------------------
+#
+# ------------------------------------
+
+global env
+
+# setup environment
+do ../../../../scripts/sim_env.do
+set env(SIM_TARGET) fpga
+set env(SIM_TB) tb_recursive_axis_mux
+
+radix -hexadecimal
+
+make_lib work 1
+
+sim_compile_lib $env(LIB_BASE_DIR) tb_packages
+sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
+sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
+sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
+sim_compile_lib $env(LIB_BASE_DIR) sim
+
+# compile simulation files
+vlog -f ./$env(SIM_TB).f
+
+# simulation $root
+vlog ./$env(SIM_TB)_pkg.sv
+vlog ./$env(SIM_TB).sv
+
+# compile test last
+vlog ./the_test.sv
+
+# run the sim
+sim_run_test
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (revision 36)
@@ -0,0 +1,11 @@
+#
+#
+
+quit -sim
+
+vsim -novopt work.tb_top
+# vsim -f ./sim.f work.tb_top
+
+# log all signals
+log -r *
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (revision 36)
@@ -0,0 +1,4 @@
+#
+
+${PROJECT_DIR}/src/recursive_axis_mux.sv
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (revision 36)
@@ -0,0 +1,126 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// ----------------------------------------------------------------------------
+
+
+module tb_top();
+
+ // --------------------------------------------------------------------
+ // test bench clock & reset
+ wire clk_100mhz;
+ wire tb_clk = clk_100mhz;
+ wire tb_rst;
+
+ tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire tb_rst_s;
+ wire aclk = tb_clk;
+ wire aresetn = ~tb_rst_s;
+ wire clk = tb_clk;
+ wire reset = tb_rst_s;
+
+ sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
+
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_mux_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*);
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire [MA-1:0] select = 0;
+
+ recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA))
+ dut(.*);
+
+
+ // --------------------------------------------------------------------
+ // sim models
+ // | | | | | | | | | | | | | | | | |
+ // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+
+
+ // --------------------------------------------------------------------
+ //
+ initial
+ axis_out.cb_s.tready <= 1;
+
+
+ // --------------------------------------------------------------------
+ //
+ tb_recursive_axis_mux_class a_h;
+
+ initial
+ a_h = new(axis_in, axis_out);
+
+
+
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+ // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
+ // | | | | | | | | | | | | | | | | |
+ // sim models
+ // --------------------------------------------------------------------
+
+
+ // --------------------------------------------------------------------
+ // debug wires
+
+
+ // --------------------------------------------------------------------
+ // test
+ the_test test(tb_clk, tb_rst);
+
+ initial
+ begin
+
+ test.run_the_test();
+
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench done.", $time);
+ $display("^^^---------------------------------");
+
+ $display("^^^---------------------------------");
+
+ $stop();
+
+ end
+
+endmodule
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (revision 36)
@@ -0,0 +1,142 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+package tb_recursive_axis_mux_pkg;
+
+ // --------------------------------------------------------------------
+ //
+ import video_frame_pkg::*;
+ import axis_video_frame_bfm_pkg::*;
+ import avf_agent_class_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ localparam AW = 32; // active width
+ localparam AH = 16; // active height
+ localparam B = 2; // bytes per pixel
+ localparam T = 1; // pixels per clock
+ localparam VERTICAL_BLANKING = AW * 4;
+ localparam N = B * T; // data bus width in bytes
+ localparam I = 1; // TID width
+ localparam D = 1; // TDEST width
+ localparam U = 3; // TUSER width
+ localparam MA = 5;
+ localparam MD = 2 ** MA;
+
+
+ // --------------------------------------------------------------------
+ //
+ class tb_recursive_axis_mux_class;
+
+ avf_config_class c_h;
+ avf_tile_config_t tile_config[];
+
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out;
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[];
+
+ avf_tx_class #(B, T, U) tx_h;
+ avf_rx_class #(B, T, U) rx_h;
+
+ // video_frame_class clone_h;
+ // video_frame_class sent_f_h;
+ // video_frame_class rx_f_h;
+
+ // mailbox #(video_frame_class) q[];
+
+
+ // --------------------------------------------------------------------
+ //
+ task automatic
+ queue_frame
+ (
+ string pattern = "",
+ int pixel = 0
+ );
+ video_frame_class clone_h;
+
+ if(pattern != "")
+ tx_h.make_frame(pattern, pixel);
+
+ foreach(tx_h.tx_bfm_h[i])
+ begin
+ clone_h = tx_h.tx_bfm_h[i].f_h.clone();
+ tx_h.tx_bfm_h[i].put(clone_h);
+ // q[i].put(clone_h);
+ end
+
+ $display("^^^ %16.t | %m | using %s pattern", $time, pattern);
+
+ endtask: queue_frame
+
+
+ //--------------------------------------------------------------------
+ //
+ function new
+ (
+ virtual axis_if #(.N(N), .U(U)) axis_in[],
+ virtual axis_if #(.N(N), .U(U)) axis_out
+ );
+
+ this.axis_out = axis_out;
+ this.axis_in = axis_in;
+
+ this.tile_config = new[T];
+ this.tile_config[0].direction = RIGHT_DOWN;
+
+ this.c_h = new
+ (
+ .width(AW),
+ .height(AH),
+ .bytes_per_pixel(B),
+ .bits_per_pixel(B * 8),
+ .pixels_per_clk(T),
+ .name("AVR_"),
+ .vertical_blanking(VERTICAL_BLANKING),
+ .tile(tile_config)
+ );
+
+ rx_h = new(c_h, '{axis_out});
+ tx_h = new(c_h, axis_in);
+
+ endfunction: new
+
+
+ // --------------------------------------------------------------------
+ //
+ endclass: tb_recursive_axis_mux_class
+
+
+// --------------------------------------------------------------------
+//
+endpackage: tb_recursive_axis_mux_pkg
+
+
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (revision 36)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+
+module the_test(input tb_clk, input tb_rst);
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_mux_pkg::*;
+
+ // --------------------------------------------------------------------
+ //
+ int i = 0;
+
+ task automatic run_the_test;
+
+ // --------------------------------------------------------------------
+ // insert test below
+ // --------------------------------------------------------------------
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench begun.", $time);
+ $display("^^^---------------------------------");
+
+ // --------------------------------------------------------------------
+ // tb_top.tb.timeout_stop(2ms);
+ wait(~tb_rst);
+
+ // --------------------------------------------------------------------
+ #1us;
+
+ // --------------------------------------------------------------------
+ repeat(1)tb_top.a_h.queue_frame("counting");
+
+ // // --------------------------------------------------------------------
+ // repeat(1) tb_top.a_h.queue_frame("random");
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+ // repeat(3) tb_top.a_h.queue_frame("random");
+ // tb_top.a_h.queue_frame("constant", 16'habba);
+
+ // --------------------------------------------------------------------
+ for(i = 0; i < MD; i++)
+ begin
+ force tb_top.select = i;
+ #20us;
+ end
+
+ // --------------------------------------------------------------------
+ #10us;
+
+ // --------------------------------------------------------------------
+ // insert test above
+ // --------------------------------------------------------------------
+
+ endtask
+
+
+endmodule
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (revision 36)
@@ -0,0 +1,35 @@
+# ------------------------------------
+#
+# ------------------------------------
+
+global env
+
+# setup environment
+do ../../../../scripts/sim_env.do
+set env(SIM_TARGET) fpga
+set env(SIM_TB) tb_recursive_axis_switch
+
+radix -hexadecimal
+
+make_lib work 1
+
+sim_compile_lib $env(LIB_BASE_DIR) tb_packages
+sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
+sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
+sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
+sim_compile_lib $env(LIB_BASE_DIR) sim
+
+# compile simulation files
+vlog -f ./$env(SIM_TB).f
+
+# simulation $root
+vlog ./$env(SIM_TB)_pkg.sv
+vlog ./$env(SIM_TB).sv
+
+# compile test last
+vlog ./the_test.sv
+
+# run the sim
+sim_run_test
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (revision 36)
@@ -0,0 +1,11 @@
+#
+#
+
+quit -sim
+
+vsim -novopt work.tb_top
+# vsim -f ./sim.f work.tb_top
+
+# log all signals
+log -r *
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (revision 36)
@@ -0,0 +1,5 @@
+#
+
+${PROJECT_DIR}/src/axis_switch.sv
+${PROJECT_DIR}/src/recursive_axis_switch.sv
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (revision 36)
@@ -0,0 +1,127 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// ----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module tb_top();
+
+ // --------------------------------------------------------------------
+ // test bench clock & reset
+ wire clk_100mhz;
+ wire tb_clk = clk_100mhz;
+ wire tb_rst;
+
+ tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire tb_rst_s;
+ wire aclk = tb_clk;
+ wire aresetn = ~tb_rst_s;
+ wire clk = tb_clk;
+ wire reset = tb_rst_s;
+
+ sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
+
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_switch_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*);
+ axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*);
+
+
+ // --------------------------------------------------------------------
+ //
+ wire [SA-1:0] select = 0;
+
+ recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA))
+ dut(.*);
+
+
+ // --------------------------------------------------------------------
+ // sim models
+ // | | | | | | | | | | | | | | | | |
+ // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+
+
+ // // --------------------------------------------------------------------
+ // //
+ // initial
+ // axis_out.cb_s.tready <= 1;
+
+
+ // --------------------------------------------------------------------
+ //
+ tb_recursive_axis_switch_class a_h;
+
+ initial
+ a_h = new(axis_in, axis_out);
+
+
+
+ // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
+ // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
+ // | | | | | | | | | | | | | | | | |
+ // sim models
+ // --------------------------------------------------------------------
+
+
+ // --------------------------------------------------------------------
+ // debug wires
+
+
+ // --------------------------------------------------------------------
+ // test
+ the_test test(tb_clk, tb_rst);
+
+ initial
+ begin
+
+ test.run_the_test();
+
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench done.", $time);
+ $display("^^^---------------------------------");
+
+ $display("^^^---------------------------------");
+
+ $stop();
+
+ end
+
+endmodule
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (revision 36)
@@ -0,0 +1,142 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+package tb_recursive_axis_switch_pkg;
+
+ // --------------------------------------------------------------------
+ //
+ import video_frame_pkg::*;
+ import axis_video_frame_bfm_pkg::*;
+ import avf_agent_class_pkg::*;
+
+
+ // --------------------------------------------------------------------
+ //
+ localparam AW = 32; // active width
+ localparam AH = 16; // active height
+ localparam B = 2; // bytes per pixel
+ localparam T = 1; // pixels per clock
+ localparam VERTICAL_BLANKING = AW * 4;
+ localparam N = B * T; // data bus width in bytes
+ localparam I = 1; // TID width
+ localparam D = 1; // TDEST width
+ localparam U = 3; // TUSER width
+ localparam SA = 2;
+ localparam SD = 2 ** SA;
+
+
+ // --------------------------------------------------------------------
+ //
+ class tb_recursive_axis_switch_class;
+
+ avf_config_class c_h;
+ avf_tile_config_t tile_config[];
+
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[];
+ virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in;
+
+ avf_tx_class #(B, T, U) tx_h;
+ avf_rx_class #(B, T, U) rx_h;
+
+ // video_frame_class clone_h;
+ // video_frame_class sent_f_h;
+ // video_frame_class rx_f_h;
+
+ // mailbox #(video_frame_class) q[];
+
+
+ // --------------------------------------------------------------------
+ //
+ task automatic
+ queue_frame
+ (
+ string pattern = "",
+ int pixel = 0
+ );
+ video_frame_class clone_h;
+
+ if(pattern != "")
+ tx_h.make_frame(pattern, pixel);
+
+ foreach(tx_h.tx_bfm_h[i])
+ begin
+ clone_h = tx_h.tx_bfm_h[i].f_h.clone();
+ tx_h.tx_bfm_h[i].put(clone_h);
+ // q[i].put(clone_h);
+ end
+
+ $display("^^^ %16.t | %m | using %s pattern", $time, pattern);
+
+ endtask: queue_frame
+
+
+ //--------------------------------------------------------------------
+ //
+ function new
+ (
+ virtual axis_if #(.N(N), .U(U)) axis_in,
+ virtual axis_if #(.N(N), .U(U)) axis_out[]
+ );
+
+ this.axis_out = axis_out;
+ this.axis_in = axis_in;
+
+ this.tile_config = new[T];
+ this.tile_config[0].direction = RIGHT_DOWN;
+
+ this.c_h = new
+ (
+ .width(AW),
+ .height(AH),
+ .bytes_per_pixel(B),
+ .bits_per_pixel(B * 8),
+ .pixels_per_clk(T),
+ .name("AVR_"),
+ .vertical_blanking(VERTICAL_BLANKING),
+ .tile(tile_config)
+ );
+
+ rx_h = new(c_h, axis_out);
+ tx_h = new(c_h, '{axis_in});
+
+ endfunction: new
+
+
+ // --------------------------------------------------------------------
+ //
+ endclass: tb_recursive_axis_switch_class
+
+
+// --------------------------------------------------------------------
+//
+endpackage: tb_recursive_axis_switch_pkg
+
+
+
+
+
Index: qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (nonexistent)
+++ qaz_libs/trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (revision 36)
@@ -0,0 +1,86 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+
+module the_test(input tb_clk, input tb_rst);
+
+ // --------------------------------------------------------------------
+ //
+ import tb_recursive_axis_switch_pkg::*;
+
+ // --------------------------------------------------------------------
+ //
+ int i = 0;
+
+ task automatic run_the_test;
+
+ // --------------------------------------------------------------------
+ // insert test below
+ // --------------------------------------------------------------------
+ $display("^^^---------------------------------");
+ $display("^^^ %16.t | Testbench begun.", $time);
+ $display("^^^---------------------------------");
+
+ // --------------------------------------------------------------------
+ tb_top.tb.timeout_stop(2ms);
+ wait(~tb_rst);
+
+ // --------------------------------------------------------------------
+ #1us;
+
+ // // --------------------------------------------------------------------
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+
+ // // --------------------------------------------------------------------
+ // repeat(1) tb_top.a_h.queue_frame("random");
+ // repeat(1)tb_top.a_h.queue_frame("counting");
+ // repeat(3) tb_top.a_h.queue_frame("random");
+ // tb_top.a_h.queue_frame("constant", 16'habba);
+
+ // --------------------------------------------------------------------
+ for(i = 0; i < SD; i++)
+ begin
+ force tb_top.select = i;
+ #1us;
+ tb_top.a_h.queue_frame("counting");
+ #8us;
+ end
+
+ // --------------------------------------------------------------------
+ #5us;
+
+ // --------------------------------------------------------------------
+ // insert test above
+ // --------------------------------------------------------------------
+
+ endtask
+
+
+endmodule
+
Index: qaz_libs/trunk/axi4_stream_lib/src/axis_alias.sv
===================================================================
--- qaz_libs/trunk/axi4_stream_lib/src/axis_alias.sv (revision 35)
+++ qaz_libs/trunk/axi4_stream_lib/src/axis_alias.sv (revision 36)
@@ -27,6 +27,10 @@
module
axis_alias
+ #(
+ CONNECT_TREADY = 1,
+ CONNECT_TVALID = 1
+ )
(
axis_if axis_in,
axis_if axis_out
@@ -34,9 +38,26 @@
// --------------------------------------------------------------------
//
- assign axis_in.tready = axis_out.tready;
+ generate
+ if(CONNECT_TREADY == 1)
+ begin: tready_gen
+ assign axis_in.tready = axis_out.tready;
+ end
+ endgenerate
- assign axis_out.tvalid = axis_in.tvalid;
+
+ // --------------------------------------------------------------------
+ //
+ generate
+ if(CONNECT_TVALID == 1)
+ begin: tvalid_gen
+ assign axis_out.tvalid = axis_in.tvalid;
+ end
+ endgenerate
+
+
+ // --------------------------------------------------------------------
+ //
assign axis_out.tdata = axis_in.tdata;
assign axis_out.tstrb = axis_in.tstrb;
assign axis_out.tkeep = axis_in.tkeep;
@@ -48,7 +69,6 @@
// --------------------------------------------------------------------
//
-
endmodule
/qaz_libs/trunk/axi4_stream_lib/src/axis_catenate.sv
0,0 → 1,112
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_catenate |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
U_IS_EOP = -1 |
) |
( |
axis_if axis_in [1:0], |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
wire select; |
wire axis_eop; |
|
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules? |
defparam axis_eop_mux_i.MA = 1; |
axis_eop_mux |
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1)) |
axis_eop_mux_i(.axis_in(axis_in), .*); |
|
|
// -------------------------------------------------------------------- |
// state machine binary definitions |
enum reg [1:0] |
{ |
HEAD = 2'b01, |
TAIL = 2'b10 |
} state, next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine flop |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= HEAD; |
else |
state <= next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine |
always_comb |
case(state) |
HEAD: if(axis_eop) |
next_state <= TAIL; |
else |
next_state <= HEAD; |
|
TAIL: if(axis_eop) |
next_state <= HEAD; |
else |
next_state <= TAIL; |
|
default: next_state <= HEAD; |
endcase |
|
|
// -------------------------------------------------------------------- |
// |
defparam axis_mux_i.N = N; // why are needed these for recursive modules? |
defparam axis_mux_i.I = I; |
defparam axis_mux_i.D = D; |
defparam axis_mux_i.U = U; |
axis_mux |
// axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i(.axis_in(axis_in), .*); |
|
|
// -------------------------------------------------------------------- |
// |
assign select = (state == HEAD) ? 0 : 1; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_eop_mux.sv
0,0 → 1,74
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_eop_mux |
#( |
U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser |
MA, // select width |
MD = 2 ** MA |
) |
( |
axis_if axis_in[MD-1:0], |
input [MA-1:0] select, |
output axis_eop, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
wire eop_out[MD-1:0]; |
genvar j; |
|
generate |
for(j = 0; j < MD; j++) |
begin: eop_gen |
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in[j]), |
.tready(axis_in[j].tready), |
.tvalid(axis_in[j].tvalid), |
.axis_eop(eop_out[j]), |
.* |
); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
recursive_mux #(.A(MA), .W(1)) |
recursive_mux_i(select, eop_out, axis_eop); |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_eop_set.sv
0,0 → 1,62
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_eop_set |
#( |
U_IS_EOP = -1 // set to -1 for tlast, else set to index of tuser |
) |
( |
axis_if axis_in, |
input tready, |
input tvalid, |
output axis_eop, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
genvar j; |
|
generate |
if(U_IS_EOP > -1) |
begin: axis_eop_is_tuser_gen |
assign axis_eop = tready & tvalid & axis_in.tuser[U_IS_EOP]; |
end |
else |
begin: axis_eop_is_tlast_gen |
assign axis_eop = tready & tvalid & axis_in.tlast; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_map_fifo.sv
1,6 → 1,6
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// Copyright (C) 2016 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
28,7 → 28,7
module |
axis_map_fifo |
#( |
N = 8, // data bus width in bytes |
N, // data bus width in bytes |
I = 0, // TID width |
D = 0, // TDEST width |
U = 1, // TUSER width |
/qaz_libs/trunk/axi4_stream_lib/src/axis_mux.sv
28,50 → 28,36
module |
axis_mux |
#( |
N, // data bus width in bytes |
I = 0, // TID width |
D = 0, // TDEST width |
U = 1, // TUSER width |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0 // set to 1 to enable, 0 to disable |
) |
( |
input mux_select, |
axis_if axis_0_in, |
axis_if axis_1_in, |
input select, |
axis_if axis_in[1:0], |
axis_if axis_out, |
input axis_en, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_tid_unsuported: assert(I == 0) else $fatal; |
a_tdest_unsuported: assert(D == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(1), .D(1), .U(U)) |
axis_mux_out(.*); |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*); |
|
assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready; |
assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0; |
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready; |
assign axis_in[1].tready = select ? axis_mux_out.tready : 0; |
|
assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid; |
assign axis_mux_out.tdata = mux_select ? axis_1_in.tdata : axis_0_in.tdata; |
assign axis_mux_out.tstrb = mux_select ? axis_1_in.tstrb : axis_0_in.tstrb; |
assign axis_mux_out.tkeep = mux_select ? axis_1_in.tkeep : axis_0_in.tkeep; |
assign axis_mux_out.tlast = mux_select ? axis_1_in.tlast : axis_0_in.tlast; |
assign axis_mux_out.tid = mux_select ? axis_1_in.tid : axis_0_in.tid; |
assign axis_mux_out.tdest = mux_select ? axis_1_in.tdest : axis_0_in.tdest; |
assign axis_mux_out.tuser = mux_select ? axis_1_in.tuser : axis_0_in.tuser; |
assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid; |
assign axis_mux_out.tdata = select ? axis_in[1].tdata : axis_in[0].tdata; |
assign axis_mux_out.tstrb = select ? axis_in[1].tstrb : axis_in[0].tstrb; |
assign axis_mux_out.tkeep = select ? axis_in[1].tkeep : axis_in[0].tkeep; |
assign axis_mux_out.tlast = select ? axis_in[1].tlast : axis_in[0].tlast; |
assign axis_mux_out.tid = select ? axis_in[1].tid : axis_in[0].tid; |
assign axis_mux_out.tdest = select ? axis_in[1].tdest : axis_in[0].tdest; |
assign axis_mux_out.tuser = select ? axis_in[1].tuser : axis_in[0].tuser; |
|
|
// -------------------------------------------------------------------- |
82,21 → 68,19
.I(I), |
.D(D), |
.U(U), |
.USE_TSTRB(USE_TSTRB), |
.USE_TKEEP(USE_TKEEP) |
.USE_TSTRB(0), |
.USE_TKEEP(0) |
) |
axis_register_slice_i |
( |
.axis_in(axis_mux_out), // .slave |
.axis_out(axis_out), // .master |
.axis_in(axis_mux_out), // slave |
.axis_out(axis_out), // master |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_register_slice.sv
28,9 → 28,9
module |
axis_register_slice |
#( |
N = 8, // data bus width in bytes |
I = 0, // TID width |
D = 0, // TDEST width |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0 // set to 1 to enable, 0 to disable |
42,17 → 42,6
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_tid_unsuported: assert(I == 0) else $fatal; |
a_tdest_unsuported: assert(D == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1; |
68,7 → 57,9
wire [W-1:0] rd_data; |
wire rd_en; |
|
tiny_sync_fifo #(.W(W)) |
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules? |
tiny_sync_fifo |
// tiny_sync_fifo #(W) |
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*); |
|
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_switch.sv
0,0 → 1,137
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_switch |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1 // TUSER width |
) |
( |
input select, |
axis_if axis_in, |
axis_if axis_out[1:0], |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_fanout[1:0](.*); |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_fanout[0].tdata = axis_in.tdata; |
assign axis_fanout[0].tstrb = axis_in.tstrb; |
assign axis_fanout[0].tkeep = axis_in.tkeep; |
assign axis_fanout[0].tlast = axis_in.tlast; |
assign axis_fanout[0].tid = axis_in.tid; |
assign axis_fanout[0].tdest = axis_in.tdest; |
assign axis_fanout[0].tuser = axis_in.tuser; |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_fanout[1].tdata = axis_in.tdata; |
assign axis_fanout[1].tstrb = axis_in.tstrb; |
assign axis_fanout[1].tkeep = axis_in.tkeep; |
assign axis_fanout[1].tlast = axis_in.tlast; |
assign axis_fanout[1].tid = axis_in.tid; |
assign axis_fanout[1].tdest = axis_in.tdest; |
assign axis_fanout[1].tuser = axis_in.tuser; |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_in.tready = select ? axis_fanout[1].tready : axis_fanout[0].tready; |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_fanout[0].tvalid = axis_in.tvalid & (select == 0); |
assign axis_fanout[1].tvalid = axis_in.tvalid & (select == 1); |
|
|
// -------------------------------------------------------------------- |
// |
defparam axis_register_slice_lo.N = N; // why are needed these for recursive modules? |
defparam axis_register_slice_lo.I = I; |
defparam axis_register_slice_lo.D = D; |
defparam axis_register_slice_lo.U = U; |
defparam axis_register_slice_lo.USE_TSTRB = 0; |
defparam axis_register_slice_lo.USE_TKEEP = 0; |
axis_register_slice |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(0), |
// .USE_TKEEP(0) |
// ) |
axis_register_slice_lo |
( |
.axis_in(axis_fanout[0]), |
.axis_out(axis_out[0]), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
// why does questasim need these for recursive modules? |
defparam axis_register_slice_hi.N = N; |
defparam axis_register_slice_hi.I = I; |
defparam axis_register_slice_hi.D = D; |
defparam axis_register_slice_hi.U = U; |
defparam axis_register_slice_hi.USE_TSTRB = 0; |
defparam axis_register_slice_hi.USE_TKEEP = 0; |
axis_register_slice |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(0), |
// .USE_TKEEP(0) |
// ) |
axis_register_slice_hi |
( |
.axis_in(axis_fanout[1]), |
.axis_out(axis_out[1]), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/axis_switch_allocator.sv
0,0 → 1,150
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_switch_allocator |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser |
SA, // select width |
SD = 2 ** SA |
) |
( |
axis_if axis_in, |
axis_if axis_out[SD-1:0], |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
wire eop_in; |
|
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in), |
.tready(axis_switch_in.tready), |
.tvalid(axis_in.tvalid), |
.axis_eop(eop_in), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
wire eop_out_mux; |
reg [SA-1:0] select; |
|
axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(SA)) |
axis_eop_mux_i |
( |
.axis_in(axis_out), |
.axis_eop(eop_out_mux), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_in(.*); |
|
axis_alias #(.CONNECT_TREADY(0), .CONNECT_TVALID(0)) |
axis_alias_i(.axis_out(axis_switch_in), .*); |
|
|
// -------------------------------------------------------------------- |
// state machine binary definitions |
enum reg [3:0] |
{ |
ALLOT = 4'b0001, |
FLUSH = 4'b0010, |
SWITCH = 4'b0100, |
SETTLE = 4'b1000 |
} state, next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine flop |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= ALLOT; |
else |
state <= next_state; |
|
|
// -------------------------------------------------------------------- |
// state machine |
always_comb |
case(state) |
ALLOT: if(eop_in) |
next_state <= FLUSH; |
else |
next_state <= ALLOT; |
|
FLUSH: if(eop_out_mux) |
next_state <= SWITCH; |
else |
next_state <= FLUSH; |
|
SWITCH: next_state <= SETTLE; |
|
SETTLE: next_state <= ALLOT; // let select propagate to the switches |
|
default: next_state <= ALLOT; |
endcase |
|
|
// -------------------------------------------------------------------- |
// |
always_ff @(posedge aclk) |
if(~aresetn) |
select <= 0; |
else if(state == SWITCH) |
select <= select + 1; |
|
|
// -------------------------------------------------------------------- |
// |
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA)) |
recursive_axis_switch_i(.axis_in(axis_switch_in), .*); |
|
|
// -------------------------------------------------------------------- |
// |
assign axis_in.tready = (state == ALLOT) & axis_switch_in.tready; |
assign axis_switch_in.tvalid = (state == ALLOT) & axis_in.tvalid; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/recursive_axis_catenate.sv
0,0 → 1,113
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
recursive_axis_catenate |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
U_IS_EOP = -1, |
MA, // mux select width |
MD = 2 ** MA |
) |
( |
axis_if axis_in [MD-1:0], |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
generate |
if(MA == 1) |
begin: catenate_gen |
axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP)) |
axis_catenate_i(.*); |
end |
else |
begin: recursive_catenate_gen |
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_catenate_out[1:0](.*); |
|
recursive_axis_catenate |
#( |
.N(N), |
.I(I), |
.D(D), |
.U(U), |
.U_IS_EOP(U_IS_EOP), |
.MA(MA - 1) |
) |
catenate_lo |
( |
.axis_in(axis_in[(MD/2)-1:0]), |
.axis_out(axis_catenate_out[0]), |
.* |
); |
|
// -------------------------------------------------------------------- |
// |
recursive_axis_catenate |
#( |
.N(N), |
.I(I), |
.D(D), |
.U(U), |
.U_IS_EOP(U_IS_EOP), |
.MA(MA - 1) |
) |
catenate_hi |
( |
.axis_in(axis_in[MD-1:(MD/2)]), |
.axis_out(axis_catenate_out[1]), |
.* |
); |
|
// -------------------------------------------------------------------- |
// |
axis_catenate |
#( |
.N(N), |
.I(I), |
.D(D), |
.U(U), |
.U_IS_EOP(U_IS_EOP) |
) |
axis_catenate_i(.axis_in(axis_catenate_out), .*); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/recursive_axis_mux.sv
0,0 → 1,91
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
recursive_axis_mux |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
MA, // mux select width |
MD = 2 ** MA |
) |
( |
input [MA-1:0] select, |
axis_if axis_in [MD-1:0], |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
generate |
if(MA == 1) |
begin: mux_gen |
axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i(.*); |
end |
else |
begin: recurse_mux_gen |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out[1:0](.*); |
|
recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1)) |
mux_lo |
( |
.select(select[MA-2:0]), |
.axis_in(axis_in[(MD/2)-1:0]), |
.axis_out(axis_mux_out[0]), |
.* |
); |
|
recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1)) |
mux_hi |
( |
.select(select[MA-2:0]), |
.axis_in(axis_in[MD-1:(MD/2)]), |
.axis_out(axis_mux_out[1]), |
.* |
); |
|
axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i |
( |
.select(select[MA-1]), |
.axis_in(axis_mux_out), |
.* |
); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/axi4_stream_lib/src/recursive_axis_switch.sv
0,0 → 1,100
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
recursive_axis_switch |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1, // TUSER width |
SA, // mux select width |
SD = 2 ** SA |
) |
( |
input [SA-1:0] select, |
axis_if axis_in, |
axis_if axis_out[SD-1:0], |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
generate |
if(SA == 1) |
begin: switch_gen |
axis_switch #(.N(N), .I(I), .D(D), .U(U)) |
axis_switch_i(.*); |
end |
else |
begin: recursive_switch_gen |
|
// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_out[1:0](.*); |
|
axis_switch #(.N(N), .I(I), .D(D), .U(U)) |
axis_switch_i |
( |
.select(select[SA-1]), |
.axis_out(axis_switch_out), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA - 1)) |
switch_lo |
( |
.select(select[SA-2:0]), |
.axis_in(axis_switch_out[0]), |
.axis_out(axis_out[(SD/2)-1:0]), |
.* |
); |
|
|
// -------------------------------------------------------------------- |
// |
recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA - 1)) |
switch_hi |
( |
.select(select[SA-2:0]), |
.axis_in(axis_switch_out[1]), |
.axis_out(axis_out[SD-1:(SD/2)]), |
.* |
); |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/qaz_libs/trunk/basal/src/FIFOs/tiny_sync_fifo.sv
29,7 → 29,7
module |
tiny_sync_fifo |
#( |
W = 0 |
W |
) |
( |
output reg wr_full, |
108,9 → 108,9
|
// -------------------------------------------------------------------- |
// |
reg [W - 1:0] data_0_r; |
reg [W - 1:0] data_1_r; |
wire [W - 1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r; |
reg [W-1:0] data_0_r; |
reg [W-1:0] data_1_r; |
wire [W-1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r; |
assign rd_data = wr_data_mux; |
|
always_ff @(posedge clk) |
/qaz_libs/trunk/scripts/sim_procs.do
33,12 → 33,12
global env |
|
echo "INFO: compiling $target rtl" |
|
|
foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -f $filename |
} |
|
|
foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -f $filename |
53,12 → 53,12
global env |
|
echo "INFO: compiling $target rtl" |
|
|
foreach filename [glob -nocomplain -directory ../../libs/${target}_verilog/ *.f] { |
echo "INFO: compiling $filename" |
vlog -f $filename |
} |
|
|
foreach filename [glob -nocomplain -directory ../../libs/${target}_VHDL/ *.f] { |
echo "INFO: compiling $filename" |
vcom -explicit -f $filename |
70,6 → 70,11
# |
proc sim_run_sim { } { |
|
if { [file exists ./pre_sim.do] } { |
echo "INFO: found ./pre_sim.do" |
do ./pre_sim.do |
} |
|
if {[file exists ./sim.do]} { |
do ./sim.do |
} elseif {[file exists ../../libs/sim.do]} { |
79,10 → 84,15
} elseif {[file exists ../../libs/xilinx_sim.f]} { |
vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl |
} |
|
|
if { [file exists ./wave.do] } { |
do ./wave.do |
} |
|
if { [file exists ./post_sim.do] } { |
echo "INFO: found ./post_sim.do" |
do ./post_sim.do |
} |
} |
|
|
118,7 → 128,12
echo "INFO: found ./wip.do" |
do ./wip.do |
} |
|
|
if { [file exists ./pre_sim.do] } { |
echo "INFO: found ./pre_sim.do" |
do ./pre_sim.do |
} |
|
if { [string equal nodesign [runStatus]] } { |
sim_run_sim |
} else { |
126,6 → 141,12
} |
|
run -all |
echo "INFO: run -all done." |
|
if { [file exists ./post_sim.do] } { |
echo "INFO: found ./post_sim.do" |
do ./post_sim.do |
} |
} |
|
|
135,7 → 156,7
|
if {[file exists $lib/_info]} { |
echo "INFO: Simulation library $lib already exists" |
|
|
if { $rebuild != 0 } { |
echo "INFO: Rebuilding library. Deleting ./$lib and recompiling all" |
quit -sim |
143,7 → 164,7
vlib $lib |
vmap $lib $lib |
} |
|
|
} else { |
vlib $lib |
vmap $lib $lib |
/qaz_libs/trunk/sim/libs/axi4_lib_verilog/axi4_stream_base.f
6,7 → 6,6
${LIB_BASE_DIR}/axi4_stream_lib/src/data_to_axis_fsm.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_register_slice.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_flow_control.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_mux.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_alias.sv |
14,4 → 13,5
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_downsizer.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_upsizer.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_synchronizer.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_set.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_mux.sv |