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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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Rev 4 → Rev 5

/qaz_libs/trunk/gear_box/src/unbuffered_gear_box.v
0,0 → 1,81
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
unbuffered_gear_box(
input [12:0] adc_bus,
output adc_rd_en,
 
output reg [7:0] out,
 
input gb_en,
input clk_250,
input sys_reset
);
 
 
// --------------------------------------------------------------------
//
wire adc_bus_bank_select;
wire [3:0] gear_select;
wire ugb_enable = gb_en;
unbuffered_gear_box_fsm
i_unbuffered_gear_box_fsm
(
.ugb_enable(ugb_enable),
.adc_bus_bank_select(adc_bus_bank_select),
.adc_rd_en(adc_rd_en),
.gear_select(gear_select),
.ugb_clock(clk_250),
.ugb_reset(sys_reset)
);
 
// --------------------------------------------------------------------
//
reg [12:0] adc_bus_b0_r;
reg [12:0] adc_bus_b1_r;
 
always @( posedge clk_250 )
if( ~adc_bus_bank_select )
adc_bus_b0_r <= adc_bus;
 
always @( posedge clk_250 )
if( adc_bus_bank_select )
adc_bus_b1_r <= adc_bus;
// --------------------------------------------------------------------
// bypass mux
wire [12:0] adc_bus_b0_w = adc_bus_bank_select ? adc_bus_b0_r : adc_bus;
wire [12:0] adc_bus_b1_w = adc_bus_bank_select ? adc_bus : adc_bus_b1_r;
wire [25:0] adc_bus_mux = {adc_bus_b1_w, adc_bus_b0_w};
 
 
// --------------------------------------------------------------------
// out mux
always @( * )
case( gear_select )
4'h0: out = adc_bus_mux[7:0];
4'h1: out = adc_bus_mux[15:8];
4'h2: out = adc_bus_mux[23:16];
4'h3: out = {adc_bus_mux[5:0],adc_bus_mux[25:24]};
4'h4: out = adc_bus_mux[13:6];
4'h5: out = adc_bus_mux[21:14];
4'h6: out = {adc_bus_mux[3:0],adc_bus_mux[25:22]};
4'h7: out = adc_bus_mux[11:4];
4'h8: out = adc_bus_mux[19:12];
4'h9: out = {adc_bus_mux[1:0],adc_bus_mux[25:20]};
4'ha: out = adc_bus_mux[9:2];
4'hb: out = adc_bus_mux[17:10];
4'hc: out = adc_bus_mux[25:18];
default: out = adc_bus_mux[7:0];
endcase
 
 
endmodule
/qaz_libs/trunk/gear_box/src/sync_fifo.v
0,0 → 1,78
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
sync_fifo
(
input [12:0] fifo_wr_data,
output reg [12:0] fifo_rd_data,
input fifo_wr_en,
input fifo_rd_en,
 
output reg fifo_full,
output reg fifo_empty,
 
input fifo_clock,
input fifo_reset
);
 
// -----------------------------
//
wire wr_en = fifo_wr_en & ~fifo_full;
reg [2:0] wr_ptr;
 
always @( posedge fifo_clock )
if( fifo_reset )
wr_ptr <= 0;
else if( wr_en )
wr_ptr <= wr_ptr + 1;
 
wire rd_en = fifo_rd_en & ~fifo_empty;
reg [2:0] rd_ptr;
 
always @( posedge fifo_clock )
if( fifo_reset )
rd_ptr <= 0;
else if( rd_en )
rd_ptr <= rd_ptr + 1;
 
 
// -----------------------------
//
wire ptr_are_equal = wr_ptr[1:0] == rd_ptr[1:0];
wire ptr_msb_are_equal = ~(wr_ptr[2] ^ rd_ptr[2]);
 
always @( posedge fifo_clock )
if( fifo_reset )
fifo_full <= 0;
else
fifo_full <= ptr_are_equal & ~ptr_msb_are_equal ;
 
always @( posedge fifo_clock )
if( fifo_reset )
fifo_empty <= 1;
else
fifo_empty <= ptr_are_equal & ptr_msb_are_equal ;
 
 
// -----------------------------
//
reg [12:0] reg_file[3:0];
 
always @( posedge fifo_clock )
if( wr_en )
reg_file[wr_ptr[1:0]] <= fifo_wr_data;
 
// always @( posedge fifo_clock )
// if( rd_en )
// fifo_rd_data <= reg_file[rd_ptr[1:0]];
 
always @( * )
fifo_rd_data <= reg_file[rd_ptr[1:0]];
 
 
endmodule
 
 
/qaz_libs/trunk/gear_box/src/unbuffered_gear_box_fsm.v
0,0 → 1,132
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
unbuffered_gear_box_fsm
(
input ugb_enable,
 
output adc_bus_bank_select,
output adc_rd_en,
output [3:0] gear_select,
 
input ugb_clock,
input ugb_reset
);
 
// -----------------------------
// state machine binary definitions
localparam STATE_13_IN_05_RESIDUE = 6'b0_1_0000;
localparam STATE_13_IN_10_RESIDUE = 6'b1_1_0001;
localparam STATE_00_IN_02_RESIDUE = 6'b0_0_0010;
localparam STATE_13_IN_07_RESIDUE = 6'b0_1_0011;
localparam STATE_13_IN_12_RESIDUE = 6'b1_1_0100;
localparam STATE_00_IN_04_RESIDUE = 6'b0_0_0101;
localparam STATE_13_IN_09_RESIDUE = 6'b0_1_0110;
localparam STATE_00_IN_01_RESIDUE = 6'b1_0_0111;
localparam STATE_13_IN_06_RESIDUE = 6'b1_1_1000;
localparam STATE_13_IN_11_RESIDUE = 6'b0_1_1001;
localparam STATE_00_IN_03_RESIDUE = 6'b1_0_1010;
localparam STATE_13_IN_08_RESIDUE = 6'b1_1_1011;
localparam STATE_00_IN_00_RESIDUE = 6'b0_0_1100;
 
 
// -----------------------------
// state machine flop
reg [5:0] state;
reg [5:0] next_state;
 
always @(posedge ugb_clock)
if(ugb_reset)
state <= STATE_00_IN_00_RESIDUE;
else
state <= next_state;
 
 
// -----------------------------
// state machine
 
 
always @( * )
case(state)
STATE_13_IN_05_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_10_RESIDUE;
else
next_state = STATE_13_IN_05_RESIDUE;
 
STATE_13_IN_10_RESIDUE: if( ugb_enable )
next_state = STATE_00_IN_02_RESIDUE;
else
next_state = STATE_13_IN_10_RESIDUE;
 
STATE_00_IN_02_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_07_RESIDUE;
else
next_state = STATE_00_IN_02_RESIDUE;
 
STATE_13_IN_07_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_12_RESIDUE;
else
next_state = STATE_13_IN_07_RESIDUE;
 
STATE_13_IN_12_RESIDUE: if( ugb_enable )
next_state = STATE_00_IN_04_RESIDUE;
else
next_state = STATE_13_IN_12_RESIDUE;
 
STATE_00_IN_04_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_09_RESIDUE;
else
next_state = STATE_00_IN_04_RESIDUE;
 
STATE_13_IN_09_RESIDUE: if( ugb_enable )
next_state = STATE_00_IN_01_RESIDUE;
else
next_state = STATE_13_IN_09_RESIDUE;
 
STATE_00_IN_01_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_06_RESIDUE;
else
next_state = STATE_00_IN_01_RESIDUE;
 
STATE_13_IN_06_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_11_RESIDUE;
else
next_state = STATE_13_IN_06_RESIDUE;
 
STATE_13_IN_11_RESIDUE: if( ugb_enable )
next_state = STATE_00_IN_03_RESIDUE;
else
next_state = STATE_13_IN_11_RESIDUE;
 
STATE_00_IN_03_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_08_RESIDUE;
else
next_state = STATE_00_IN_03_RESIDUE;
 
STATE_13_IN_08_RESIDUE: if( ugb_enable )
next_state = STATE_00_IN_00_RESIDUE;
else
next_state = STATE_13_IN_08_RESIDUE;
 
STATE_00_IN_00_RESIDUE: if( ugb_enable )
next_state = STATE_13_IN_05_RESIDUE;
else
next_state = STATE_00_IN_00_RESIDUE;
 
default: next_state = STATE_00_IN_00_RESIDUE;
 
endcase
 
 
// --------------------------------------------------------------------
// outputs
assign gear_select = state[3:0];
assign adc_rd_en = state[4];
assign adc_bus_bank_select = state[5];
 
 
endmodule
 
/qaz_libs/trunk/gear_box/src/buffered_gear_box.v
0,0 → 1,122
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
buffered_gear_box(
input [12:0] adc_bus,
output adc_data_stall,
 
output [7:0] out,
 
input clk_1250,
input clk_250,
input sys_reset
);
 
 
// --------------------------------------------------------------------
//
reg [3:0] gear_select;
wire gear_reset = sys_reset | ~(gear_select < 4'hc);
 
always @( posedge clk_250 )
if( gear_reset )
gear_select <= 0;
else
gear_select <= gear_select + 1;
 
 
// --------------------------------------------------------------------
//
reg load_shift_r_select;
always @( posedge clk_250 )
if( sys_reset )
load_shift_r_select <= 0;
else if( gear_reset )
load_shift_r_select <= ~load_shift_r_select;
 
// --------------------------------------------------------------------
//
reg [3:0] counter;
wire shift_en = (~gear_reset) & (counter < 4'h8);
 
always @( posedge clk_1250 )
if( gear_reset )
counter <= 0;
else if( shift_en )
counter <= counter + 1;
 
 
// --------------------------------------------------------------------
//
reg [103:0] shift_b0_r;
reg [103:0] shift_b1_r;
 
always @( posedge clk_1250 )
if( ~load_shift_r_select & shift_en )
shift_b0_r <= {adc_bus, shift_b0_r[103:13]};
 
always @( posedge clk_1250 )
if( load_shift_r_select & shift_en )
shift_b1_r <= {adc_bus, shift_b1_r[103:13]};
 
 
// --------------------------------------------------------------------
//
reg [7:0] shift_b0_r_mux;
 
always @( * )
case( gear_select )
4'h0: shift_b0_r_mux = shift_b0_r[7:0];
4'h1: shift_b0_r_mux = shift_b0_r[15:8];
4'h2: shift_b0_r_mux = shift_b0_r[23:16];
4'h3: shift_b0_r_mux = shift_b0_r[31:24];
4'h4: shift_b0_r_mux = shift_b0_r[39:32];
4'h5: shift_b0_r_mux = shift_b0_r[47:40];
4'h6: shift_b0_r_mux = shift_b0_r[55:48];
4'h7: shift_b0_r_mux = shift_b0_r[63:56];
4'h8: shift_b0_r_mux = shift_b0_r[71:64];
4'h9: shift_b0_r_mux = shift_b0_r[79:72];
4'ha: shift_b0_r_mux = shift_b0_r[87:80];
4'hb: shift_b0_r_mux = shift_b0_r[95:88];
4'hc: shift_b0_r_mux = shift_b0_r[103:96];
default: shift_b0_r_mux = shift_b0_r[7:0];
endcase
 
 
// --------------------------------------------------------------------
//
reg [7:0] shift_b1_r_mux;
 
always @( * )
case( gear_select )
4'h0: shift_b1_r_mux = shift_b1_r[7:0];
4'h1: shift_b1_r_mux = shift_b1_r[15:8];
4'h2: shift_b1_r_mux = shift_b1_r[23:16];
4'h3: shift_b1_r_mux = shift_b1_r[31:24];
4'h4: shift_b1_r_mux = shift_b1_r[39:32];
4'h5: shift_b1_r_mux = shift_b1_r[47:40];
4'h6: shift_b1_r_mux = shift_b1_r[55:48];
4'h7: shift_b1_r_mux = shift_b1_r[63:56];
4'h8: shift_b1_r_mux = shift_b1_r[71:64];
4'h9: shift_b1_r_mux = shift_b1_r[79:72];
4'ha: shift_b1_r_mux = shift_b1_r[87:80];
4'hb: shift_b1_r_mux = shift_b1_r[95:88];
4'hc: shift_b1_r_mux = shift_b1_r[103:96];
default: shift_b1_r_mux = shift_b1_r[7:0];
endcase
 
 
// --------------------------------------------------------------------
//
assign adc_data_stall = ~shift_en;
assign out = load_shift_r_select ? shift_b0_r_mux : shift_b1_r_mux;
 
 
endmodule
/qaz_libs/trunk/gear_box/sim/test/debug/the_test.v
0,0 → 1,38
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module the_test(
input tb_clk,
input tb_rst
);
 
task run_the_test;
begin
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
repeat(200) @(posedge tb_clk);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
end
endtask
 
 
endmodule
 
 
/qaz_libs/trunk/gear_box/sim/test/debug/wave.do
0,0 → 1,77
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /tb_top/clk_250
add wave -noupdate -radix hexadecimal /tb_top/tb_rst
add wave -noupdate -radix hexadecimal /tb_top/fifo_full
add wave -noupdate -radix hexadecimal /tb_top/fifo_empty
add wave -noupdate -radix hexadecimal /tb_top/tb_clk
add wave -noupdate -radix hexadecimal /tb_top/fifo_wr_data
add wave -noupdate -radix hexadecimal /tb_top/fifo_wr_en
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/fifo_rd_data[12]} {-radix hexadecimal} {/tb_top/fifo_rd_data[11]} {-radix hexadecimal} {/tb_top/fifo_rd_data[10]} {-radix hexadecimal} {/tb_top/fifo_rd_data[9]} {-radix hexadecimal} {/tb_top/fifo_rd_data[8]} {-radix hexadecimal} {/tb_top/fifo_rd_data[7]} {-radix hexadecimal} {/tb_top/fifo_rd_data[6]} {-radix hexadecimal} {/tb_top/fifo_rd_data[5]} {-radix hexadecimal} {/tb_top/fifo_rd_data[4]} {-radix hexadecimal} {/tb_top/fifo_rd_data[3]} {-radix hexadecimal} {/tb_top/fifo_rd_data[2]} {-radix hexadecimal} {/tb_top/fifo_rd_data[1]} {-radix hexadecimal} {/tb_top/fifo_rd_data[0]} {-radix hexadecimal}} /tb_top/fifo_rd_data
add wave -noupdate -radix hexadecimal /tb_top/fifo_rd_en
add wave -noupdate -radix hexadecimal /tb_top/ugb_adc_bus
add wave -noupdate -radix hexadecimal /tb_top/ugb_out
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/ugb_out_r[103]} {-radix hexadecimal} {/tb_top/ugb_out_r[102]} {-radix hexadecimal} {/tb_top/ugb_out_r[101]} {-radix hexadecimal} {/tb_top/ugb_out_r[100]} {-radix hexadecimal} {/tb_top/ugb_out_r[99]} {-radix hexadecimal} {/tb_top/ugb_out_r[98]} {-radix hexadecimal} {/tb_top/ugb_out_r[97]} {-radix hexadecimal} {/tb_top/ugb_out_r[96]} {-radix hexadecimal} {/tb_top/ugb_out_r[95]} {-radix hexadecimal} {/tb_top/ugb_out_r[94]} {-radix hexadecimal} {/tb_top/ugb_out_r[93]} {-radix hexadecimal} {/tb_top/ugb_out_r[92]} {-radix hexadecimal} {/tb_top/ugb_out_r[91]} {-radix hexadecimal} {/tb_top/ugb_out_r[90]} {-radix hexadecimal} {/tb_top/ugb_out_r[89]} {-radix hexadecimal} {/tb_top/ugb_out_r[88]} {-radix hexadecimal} {/tb_top/ugb_out_r[87]} {-radix hexadecimal} {/tb_top/ugb_out_r[86]} {-radix hexadecimal} {/tb_top/ugb_out_r[85]} {-radix hexadecimal} {/tb_top/ugb_out_r[84]} {-radix hexadecimal} {/tb_top/ugb_out_r[83]} {-radix hexadecimal} {/tb_top/ugb_out_r[82]} {-radix hexadecimal} {/tb_top/ugb_out_r[81]} {-radix hexadecimal} {/tb_top/ugb_out_r[80]} {-radix hexadecimal} {/tb_top/ugb_out_r[79]} {-radix hexadecimal} {/tb_top/ugb_out_r[78]} {-radix hexadecimal} {/tb_top/ugb_out_r[77]} {-radix hexadecimal} {/tb_top/ugb_out_r[76]} {-radix hexadecimal} {/tb_top/ugb_out_r[75]} {-radix hexadecimal} {/tb_top/ugb_out_r[74]} {-radix hexadecimal} {/tb_top/ugb_out_r[73]} {-radix hexadecimal} {/tb_top/ugb_out_r[72]} {-radix hexadecimal} {/tb_top/ugb_out_r[71]} {-radix hexadecimal} {/tb_top/ugb_out_r[70]} {-radix hexadecimal} {/tb_top/ugb_out_r[69]} {-radix hexadecimal} {/tb_top/ugb_out_r[68]} {-radix hexadecimal} {/tb_top/ugb_out_r[67]} {-radix hexadecimal} {/tb_top/ugb_out_r[66]} {-radix hexadecimal} {/tb_top/ugb_out_r[65]} {-radix hexadecimal} {/tb_top/ugb_out_r[64]} {-radix hexadecimal} {/tb_top/ugb_out_r[63]} {-radix hexadecimal} {/tb_top/ugb_out_r[62]} {-radix hexadecimal} {/tb_top/ugb_out_r[61]} {-radix hexadecimal} {/tb_top/ugb_out_r[60]} {-radix hexadecimal} {/tb_top/ugb_out_r[59]} {-radix hexadecimal} {/tb_top/ugb_out_r[58]} {-radix hexadecimal} {/tb_top/ugb_out_r[57]} {-radix hexadecimal} {/tb_top/ugb_out_r[56]} {-radix hexadecimal} {/tb_top/ugb_out_r[55]} {-radix hexadecimal} {/tb_top/ugb_out_r[54]} {-radix hexadecimal} {/tb_top/ugb_out_r[53]} {-radix hexadecimal} {/tb_top/ugb_out_r[52]} {-radix hexadecimal} {/tb_top/ugb_out_r[51]} {-radix hexadecimal} {/tb_top/ugb_out_r[50]} {-radix hexadecimal} {/tb_top/ugb_out_r[49]} {-radix hexadecimal} {/tb_top/ugb_out_r[48]} {-radix hexadecimal} {/tb_top/ugb_out_r[47]} {-radix hexadecimal} {/tb_top/ugb_out_r[46]} {-radix hexadecimal} {/tb_top/ugb_out_r[45]} {-radix hexadecimal} {/tb_top/ugb_out_r[44]} {-radix hexadecimal} {/tb_top/ugb_out_r[43]} {-radix hexadecimal} {/tb_top/ugb_out_r[42]} {-radix hexadecimal} {/tb_top/ugb_out_r[41]} {-radix hexadecimal} {/tb_top/ugb_out_r[40]} {-radix hexadecimal} {/tb_top/ugb_out_r[39]} {-radix hexadecimal} {/tb_top/ugb_out_r[38]} {-radix hexadecimal} {/tb_top/ugb_out_r[37]} {-radix hexadecimal} {/tb_top/ugb_out_r[36]} {-radix hexadecimal} {/tb_top/ugb_out_r[35]} {-radix hexadecimal} {/tb_top/ugb_out_r[34]} {-radix hexadecimal} {/tb_top/ugb_out_r[33]} {-radix hexadecimal} {/tb_top/ugb_out_r[32]} {-radix hexadecimal} {/tb_top/ugb_out_r[31]} {-radix hexadecimal} {/tb_top/ugb_out_r[30]} {-radix hexadecimal} {/tb_top/ugb_out_r[29]} {-radix hexadecimal} {/tb_top/ugb_out_r[28]} {-radix hexadecimal} {/tb_top/ugb_out_r[27]} {-radix hexadecimal} {/tb_top/ugb_out_r[26]} {-radix hexadecimal} {/tb_top/ugb_out_r[25]} {-radix hexadecimal} {/tb_top/ugb_out_r[24]} {-radix hexadecimal} {/tb_top/ugb_out_r[23]} {-radix hexadecimal} {/tb_top/ugb_out_r[22]} {-radix hexadecimal} {/tb_top/ugb_out_r[21]} {-radix hexadecimal} {/tb_top/ugb_out_r[20]} {-radix hexadecimal} {/tb_top/ugb_out_r[19]} {-radix hexadecimal} {/tb_top/ugb_out_r[18]} {-radix hexadecimal} {/tb_top/ugb_out_r[17]} {-radix hexadecimal} {/tb_top/ugb_out_r[16]} {-radix hexadecimal} {/tb_top/ugb_out_r[15]} {-radix hexadecimal} {/tb_top/ugb_out_r[14]} {-radix hexadecimal} {/tb_top/ugb_out_r[13]} {-radix hexadecimal} {/tb_top/ugb_out_r[12]} {-radix hexadecimal} {/tb_top/ugb_out_r[11]} {-radix hexadecimal} {/tb_top/ugb_out_r[10]} {-radix hexadecimal} {/tb_top/ugb_out_r[9]} {-radix hexadecimal} {/tb_top/ugb_out_r[8]} {-radix hexadecimal} {/tb_top/ugb_out_r[7]} {-radix hexadecimal} {/tb_top/ugb_out_r[6]} {-radix hexadecimal} {/tb_top/ugb_out_r[5]} {-radix hexadecimal} {/tb_top/ugb_out_r[4]} {-radix hexadecimal} {/tb_top/ugb_out_r[3]} {-radix hexadecimal} {/tb_top/ugb_out_r[2]} {-radix hexadecimal} {/tb_top/ugb_out_r[1]} {-radix hexadecimal} {/tb_top/ugb_out_r[0]} {-radix hexadecimal}} /tb_top/ugb_out_r
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/dbg_ugb_shift[7]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[6]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[5]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[4]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[3]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[2]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[1]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[0]} {-height 15 -radix hexadecimal}} -expand -subitemconfig {{/tb_top/dbg_ugb_shift[7]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[6]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[5]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[4]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[3]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[2]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[1]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_shift[0]} {-height 15 -radix hexadecimal}} /tb_top/dbg_ugb_shift
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/dbg_ugb_out[12]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[11]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[10]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[9]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[8]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[7]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[6]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[5]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[4]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[3]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[2]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[1]} {-radix hexadecimal} {/tb_top/dbg_ugb_out[0]} {-radix hexadecimal}} /tb_top/dbg_ugb_out
add wave -noupdate -divider {New Divider}
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_clock
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_wr_data
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_full
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_rd_en
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_rd_data
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_empty
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/fifo_reset
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/wr_en
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/wr_ptr
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/rd_en
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/rd_ptr
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/ptr_are_equal
add wave -noupdate -radix hexadecimal /tb_top/i_sync_fifo/ptr_msb_are_equal
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/i_sync_fifo/reg_file[3]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[2]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[1]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[0]} {-height 15 -radix hexadecimal}} -expand -subitemconfig {{/tb_top/i_sync_fifo/reg_file[3]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[2]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[1]} {-height 15 -radix hexadecimal} {/tb_top/i_sync_fifo/reg_file[0]} {-height 15 -radix hexadecimal}} /tb_top/i_sync_fifo/reg_file
add wave -noupdate -divider {New Divider}
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/out
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/clk_250
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/sys_reset
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus_bank_select
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/gear_select
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/ugb_enable
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[12]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[11]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[10]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[9]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[8]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[7]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[6]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[5]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[4]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[3]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[2]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[1]} {-radix hexadecimal} {/tb_top/i_unbuffered_gear_box/adc_bus_b0_r[0]} {-radix hexadecimal}} /tb_top/i_unbuffered_gear_box/adc_bus_b0_r
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus_b1_r
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus_b0_w
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus_b1_w
add wave -noupdate -radix hexadecimal /tb_top/i_unbuffered_gear_box/adc_bus_mux
add wave -noupdate -divider {New Divider}
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/dbg_ugb_pixels_out_r[7]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[6]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[5]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[4]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[3]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[2]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[1]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[0]} {-height 15 -radix hexadecimal}} -expand -subitemconfig {{/tb_top/dbg_ugb_pixels_out_r[7]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[6]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[5]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[4]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[3]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[2]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[1]} {-height 15 -radix hexadecimal} {/tb_top/dbg_ugb_pixels_out_r[0]} {-height 15 -radix hexadecimal}} /tb_top/dbg_ugb_pixels_out_r
add wave -noupdate -divider {New Divider}
add wave -noupdate -radix hexadecimal /tb_top/tb_rst
add wave -noupdate -radix hexadecimal /tb_top/fifo_wr_data
add wave -noupdate -radix hexadecimal /tb_top/fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_top/fifo_full
add wave -noupdate -radix hexadecimal -subitemconfig {{/tb_top/fifo_rd_data[12]} {-radix hexadecimal} {/tb_top/fifo_rd_data[11]} {-radix hexadecimal} {/tb_top/fifo_rd_data[10]} {-radix hexadecimal} {/tb_top/fifo_rd_data[9]} {-radix hexadecimal} {/tb_top/fifo_rd_data[8]} {-radix hexadecimal} {/tb_top/fifo_rd_data[7]} {-radix hexadecimal} {/tb_top/fifo_rd_data[6]} {-radix hexadecimal} {/tb_top/fifo_rd_data[5]} {-radix hexadecimal} {/tb_top/fifo_rd_data[4]} {-radix hexadecimal} {/tb_top/fifo_rd_data[3]} {-radix hexadecimal} {/tb_top/fifo_rd_data[2]} {-radix hexadecimal} {/tb_top/fifo_rd_data[1]} {-radix hexadecimal} {/tb_top/fifo_rd_data[0]} {-radix hexadecimal}} /tb_top/fifo_rd_data
add wave -noupdate -radix hexadecimal /tb_top/fifo_rd_en
add wave -noupdate -radix hexadecimal /tb_top/fifo_empty
add wave -noupdate -radix hexadecimal /tb_top/bank_sel
add wave -noupdate -radix unsigned /tb_top/gear
add wave -noupdate -radix hexadecimal /tb_top/gear_box_out
add wave -noupdate -radix hexadecimal /tb_top/clk_250
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {43950 ps} 0}
configure wave -namecolwidth 197
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {890400 ps}
/qaz_libs/trunk/gear_box/sim/scripts/compile_all.do
0,0 → 1,20
 
if {[file exists work/_info]} {
echo "INFO: Simulation library work already exists"
} else {
vlib work
}
 
 
vlog ../../../../libs/hdl/clock/tb_clk.v
vlog ../../../../libs/hdl/system/tb_reset.v
 
vlog ../../src/tb_top.v
 
vlog ./the_test.v
 
vlog ../../../src/buffered_gear_box.v
vlog ../../../src/unbuffered_gear_box.v
vlog ../../../src/unbuffered_gear_box_fsm.v
vlog ../../../src/sync_fifo.v
 
/qaz_libs/trunk/gear_box/sim/scripts/sim_init.do
0,0 → 1,6
 
vlog +define+DEBUG "../../src/tb_top.v"
 
vsim -voptargs=+acc -l transcript.txt -t 1ps work.tb_top
 
#do wave.do
/qaz_libs/trunk/gear_box/sim/scripts/sim_restart.do
0,0 → 1,17
 
vlog +define+DEBUG "../../src/tb_top.v"
 
vlog ./the_test.v
 
vlog ../../../src/buffered_gear_box.v
vlog ../../../src/unbuffered_gear_box.v
vlog ../../../src/unbuffered_gear_box_fsm.v
vlog ../../../src/sync_fifo.v
 
 
restart -force
 
#run 100us
 
run -all
 
/qaz_libs/trunk/gear_box/sim/src/tb_top.v
0,0 → 1,179
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 10ps/1ps
 
 
module tb_top();
 
// --------------------------------------------------------------------
// system wires
wire clk_250;
wire tb_clk = clk_250;
wire tb_rst;
 
// --------------------------------------------------------------------
// clock & reset
 
parameter CLK_PERIOD = 400; // use 250MHZ for main clk
tb_clk #( .CLK_PERIOD(400) ) i_clk_250 ( clk_250 );
 
tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst );
 
initial
begin
$display("\n^^^---------------------------------");
#(CLK_PERIOD/3);
i_tb_rst.assert_reset();
end
 
 
// dut
// --------------------------------------------------------------------
wire ugb_adc_rd_en;
wire fifo_full;
wire fifo_empty;
reg [12:0] fifo_wr_data;
wire [12:0] fifo_rd_data;
wire fifo_wr_en = ~tb_rst & ~fifo_full;
wire fifo_rd_en = ~tb_rst & ugb_adc_rd_en & ~fifo_empty;
wire [12:0] ugb_adc_bus = fifo_rd_data;
wire [7:0] ugb_out;
unbuffered_gear_box
i_unbuffered_gear_box
(
.adc_bus(ugb_adc_bus),
.adc_rd_en(ugb_adc_rd_en),
 
.out(ugb_out),
 
.gb_en(~fifo_empty),
.clk_250(clk_250),
.sys_reset(tb_rst)
);
 
sync_fifo
i_sync_fifo
(
.fifo_wr_data(fifo_wr_data),
.fifo_rd_data(fifo_rd_data),
.fifo_wr_en(fifo_wr_en),
.fifo_rd_en(fifo_rd_en),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty),
.fifo_clock(clk_250),
.fifo_reset(tb_rst)
);
 
// --------------------------------------------------------------------
// dut
 
// --------------------------------------------------------------------
// sim modles
// tb_log log();
 
 
always @( posedge clk_250 )
if( tb_rst )
fifo_wr_data <= 0;
else if( fifo_wr_en )
fifo_wr_data <= fifo_wr_data + 1;
reg [103:0] ugb_out_r;
 
always @( posedge clk_250 )
ugb_out_r <= {ugb_out, ugb_out_r[103:8]};
 
wire [12:0] dbg_ugb_shift[7:0];
assign dbg_ugb_shift[0] = ugb_out_r[12:0];
assign dbg_ugb_shift[1] = ugb_out_r[25:13];
assign dbg_ugb_shift[2] = ugb_out_r[38:26];
assign dbg_ugb_shift[3] = ugb_out_r[51:39];
assign dbg_ugb_shift[4] = ugb_out_r[64:52];
assign dbg_ugb_shift[5] = ugb_out_r[77:65];
assign dbg_ugb_shift[6] = ugb_out_r[90:78];
assign dbg_ugb_shift[7] = ugb_out_r[103:91];
 
wire [7:0] dbg_ugb_out[12:0];
 
assign dbg_ugb_out[0] = ugb_out_r[7:0];
assign dbg_ugb_out[1] = ugb_out_r[15:8];
assign dbg_ugb_out[2] = ugb_out_r[23:16];
assign dbg_ugb_out[3] = ugb_out_r[31:24];
assign dbg_ugb_out[4] = ugb_out_r[39:32];
assign dbg_ugb_out[5] = ugb_out_r[47:40];
assign dbg_ugb_out[6] = ugb_out_r[55:48];
assign dbg_ugb_out[7] = ugb_out_r[63:56];
assign dbg_ugb_out[8] = ugb_out_r[71:64];
assign dbg_ugb_out[9] = ugb_out_r[79:72];
assign dbg_ugb_out[10] = ugb_out_r[87:80];
assign dbg_ugb_out[11] = ugb_out_r[95:88];
assign dbg_ugb_out[12] = ugb_out_r[103:96];
reg [12:0] dbg_ugb_pixels_out_r[7:0];
integer j;
always @( posedge clk_250 )
if( i_unbuffered_gear_box.gear_select == 0 )
for( j = 0; j < 8; j = j + 1 )
dbg_ugb_pixels_out_r[j] <= dbg_ugb_shift[j];
// sim modles
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// waveform signals
wire [3:0] gear = i_unbuffered_gear_box.gear_select;
wire bank_sel = i_unbuffered_gear_box.adc_bus_bank_select;
wire [12:0] adc_bus_in = ugb_adc_bus;
wire [7:0] gear_box_out = ugb_out;
wire adc_bus_rd_en = ugb_adc_rd_en;
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
wait( ~tb_rst );
 
repeat(2) @(posedge tb_clk);
 
test.run_the_test();
 
$display("\n^^^---------------------------------");
$display("^^^ %15.t | Testbench done.\n", $time);
$display("\n^^^---------------------------------");
// log.log_fail_count();
$display("\n^^^---------------------------------");
 
`ifdef DEBUG
$stop();
`else
$finish();
`endif
 
end
 
endmodule
 

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