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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/sim/tests
    from Rev 32 to Rev 34
    Reverse comparison

Rev 32 → Rev 34

/tb_riffa_axis_test_pattern/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_axis_test_pattern
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/tb_riffa_axis_test_pattern/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern.f
0,0 → 1,18
#
 
${LIB_BASE_DIR}/PCIe/sim/src/riffa_bfm_class_pkg.sv
${LIB_BASE_DIR}/PCIe/sim/src/riffa_agent_class_pkg.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_if.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_register_if.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_tx_fsm.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_tx.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_rx_fsm.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_rx.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_test_patern.sv
 
 
/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern.sv
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
wire aclk = clk;
wire aresetn = ~reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_axis_test_pattern_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
 
 
// --------------------------------------------------------------------
//
wire [31:0] tx_len = TX_L;
 
riffa_axis_test_pattern #(.N(N))
dut(.*);
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
tb_riffa_axis_test_pattern_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern_pkg.sv
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_axis_test_pattern_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam N = 16; // RIFFA bus width in bytes
localparam I = 0; // TID width
localparam D = 0; // TDEST width
localparam U = 3; // TUSER width
localparam TX_L = 256 * 256; // RIFFA tx length
 
 
// --------------------------------------------------------------------
//
class tb_riffa_axis_test_pattern_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_axis_test_pattern_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_axis_test_pattern_pkg
 
 
 
 
 
/tb_riffa_axis_test_pattern/the_test.sv
0,0 → 1,93
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_axis_test_pattern_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(500us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// // --------------------------------------------------------------------
// $display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/tb_riffa_register_file/tb_riffa_register_file.sv
53,12 → 53,12
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_register_if #(.N(N), .MW(MW)) r_if(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.A(A), .N(N), .MW(MW))
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
 
70,7 → 70,7
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < MI; j++)
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
35,11 → 35,9
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 16; // width of the bus in bytes
localparam MW = 3; // mux select width
localparam MI = 2 ** MW; // mux inputs
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
 
// --------------------------------------------------------------------
/tb_riffa_register_file/the_test.sv
59,7 → 59,7
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*MI, 0, 1);
tb_top.a_h.queue_tx_random(RW*B, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
66,7 → 66,7
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*MI, 0, 1);
tb_top.a_h.queue_rx(RW*B, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------

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