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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/src/RIFFA
    from Rev 37 to Rev 39
    Reverse comparison

Rev 37 → Rev 39

/axis_to_riffa_tx.sv
0,0 → 1,78
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axis_to_riffa_tx
#(
N // RIFFA data bus width in bytes
)
(
axis_if axis_in,
riffa_chnl_if chnl_bus,
input [31:0] tx_len,
input [30:0] tx_off,
input tx_ready,
input tx_last,
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the RIFFA bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
wire acked;
wire [30:0] tx_index;
wire tx_done = (tx_index >= tx_len - RW) & tx_ready;
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axis_in.tready = chnl_bus.tx_data_ren & acked;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = tx_last;
assign chnl_bus.tx_len = tx_len;
assign chnl_bus.tx_off = tx_off;
assign chnl_bus.tx_data_valid = axis_in.tvalid & acked;
assign chnl_bus.tx_data = axis_in.tdata;
 
 
// --------------------------------------------------------------------
//
endmodule
 
 
 
 
/riffa_axis_test_pattern.sv
34,7 → 34,7
WPB = N / W // number of words per beat
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_bus,
input [31:0] tx_len,
input clk,
input reset
77,20 → 77,20
 
// --------------------------------------------------------------------
//
assign axis_out.tready = chnl_in.tx_data_ren & acked;
assign axis_out.tready = chnl_bus.tx_data_ren & acked;
 
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = tx_last;
assign chnl_in.tx_len = tx_len;
assign chnl_in.tx_off = tx_off;
assign chnl_in.tx_data_valid = axis_out.tvalid & acked;
assign chnl_in.tx_data = axis_out.tdata;
assign chnl_bus.rx_clk = clk;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = tx_last;
assign chnl_bus.tx_len = tx_len;
assign chnl_bus.tx_off = tx_off;
assign chnl_bus.tx_data_valid = axis_out.tvalid & acked;
assign chnl_bus.tx_data = axis_out.tdata;
 
// --------------------------------------------------------------------
//
/riffa_chnl_tx.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
31,7 → 31,7
N // data bus width in bytes
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_bus,
input tx_ready,
input tx_done,
output acked,
45,12 → 45,12
);
 
// --------------------------------------------------------------------
//
//
riffa_chnl_tx_fsm
riffa_chnl_tx_fsm_i
(
.tx(chnl_in.tx),
.tx_ack(chnl_in.tx_ack),
.tx(chnl_bus.tx),
.tx_ack(chnl_bus.tx_ack),
.*
);
 
58,9 → 58,9
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | ~chnl_in.tx | tx_done)
if(reset | ~chnl_bus.tx | tx_done)
tx_index = 0;
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren)
tx_index <= tx_index + (N/4); // increment by 32 bit words
 
 
/riffa_chnl_w.sv
56,7 → 56,7
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN, // Channel write data has been received
 
riffa_chnl_if chnl_in[C_NUM_CHNL]
riffa_chnl_if chnl_bus[C_NUM_CHNL]
);
 
// --------------------------------------------------------------------
65,25 → 65,25
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1)
begin : channels
assign CHNL_RX_CLK[i] = chnl_in[i].rx_clk;
assign chnl_in[i].rx = CHNL_RX[i];
assign CHNL_RX_ACK[i] = chnl_in[i].rx_ack;
assign chnl_in[i].rx_last = CHNL_RX_LAST[i];
assign chnl_in[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
assign chnl_in[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
assign chnl_in[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
assign chnl_in[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
assign CHNL_RX_DATA_REN[i] = chnl_in[i].rx_data_ren;
assign CHNL_RX_CLK[i] = chnl_bus[i].rx_clk;
assign chnl_bus[i].rx = CHNL_RX[i];
assign CHNL_RX_ACK[i] = chnl_bus[i].rx_ack;
assign chnl_bus[i].rx_last = CHNL_RX_LAST[i];
assign chnl_bus[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
assign chnl_bus[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
assign chnl_bus[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
assign chnl_bus[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
assign CHNL_RX_DATA_REN[i] = chnl_bus[i].rx_data_ren;
 
assign CHNL_TX_CLK[i] = chnl_in[i].tx_clk;
assign CHNL_TX[i] = chnl_in[i].tx;
assign chnl_in[i].tx_ack = CHNL_TX_ACK[i];
assign CHNL_TX_LAST[i] = chnl_in[i].tx_last;
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_in[i].tx_len;
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_in[i].tx_off;
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_in[i].tx_data;
assign CHNL_TX_DATA_VALID[i] = chnl_in[i].tx_data_valid;
assign chnl_in[i].tx_data_ren = CHNL_TX_DATA_REN[i];
assign CHNL_TX_CLK[i] = chnl_bus[i].tx_clk;
assign CHNL_TX[i] = chnl_bus[i].tx;
assign chnl_bus[i].tx_ack = CHNL_TX_ACK[i];
assign CHNL_TX_LAST[i] = chnl_bus[i].tx_last;
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_bus[i].tx_len;
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_bus[i].tx_off;
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_bus[i].tx_data;
assign CHNL_TX_DATA_VALID[i] = chnl_bus[i].tx_data_valid;
assign chnl_bus[i].tx_data_ren = CHNL_TX_DATA_REN[i];
end
endgenerate
 
/riffa_register_file.sv
32,7 → 32,7
B // number of register banks
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_bus,
riffa_register_if r_if,
input clk, // must be same clock domain as rx_clk & tx_clk
input reset // must be same clock domain as rx_clk & tx_clk
69,7 → 69,7
wire rd_en;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
riffa_chn_rx_i(.chnl_bus(chnl_bus), .*);
 
 
// --------------------------------------------------------------------
97,7 → 97,7
 
// --------------------------------------------------------------------
//
// assign chnl_in.rx_data_ren = rx_data_ren;
// assign chnl_bus.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
 
 
104,13 → 104,13
// --------------------------------------------------------------------
//
// write to register[0][0] to enable reading
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire tx_done = (tx_index >= chnl_in.tx_len - RW);
wire tx_done = (tx_index >= chnl_bus.tx_len - RW);
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
137,7 → 137,7
recursive_mux_i
(
.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
.data_out(chnl_in.tx_data),
.data_out(chnl_bus.tx_data),
.*
);
 
144,14 → 144,14
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = 1;
assign chnl_in.tx_len = RC;
assign chnl_in.tx_off = 0;
assign chnl_in.tx_data_valid = acked;
assign chnl_bus.rx_clk = clk;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = 1;
assign chnl_bus.tx_len = RC;
assign chnl_bus.tx_off = 0;
assign chnl_bus.tx_data_valid = acked;
 
 
// --------------------------------------------------------------------
/riffa_rx_to_axis.sv
0,0 → 1,70
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
riffa_rx_to_axis
#(
N // RIFFA bus width in bytes
)
(
axis_if axis_out,
riffa_chnl_if chnl_bus,
input rx_ready,
output rx_done,
output [30:0] rx_index,
output rx_last,
output [31:0] rx_len,
output [30:0] rx_off,
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en = axis_out.tvalid & axis_out.tready;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.*);
 
 
// --------------------------------------------------------------------
//
assign chnl_bus.rx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign axis_out.tvalid = ~rd_empty;
assign axis_out.tdata = rd_data;
 
 
// --------------------------------------------------------------------
//
endmodule
 
 
 

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