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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/PCIe/src
    from Rev 34 to Rev 35
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  •

Rev 34 → Rev 35

/RIFFA/riffa_chnl_rx.sv
31,13 → 31,14
N // data bus width in bytes
)
(
riffa_chnl_if chnl_in,
riffa_chnl_if chnl_bus,
input rx_ready,
output rx_done,
output reg [30:0] rx_index,
output reg rx_last,
output reg [31:0] rx_len,
output reg [30:0] rx_off,
output rx_data_ren,
// output rx_data_ren, // shouldn't be here??
output rd_empty,
output [(8*N)-1:0] rd_data,
input rd_en,
51,9 → 52,9
riffa_chnl_rx_fsm
riffa_chnl_rx_fsm_i
(
.rx(chnl_in.rx),
.rx_data_valid(chnl_in.rx_data_valid),
.rx_ack(chnl_in.rx_ack),
.rx(chnl_bus.rx),
.rx_data_valid(chnl_bus.rx_data_valid),
.rx_ack(chnl_bus.rx_ack),
.*
);
 
61,19 → 62,19
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(chnl_in.rx & chnl_in.rx_ack)
if(chnl_bus.rx & chnl_bus.rx_ack)
begin
rx_last <= chnl_in.rx_last;
rx_len <= chnl_in.rx_len;
rx_off <= chnl_in.rx_off;
rx_last <= chnl_bus.rx_last;
rx_len <= chnl_bus.rx_len;
rx_off <= chnl_bus.rx_off;
end
 
 
// --------------------------------------------------------------------
//
wire [(8*N)-1:0] wr_data = chnl_in.rx_data;
wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;
wire wr_full;
wire wr_en = chnl_in.rx_data_ren & chnl_in.rx_data_valid;
wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;
 
tiny_sync_fifo #(.W((8*N)))
tiny_sync_fifo_i(.*);
90,7 → 91,8
 
// --------------------------------------------------------------------
//
assign rx_data_ren = ~wr_full;
// assign rx_data_ren = ~wr_full; // shouldn't be here??
assign chnl_bus.rx_data_ren = ~wr_full;
 
 
// --------------------------------------------------------------------
/RIFFA/riffa_chnl_rx_fsm.sv
30,6 → 30,7
(
input rx,
input rx_data_valid,
input rx_ready,
output rx_ack,
output rx_done,
 
67,7 → 68,11
else
next_state <= IDLE;
 
ACK: next_state <= RX;
// ACK: next_state <= RX;
ACK: if(rx_ready)
next_state <= RX;
else
next_state <= ACK;
 
RX: if(rx)
next_state <= RX;
/RIFFA/riffa_register_file.sv
28,9 → 28,8
module
riffa_register_file
#(
A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
B // number of register banks
)
(
riffa_chnl_if chnl_in,
42,7 → 41,10
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_data_bus_mod: assert(N % 4 == 0) else $fatal;
a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
50,42 → 52,44
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
localparam MI = 2 ** MW; // mux inputs
localparam LB = $clog2(RW);
localparam UB = LB + MW;
localparam RC = RW * B; // number of available registers
 
 
// --------------------------------------------------------------------
//
wire rx_ready = ~reset;
wire rx_done;
wire [31:0] rx_index;
wire [30:0] rx_index;
wire rx_last;
wire [31:0] rx_len;
wire [30:0] rx_off;
wire rx_data_ren;
wire [30:0] rx_off; // offset ignored, always start from offset 0
// wire rx_data_ren;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.*);
riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
 
 
// --------------------------------------------------------------------
//
wire register_select [MI-1:0];
genvar j;
wire register_select [RC-1:0];
genvar j, k;
 
generate
for(j = 0; j < MI; j = j + 1)
begin: decoder_gen
assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;
for(j = 0; j < B; j = j + 1)
begin: register_j_gen
for(k = 0; k < RW; k = k + 1)
begin: register_k_gen
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
 
always_ff @(posedge clk)
if(reset)
r_if.register_out[j] <= 0;
else if(rd_en & register_select[j])
r_if.register_out[j] <= rd_data;
always_ff @(posedge clk)
if(reset)
r_if.register_out[(j*RW) + k] <= 0;
else if(rd_en & register_select[(j*RW) + k])
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
end
end
endgenerate
 
92,7 → 96,7
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_data_ren = rx_data_ren;
// assign chnl_in.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
 
 
100,9 → 104,10
//
wire tx_ready = 1;
wire tx_last = 1;
wire [31:0] tx_len = RW*MI;
wire acked;
wire [31:0] tx_len = RC;
wire [30:0] tx_off = 0;
wire [31:0] tx_index;
wire [30:0] tx_index;
wire tx_done = (tx_index >= chnl_in.tx_len - RW);
 
riffa_chn_tx #(.N(N))
111,12 → 116,27
 
// --------------------------------------------------------------------
//
recursive_mux #(.A(MW), .W(N*8))
wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
 
generate
for(j = 0; j < B; j = j + 1)
begin: data_in_j_gen
for(k = 0; k < RW; k = k + 1)
begin: data_in_k_gen
assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
recursive_mux #(.A($clog2(B)), .W(N*8))
recursive_mux_i
(
.select(tx_index[UB:LB]),
.data_in(r_if.register_in),
.data_out(chnl_in.tx_data)
.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
.data_out(chnl_in.tx_data),
.*
);
 
 
127,9 → 147,9
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = 1;
assign chnl_in.tx_len = RW*MI;
assign chnl_in.tx_len = RC;
assign chnl_in.tx_off = 0;
assign chnl_in.tx_data_valid = 1;
assign chnl_in.tx_data_valid = acked;
 
 
// --------------------------------------------------------------------

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