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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path
    /qaz_libs/trunk/PCIe/src
    from Rev 36 to Rev 37
    Reverse comparison

Rev 36 → Rev 37

/RIFFA/riffa_axis_test_pattern.sv
58,8 → 58,7
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
 
// axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern #(.W(W), .WPB(WPB))
axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern_i(.*);
 
 
/RIFFA/riffa_register_file.sv
82,12 → 82,13
begin: register_j_gen
for(k = 0; k < RW; k = k + 1)
begin: register_k_gen
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
assign r_if.wr_en[(j*RW) + k] = rd_en & register_select[(j*RW) + k];
 
always_ff @(posedge clk)
if(reset)
r_if.register_out[(j*RW) + k] <= 0;
else if(rd_en & register_select[(j*RW) + k])
else if(r_if.wr_en[(j*RW) + k])
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
end
end
102,7 → 103,8
 
// --------------------------------------------------------------------
//
wire tx_ready = 1;
// write to register[0][0] to enable reading
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
/RIFFA/riffa_register_if.sv
39,8 → 39,9
input reset
);
 
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
reg wr_en [RC-1:0];
 
 
// --------------------------------------------------------------------

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