URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/PCIe/src
- from Rev 39 to Rev 42
- ↔ Reverse comparison
Rev 39 → Rev 42
/RIFFA/axis_to_riffa_tx.sv
51,7 → 51,8
// |
wire acked; |
wire [30:0] tx_index; |
wire tx_done = (tx_index >= tx_len - RW) & tx_ready; |
// wire tx_done = (tx_index >= tx_len - RW) & tx_ready; |
wire tx_done = (tx_index >= tx_len - RW); |
|
riffa_chn_tx #(.N(N)) |
riffa_chn_tx_i(.*); |
/RIFFA/riffa_chnl_rx_fsm.sv
68,7 → 68,6
else |
next_state <= IDLE; |
|
// ACK: next_state <= RX; |
ACK: if(rx_ready) |
next_state <= RX; |
else |
/RIFFA/riffa_chnl_tester.sv
0,0 → 1,71
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_tester |
#( |
C_PCI_DATA_WIDTH // Settings from Vivado IP Generator |
) |
( |
riffa_chnl_if chnl_bus, |
input clk, // must be same clock domain as rx_clk & tx_clk |
input reset // must be same clock domain as rx_clk & tx_clk |
); |
|
// -------------------------------------------------------------------- |
// |
chnl_tester #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) |
chnl_tester_i |
( |
.CLK(clk), |
.RST(reset), // riffa_reset includes riffa_endpoint resets |
// Rx interface |
.CHNL_RX_CLK(chnl_bus.rx_clk), |
.CHNL_RX(chnl_bus.rx), |
.CHNL_RX_ACK(chnl_bus.rx_ack), |
.CHNL_RX_LAST(chnl_bus.rx_last), |
.CHNL_RX_LEN(chnl_bus.rx_len), |
.CHNL_RX_OFF(chnl_bus.rx_off), |
.CHNL_RX_DATA(chnl_bus.rx_data), |
.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid), |
.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren), |
// Tx interface |
.CHNL_TX_CLK(chnl_bus.tx_clk), |
.CHNL_TX(chnl_bus.tx), |
.CHNL_TX_ACK(chnl_bus.tx_ack), |
.CHNL_TX_LAST(chnl_bus.tx_last), |
.CHNL_TX_LEN(chnl_bus.tx_len), |
.CHNL_TX_OFF(chnl_bus.tx_off), |
.CHNL_TX_DATA(chnl_bus.tx_data), |
.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid), |
.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren) |
); |
|
// -------------------------------------------------------------------- |
// |
endmodule |
|