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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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    /qaz_libs/trunk/PCIe
    from Rev 33 to Rev 34
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Rev 33 → Rev 34

/sim/src/pcie_monitor_pkg.sv
30,117 → 30,203
//
package pcie_monitor_pkg;
 
// --------------------------------------------------------------------
//
import pcie_common_pkg::*;
typedef enum
{
MRd, // Memory Read Request
MRdLk, // Memory Read Request-Locked
MWr, // Memory Write Request
IORd, // I/O Read Request
IOWr, // I/O Write Request
CfgRd0, // Configuration Read Type
CfgWr0, // Configuration Write Type
CfgRd1, // Configuration Read Type
CfgWr1, // Configuration Write Type
TCfgRd, // Deprecated TLP Type3
TCfgWr, // Deprecated TLP Type3
Msg, // Message Request
MsgD, // Message Request with data payload
Cpl, // Completion without Data
CplD, // Completion with Data
CplLk, // Completion for Locked Memory Read without Data
CplDLk, // Completion for Locked Memory Read
FetchAdd, // Fetch and Add AtomicOp Request
Swap, // Unconditional Swap AtomicOp Request
CAS, // Compare and Swap AtomicOp Request
LPrfx, // Local TLP Prefix
EPrfx, // End-End TLP Prefix
Reserved
} tlp_type_t;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
IMPLICIT
} tlp_routing_t;
 
typedef enum
{
TRANSACTION_UNKNOWN,
REQUESTER,
COMPLETER
} tlp_transaction_t;
 
 
// --------------------------------------------------------------------
//
class tlp_monitor_class;
class base_tlp_packet_class;
 
// tlp_type_t header_type = Reserved;
// tlp_routing_t routing_type = ROUTING_UNKNOWN;
// tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
// logic [7:0] fmt_type;
// logic [2:0] tc;
// logic th;
// logic [2:0] attr;
// logic td;
// logic ep;
// logic [9:0] length;
// logic [7:0] header [16];
// logic header_is_4_dw;
tlp_type_t header_type = Reserved;
tlp_routing_t routing_type = ROUTING_UNKNOWN;
tlp_transaction_t transaction_type = TRANSACTION_UNKNOWN;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
logic [2:0] attr;
logic td;
logic ep;
logic [9:0] length;
logic [7:0] header [16];
logic header_is_4_dw;
 
 
// // --------------------------------------------------------------------
// //
// function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
 
// casez(fmt_type)
// 8'b000_00000: get_tlp_type = MRd;
// 8'b001_00000: get_tlp_type = MRd;
// 8'b000_00001: get_tlp_type = MRdLk;
// 8'b001_00001: get_tlp_type = MRdLk;
// 8'b010_00000: get_tlp_type = MWr;
// 8'b011_00000: get_tlp_type = MWr;
// 8'b000_00010: get_tlp_type = IORd;
// 8'b010_00010: get_tlp_type = IOWr;
// 8'b000_00100: get_tlp_type = CfgRd0;
// 8'b010_00100: get_tlp_type = CfgWr0;
// 8'b000_00101: get_tlp_type = CfgRd1;
// 8'b010_00101: get_tlp_type = CfgWr1;
// 8'b000_11011: get_tlp_type = TCfgRd;
// 8'b010_11011: get_tlp_type = TCfgWr;
// 8'b001_10???: get_tlp_type = Msg;
// 8'b011_10???: get_tlp_type = MsgD;
// 8'b000_01010: get_tlp_type = Cpl;
// 8'b010_01010: get_tlp_type = CplD;
// 8'b000_01011: get_tlp_type = CplLk;
// 8'b010_01011: get_tlp_type = CplDLk;
// 8'b010_01100: get_tlp_type = FetchAdd;
// 8'b011_01100: get_tlp_type = FetchAdd;
// 8'b010_01101: get_tlp_type = Swap;
// 8'b011_01101: get_tlp_type = Swap;
// 8'b010_01110: get_tlp_type = CAS;
// 8'b011_01110: get_tlp_type = CAS;
// 8'b100_0????: get_tlp_type = LPrfx;
// 8'b100_1????: get_tlp_type = EPrfx;
// default: get_tlp_type = Reserved;
// endcase
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
8'b000_00001: get_tlp_type = MRdLk;
8'b001_00001: get_tlp_type = MRdLk;
8'b010_00000: get_tlp_type = MWr;
8'b011_00000: get_tlp_type = MWr;
8'b000_00010: get_tlp_type = IORd;
8'b010_00010: get_tlp_type = IOWr;
8'b000_00100: get_tlp_type = CfgRd0;
8'b010_00100: get_tlp_type = CfgWr0;
8'b000_00101: get_tlp_type = CfgRd1;
8'b010_00101: get_tlp_type = CfgWr1;
8'b000_11011: get_tlp_type = TCfgRd;
8'b010_11011: get_tlp_type = TCfgWr;
8'b001_10???: get_tlp_type = Msg;
8'b011_10???: get_tlp_type = MsgD;
8'b000_01010: get_tlp_type = Cpl;
8'b010_01010: get_tlp_type = CplD;
8'b000_01011: get_tlp_type = CplLk;
8'b010_01011: get_tlp_type = CplDLk;
8'b010_01100: get_tlp_type = FetchAdd;
8'b011_01100: get_tlp_type = FetchAdd;
8'b010_01101: get_tlp_type = Swap;
8'b011_01101: get_tlp_type = Swap;
8'b010_01110: get_tlp_type = CAS;
8'b011_01110: get_tlp_type = CAS;
8'b100_0????: get_tlp_type = LPrfx;
8'b100_1????: get_tlp_type = EPrfx;
default: get_tlp_type = Reserved;
endcase
 
// endfunction: get_tlp_type
endfunction: get_tlp_type
 
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// --------------------------------------------------------------------
//
function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
// MWr: get_tlp_routing = ADDRESS;
// IORd: get_tlp_routing = ADDRESS;
// IOWr: get_tlp_routing = ADDRESS;
// CfgRd0: get_tlp_routing = ID;
// CfgWr0: get_tlp_routing = ID;
// CfgRd1: get_tlp_routing = ID;
// CfgWr1: get_tlp_routing = ID;
// TCfgRd: get_tlp_routing = ID;
// TCfgWr: get_tlp_routing = ID;
// Msg: get_tlp_routing = ROUTING_UNKNOWN;
// MsgD: get_tlp_routing = ROUTING_UNKNOWN;
// Cpl: get_tlp_routing = ID;
// CplD: get_tlp_routing = ID;
// CplLk: get_tlp_routing = ID;
// CplDLk: get_tlp_routing = ID;
// FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
// Swap: get_tlp_routing = ROUTING_UNKNOWN;
// CAS: get_tlp_routing = ROUTING_UNKNOWN;
// LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
// default: get_tlp_routing = ROUTING_UNKNOWN;
// endcase
case(tlp_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
IORd: get_tlp_routing = ADDRESS;
IOWr: get_tlp_routing = ADDRESS;
CfgRd0: get_tlp_routing = ID;
CfgWr0: get_tlp_routing = ID;
CfgRd1: get_tlp_routing = ID;
CfgWr1: get_tlp_routing = ID;
TCfgRd: get_tlp_routing = ID;
TCfgWr: get_tlp_routing = ID;
Msg: get_tlp_routing = ROUTING_UNKNOWN;
MsgD: get_tlp_routing = ROUTING_UNKNOWN;
Cpl: get_tlp_routing = ID;
CplD: get_tlp_routing = ID;
CplLk: get_tlp_routing = ID;
CplDLk: get_tlp_routing = ID;
FetchAdd: get_tlp_routing = ROUTING_UNKNOWN;
Swap: get_tlp_routing = ROUTING_UNKNOWN;
CAS: get_tlp_routing = ROUTING_UNKNOWN;
LPrfx: get_tlp_routing = ROUTING_UNKNOWN;
EPrfx: get_tlp_routing = ROUTING_UNKNOWN;
default: get_tlp_routing = ROUTING_UNKNOWN;
endcase
 
// endfunction: get_tlp_routing
endfunction: get_tlp_routing
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// --------------------------------------------------------------------
//
function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
// case(tlp_type)
case(tlp_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
IORd: get_tlp_transaction = REQUESTER;
IOWr: get_tlp_transaction = REQUESTER;
CfgRd0: get_tlp_transaction = REQUESTER;
CfgWr0: get_tlp_transaction = REQUESTER;
CfgRd1: get_tlp_transaction = REQUESTER;
CfgWr1: get_tlp_transaction = REQUESTER;
TCfgRd: get_tlp_transaction = REQUESTER;
TCfgWr: get_tlp_transaction = REQUESTER;
Msg: get_tlp_transaction = REQUESTER;
MsgD: get_tlp_transaction = REQUESTER;
Cpl: get_tlp_transaction = COMPLETER;
CplD: get_tlp_transaction = COMPLETER;
CplLk: get_tlp_transaction = COMPLETER;
CplDLk: get_tlp_transaction = COMPLETER;
FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
default: get_tlp_transaction = TRANSACTION_UNKNOWN;
endcase
 
endfunction: get_tlp_transaction
// --------------------------------------------------------------------
//
function void display_tlp_cfg(tlp_type_t tlp_type);
logic [5:0] Register_Number = header[11][7:2];
logic [3:0] Extended_Register_Number = header[10][3:0];
// $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
$display("??? %16.t | config offset = 0x%5.x",
$time, {Extended_Register_Number, Register_Number, 2'b00});
endfunction: display_tlp_cfg
// --------------------------------------------------------------------
//
function void display_tlp_type(tlp_type_t tlp_type);
case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
// MWr: get_tlp_transaction = REQUESTER;
// IORd: get_tlp_transaction = REQUESTER;
// IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: get_tlp_transaction = REQUESTER;
// CfgWr0: get_tlp_transaction = REQUESTER;
// CfgRd1: get_tlp_transaction = REQUESTER;
// CfgWr1: get_tlp_transaction = REQUESTER;
// TCfgRd: get_tlp_transaction = REQUESTER;
// TCfgWr: get_tlp_transaction = REQUESTER;
CfgRd0: display_tlp_cfg(tlp_type);
CfgWr0: display_tlp_cfg(tlp_type);
CfgRd1: display_tlp_cfg(tlp_type);
CfgWr1: display_tlp_cfg(tlp_type);
TCfgRd: display_tlp_cfg(tlp_type);
TCfgWr: display_tlp_cfg(tlp_type);
// Msg: get_tlp_transaction = REQUESTER;
// MsgD: get_tlp_transaction = REQUESTER;
// Cpl: get_tlp_transaction = COMPLETER;
152,134 → 238,86
// CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: get_tlp_transaction = TRANSACTION_UNKNOWN;
// endcase
default: return;
endcase
 
// endfunction: get_tlp_transaction
endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_header_class hd_h);
// logic [5:0] Register_Number = hd_h.header[11][7:2];
// logic [3:0] Extended_Register_Number = hd_h.header[10][3:0];
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
// endfunction: display_tlp_cfg
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
// // MWr: get_tlp_transaction = REQUESTER;
// // IORd: get_tlp_transaction = REQUESTER;
// // IOWr: get_tlp_transaction = REQUESTER;
// CfgRd0: display_tlp_cfg(tlp_type);
// CfgWr0: display_tlp_cfg(tlp_type);
// CfgRd1: display_tlp_cfg(tlp_type);
// CfgWr1: display_tlp_cfg(tlp_type);
// TCfgRd: display_tlp_cfg(tlp_type);
// TCfgWr: display_tlp_cfg(tlp_type);
// // Msg: get_tlp_transaction = REQUESTER;
// // MsgD: get_tlp_transaction = REQUESTER;
// // Cpl: get_tlp_transaction = COMPLETER;
// // CplD: get_tlp_transaction = COMPLETER;
// // CplLk: get_tlp_transaction = COMPLETER;
// // CplDLk: get_tlp_transaction = COMPLETER;
// // FetchAdd: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // Swap: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // CAS: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // LPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// // EPrfx: get_tlp_transaction = TRANSACTION_UNKNOWN;
// default: return;
// endcase
// --------------------------------------------------------------------
//
function void set_little_endian_header( logic [127:0] data);
 
// endfunction: display_tlp_type
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
logic [2:0] fmt = data[7:5];
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
// $stop;
// end
if(fmt > 3'b011)
begin
$display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
$stop;
end
 
// header_is_4_dw = data[5];
header_is_4_dw = data[5];
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
{header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
header_type = get_tlp_type(header[0]);
routing_type = get_tlp_routing(header_type);
transaction_type = get_tlp_transaction(header_type);
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
// attr = {header[1][2], header[2][5:4]};
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
fmt_type = header[0];
tc = header[1][6:4];
th = header[1][0];
attr = {header[1][2], header[2][5:4]};
td = header[2][7];
ep = header[2][6];
length = {header[2][1:0], header[3]};
// endfunction: set_little_endian_header
endfunction: set_little_endian_header
 
 
// // --------------------------------------------------------------------
// //
// function void display_header(string str);
// --------------------------------------------------------------------
//
function void display_header(string str);
 
// $display("??? %16.t | .....................", $time);
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
$time, tc, th, attr, td, ep);
 
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
if(routing_type == ADDRESS)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
else
$display("??? %16.t | address[31:0] = 0x%8.x", $time,
{ header[8], header[9], header[10], header[11][7:2], 2'b00});
else if(routing_type == ID)
$display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
header[8], header[9][7:3], header[9][2:0]);
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
// $display("??? %16.t | tag = %b", $time, header[10]);
// end
// else
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
if(transaction_type == COMPLETER)
begin
$display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | requester ID = %b", $time, {header[8], header[9]});
$display("??? %16.t | tag = %b", $time, header[10]);
end
else
begin
$display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
$display("??? %16.t | tag = %b", $time, header[6]);
$display("??? %16.t | last DW BE = %b | first DW BE = %b",
$time, header[7][7:4], header[7][3:0]);
end
// display_tlp_type(header_type);
display_tlp_type(header_type);
// $display("??? %16.t | ---------------------", $time);
$display("??? %16.t | ---------------------", $time);
 
// endfunction: display_header
endfunction: display_header
 
 
// //--------------------------------------------------------------------
291,7 → 329,7
 
// --------------------------------------------------------------------
//
endclass: tlp_monitor_class
endclass: base_tlp_packet_class
 
 
// --------------------------------------------------------------------
/sim/tests/tb_riffa_axis_test_pattern/init_test.do
0,0 → 1,36
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_axis_test_pattern
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_lib $env(LIB_BASE_DIR) tb_packages
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/sim/tests/tb_riffa_axis_test_pattern/sim.do
0,0 → 1,11
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
 
/sim/tests/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern.f
0,0 → 1,18
#
 
${LIB_BASE_DIR}/PCIe/sim/src/riffa_bfm_class_pkg.sv
${LIB_BASE_DIR}/PCIe/sim/src/riffa_agent_class_pkg.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_if.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_register_if.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_tx_fsm.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_tx.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_rx_fsm.sv
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_chnl_rx.sv
 
${LIB_BASE_DIR}/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
 
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_test_patern.sv
 
 
/sim/tests/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern.sv
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
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//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire clk = tb_clk;
wire reset;
wire aclk = clk;
wire aresetn = ~reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
 
// --------------------------------------------------------------------
//
import tb_riffa_axis_test_pattern_pkg::*;
 
 
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
 
 
// --------------------------------------------------------------------
//
wire [31:0] tx_len = TX_L;
 
riffa_axis_test_pattern #(.N(N))
dut(.*);
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
tb_riffa_axis_test_pattern_class #(.N(N)) a_h;
 
initial
a_h = new(chnl_in);
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/sim/tests/tb_riffa_axis_test_pattern/tb_riffa_axis_test_pattern_pkg.sv
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_riffa_axis_test_pattern_pkg;
 
// --------------------------------------------------------------------
//
import riffa_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam N = 16; // RIFFA bus width in bytes
localparam I = 0; // TID width
localparam D = 0; // TDEST width
localparam U = 3; // TUSER width
localparam TX_L = 256 * 256; // RIFFA tx length
 
 
// --------------------------------------------------------------------
//
class tb_riffa_axis_test_pattern_class #(N)
extends riffa_agent_class #(.N(N));
 
 
//--------------------------------------------------------------------
//
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus);
 
super.new(chnl_bus);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_riffa_axis_test_pattern_class
 
 
// --------------------------------------------------------------------
//
endpackage: tb_riffa_axis_test_pattern_pkg
 
 
 
 
 
/sim/tests/tb_riffa_axis_test_pattern/the_test.sv
0,0 → 1,93
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module the_test(input tb_clk, input tb_rst);
 
// --------------------------------------------------------------------
//
import tb_riffa_axis_test_pattern_pkg::*;
import riffa_agent_class_pkg::*;
import riffa_bfm_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(500us);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(TX_L, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
#1us;
 
// // --------------------------------------------------------------------
// $display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.q.num());
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/sim/tests/tb_riffa_register_file/tb_riffa_register_file.sv
53,12 → 53,12
// --------------------------------------------------------------------
//
riffa_chnl_if #(.N(N)) chnl_in(.*);
riffa_register_if #(.N(N), .MW(MW)) r_if(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
// --------------------------------------------------------------------
//
riffa_register_file #(.A(A), .N(N), .MW(MW))
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
 
70,7 → 70,7
 
// --------------------------------------------------------------------
//
for(genvar j = 0; j < MI; j++)
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
 
/sim/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
35,11 → 35,9
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 16; // width of the bus in bytes
localparam MW = 3; // mux select width
localparam MI = 2 ** MW; // mux inputs
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
 
// --------------------------------------------------------------------
/sim/tests/tb_riffa_register_file/the_test.sv
59,7 → 59,7
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_tx_random(RW*MI, 0, 1);
tb_top.a_h.queue_tx_random(RW*B, 0, 1);
tb_top.a_h.wait_for_tx();
 
// --------------------------------------------------------------------
66,7 → 66,7
#200ns;
 
// --------------------------------------------------------------------
tb_top.a_h.queue_rx(RW*MI, 0, 1);
tb_top.a_h.queue_rx(RW*B, 0, 1);
tb_top.a_h.wait_for_rx();
 
// --------------------------------------------------------------------
/src/RIFFA/riffa_axis_test_pattern.sv
0,0 → 1,101
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
riffa_axis_test_pattern
#(
N, // RIFFA data bus width in bytes
W = 4, // word width in bytes
WPB = N / W // number of words per beat
)
(
riffa_chnl_if chnl_in,
input [31:0] tx_len,
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
localparam I = 0; // TID width
localparam D = 0; // TDEST width
localparam U = 3; // TUSER width
localparam RW = (N/4); // width of the RIFFA bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
wire aclk = clk;
wire aresetn = ~reset;
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
 
axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern_i(.*);
 
 
// --------------------------------------------------------------------
//
wire tx_ready = 1;
wire tx_last = 1;
wire acked;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire tx_done = (tx_index >= tx_len - RW);
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axis_out.tready = chnl_in.tx_data_ren & acked;
 
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = tx_last;
assign chnl_in.tx_len = tx_len;
assign chnl_in.tx_off = tx_off;
assign chnl_in.tx_data_valid = axis_out.tvalid & acked;
assign chnl_in.tx_data = axis_out.tdata;
 
// --------------------------------------------------------------------
//
endmodule
 
 
 
 
/src/RIFFA/riffa_chnl_rx.sv
33,7 → 33,7
(
riffa_chnl_if chnl_in,
output rx_done,
output reg [31:0] rx_index,
output reg [30:0] rx_index,
output reg rx_last,
output reg [31:0] rx_len,
output reg [30:0] rx_off,
48,11 → 48,6
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
riffa_chnl_rx_fsm
riffa_chnl_rx_fsm_i
(
90,7 → 85,7
if(reset | rx_done)
rx_index = 0;
else if(rd_en)
rx_index <= rx_index + RW;
rx_index <= rx_index + (N/4); // increment by 32 bit words
 
 
// --------------------------------------------------------------------
/src/RIFFA/riffa_chnl_tx.sv
28,14 → 28,14
module
riffa_chn_tx
#(
N, // data bus width in bytes
D = 2 // TX data fifo depth
N // data bus width in bytes
)
(
riffa_chnl_if chnl_in,
input tx_ready,
input tx_done,
output reg [31:0] tx_index,
output acked,
output reg [30:0] tx_index,
input tx_last,
input [31:0] tx_len,
input [30:0] tx_off,
45,12 → 45,7
);
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
//
riffa_chnl_tx_fsm
riffa_chnl_tx_fsm_i
(
63,10 → 58,10
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | ~chnl_in.tx)
if(reset | ~chnl_in.tx | tx_done)
tx_index = 0;
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
tx_index <= tx_index + RW;
tx_index <= tx_index + (N/4); // increment by 32 bit words
 
 
// --------------------------------------------------------------------
/src/RIFFA/riffa_chnl_tx_fsm.sv
30,6 → 30,7
(
input tx_ready,
output tx,
output acked,
input tx_ack,
input tx_done,
 
85,7 → 86,8
 
// --------------------------------------------------------------------
//
assign tx = (state == ACK) | (state == TX);
assign tx = (state == ACK) | (state == TX);
assign acked = (state == TX) | (next_state == TX);
 
 
// --------------------------------------------------------------------
/src/RIFFA/riffa_register_file.sv
28,7 → 28,7
module
riffa_register_file
#(
// A, // address bus width
A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
)
/src/RIFFA/riffa_register_if.sv
30,8 → 30,9
riffa_register_if
#(
N, // data bus width in bytes
MW, // mux select width
MI = 2 ** MW // mux inputs
B, // number of register banks
RW = (N/4), // width of the bus in 32 bit words
RC = RW * B // number of available registers
)
(
input clk,
38,8 → 39,8
input reset
);
 
wire [(N*8)-1:0] register_in [MI-1:0];
reg [(N*8)-1:0] register_out [MI-1:0];
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
 
 
// --------------------------------------------------------------------

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