URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/avalon_lib/sim/tests
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/tb_ast_monitor/init_test.do
0,0 → 1,36
# ------------------------------------ |
# |
# ------------------------------------ |
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global env |
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# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_ast_monitor |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) avalon_lib |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
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# compile simulation files |
vlog -f ./$env(SIM_TB).f |
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# simulation $root |
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./$env(SIM_TB).sv |
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# compile test last |
vlog ./the_test.sv |
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# run the sim |
sim_run_test |
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/tb_ast_monitor/sim.do
0,0 → 1,11
# |
# |
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quit -sim |
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vsim -novopt work.tb_top |
# vsim -f ./sim.f work.tb_top |
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# log all signals |
# log -r * |
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/tb_ast_monitor/tb_ast_monitor.f
0,0 → 1,8
# |
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${PROJECT_DIR}/src/ast_if.sv |
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${PROJECT_DIR}/sim/src/ast_monitor.sv |
${PROJECT_DIR}/sim/src/ast_sink.sv |
${PROJECT_DIR}/sim/src/ast_source.sv |
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/tb_ast_monitor/tb_ast_monitor.sv
0,0 → 1,162
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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module tb_top(); |
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// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
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tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
wire tb_rst_s; |
wire clk = tb_clk; |
wire reset = tb_rst_s; |
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sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); |
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// -------------------------------------------------------------------- |
// |
import tb_ast_monitor_pkg::*; |
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// -------------------------------------------------------------------- |
// |
ast_if #(EW, CW, SW, NSW) src(.*); |
ast_if #(EW, CW, SW, NSW) sink(.*); |
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// -------------------------------------------------------------------- |
// |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
ast_monitor |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_monitor_i(.sink(src), .src(sink), .*); |
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// -------------------------------------------------------------------- |
// |
ast_source |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_source_i(.*); |
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// -------------------------------------------------------------------- |
// |
ast_sink |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_sink_i(.*); |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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/tb_ast_monitor/tb_ast_monitor_pkg.sv
0,0 → 1,69
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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package tb_ast_monitor_pkg; |
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// -------------------------------------------------------------------- |
// |
localparam EW = 1; |
localparam CW = 1; |
localparam SW = 8; |
localparam NSW = 4; |
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localparam ST_SYMBOL_W = SW; |
localparam ST_NUMSYMBOLS = NSW; |
localparam USE_PACKET = 1; |
localparam ST_READY_LATENCY = 3; |
localparam USE_CHANNEL = 0; |
localparam USE_ERROR = 0; |
localparam USE_READY = 1; |
localparam USE_VALID = 1; |
localparam USE_EMPTY = 1; |
localparam ST_ERROR_W = EW; |
localparam ST_MAX_PACKET_SIZE = 1; |
localparam ST_MAX_CHANNELS = 0; |
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// -------------------------------------------------------------------- |
// |
class tb_ast_monitor_class; |
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// -------------------------------------------------------------------- |
// |
endclass: tb_ast_monitor_class |
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// -------------------------------------------------------------------- |
// |
endpackage: tb_ast_monitor_pkg |
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/tb_ast_monitor/the_test.sv
0,0 → 1,102
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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`timescale 1ps/1ps |
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module the_test(input tb_clk, input tb_rst); |
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// -------------------------------------------------------------------- |
// |
import verbosity_pkg::*; |
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// -------------------------------------------------------------------- |
// |
task run_the_test; |
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// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
tb_top.tb.timeout_stop(50us); |
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// -------------------------------------------------------------------- |
// set_verbosity(VERBOSITY_DEBUG); |
tb_top.ast_source_i.st_source_bfm_i.init(); |
tb_top.ast_sink_i.st_sink_bfm_i.init(); |
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// -------------------------------------------------------------------- |
wait(~tb_rst); |
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// -------------------------------------------------------------------- |
#200ns; |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(1); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
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tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(1); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
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tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(2); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(1); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
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// -------------------------------------------------------------------- |
#200ns; |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
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// -------------------------------------------------------------------- |
#1us; |
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
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endtask |
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// -------------------------------------------------------------------- |
// |
endmodule |
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