URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/avalon_lib/src
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/ast_if.sv
0,0 → 1,57
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
interface |
ast_if |
#( |
EW = 1, // error signal width in bits. |
CW = 1, // channel width in bits. |
SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces. |
NSW, // Numbers of symbols per word |
NSW_L = (NSW == 1) ? 1 : $clog2(NSW) |
) |
( |
input reset, |
input clk |
); |
|
wire [(SW*NSW)-1:0] data; |
wire valid; |
wire ready; |
wire startofpacket; |
wire endofpacket; |
wire [NSW_L-1:0] empty; |
wire [CW-1:0] channel; |
wire [EW-1:0] error; |
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// -------------------------------------------------------------------- |
// |
endinterface |
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/ast_ready_cycle_fsm.sv
0,0 → 1,106
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
ast_ready_cycle_fsm |
( |
input axis_en, |
output axis_tvalid, |
input axis_tready, |
|
input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also |
input fifo_empty, |
output fifo_rd_en, |
|
output data_to_axis_fsm_error, |
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input aclk, |
input aresetn |
); |
|
//--------------------------------------------------- |
// state machine binary definitions |
enum reg [3:0] { |
IDLE_STATE = 4'b0001, |
TVALID = 4'b0010, |
TREADY = 4'b0100, |
ERROR_STATE = 4'b1000 |
} state, next_state; |
|
|
//--------------------------------------------------- |
// state machine flop |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= IDLE_STATE; |
else |
state <= next_state; |
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//--------------------------------------------------- |
// state machine |
always_comb |
case(state) |
IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) |
if(axis_tready) |
next_state <= TREADY; |
else |
next_state <= TVALID; |
else |
next_state <= IDLE_STATE; |
|
TVALID: if(axis_tready) // wait for slave to be ready |
next_state <= TREADY; |
else |
next_state <= TVALID; |
|
TREADY: if(fifo_empty) // slave can accept data |
next_state <= IDLE_STATE; |
else if(axis_tready) |
next_state <= TREADY; |
else |
next_state <= TVALID; |
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ERROR_STATE: next_state <= IDLE_STATE; |
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default: next_state <= ERROR_STATE; |
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endcase |
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//--------------------------------------------------- |
// outputs |
assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); |
assign fifo_rd_en = axis_tvalid & axis_tready; |
assign data_to_axis_fsm_error = (state == ERROR_STATE); |
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//--------------------------------------------------- |
// |
endmodule |
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