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/docs/mnl_avalon_spec_1_3.pdf
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docs/mnl_avalon_spec_1_3.pdf
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Index: src/fifo_to_ast.sv
===================================================================
--- src/fifo_to_ast.sv (nonexistent)
+++ src/fifo_to_ast.sv (revision 35)
@@ -0,0 +1,109 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module
+ fifo_to_ast
+ #(
+ READYLATENCY,
+ EW = 1, // error signal width in bits.
+ CW = 1, // channel width in bits.
+ SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces.
+ NSB, // Numbers of symbols per beat
+ NSB_L = (NSB == 1) ? 1 : $clog2(NSB), // empty width
+ D = 2,
+ UB = $clog2(D)
+ )
+ (
+ output wr_full,
+ input wr_en,
+
+ ast_if ast_in,
+ ast_if ast_out,
+ input clk,
+ input reset
+ );
+
+ // --------------------------------------------------------------------
+ //
+ reg [READYLATENCY:0] ready_r;
+ wire ready_cycle = ready_r[READYLATENCY];
+
+ always_ff @(posedge clk)
+ if(reset)
+ ready_r <= 0;
+ else
+ ready_r <= {ready_r[READYLATENCY-1:0], ast_out.ready};
+
+
+ // --------------------------------------------------------------------
+ //
+ localparam FW = (SW*NSB) + 1 + 1 + NSB_L + CW + EW;
+
+
+ // --------------------------------------------------------------------
+ //
+ wire [FW-1:0] wr_data =
+ { ast_in.channel
+ , ast_in.error
+ , ast_in.data
+ , ast_in.empty
+ , ast_in.endofpacket
+ , ast_in.startofpacket
+ };
+
+ wire [FW-1:0] rd_data;
+ assign { ast_out.channel
+ , ast_out.error
+ , ast_out.data
+ , ast_out.empty
+ , ast_out.endofpacket
+ , ast_out.startofpacket
+ } = rd_data;
+
+
+ // --------------------------------------------------------------------
+ //
+ wire rd_empty;
+ wire rd_en = ready_cycle & ~rd_empty;
+ wire [UB:0] count;
+
+
+ sync_fifo #(.W(FW), .D(D))
+ sync_fifo_i(.*);
+
+
+ // --------------------------------------------------------------------
+ //
+ assign ast_out.valid = rd_en;
+
+
+// --------------------------------------------------------------------
+//
+endmodule
+
+