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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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    /qaz_libs/trunk/axi4_lib/src
    from Rev 29 to Rev 31
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  •

Rev 29 → Rev 31

/axi4_if.sv
38,51 → 38,273
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
wire [(A-1):0] araddr;
wire [1:0] arburst;
wire [3:0] arcache;
wire [(I-1):0] arid;
wire [7:0] arlen;
wire arlock;
wire [2:0] arprot;
wire [3:0] arqos;
wire arready;
wire [3:0] arregion;
wire [2:0] arsize;
wire arvalid;
wire [(A-1):0] awaddr;
wire [1:0] awburst;
wire [3:0] awcache;
wire [(I-1):0] awid;
wire [7:0] awlen;
wire awlock;
wire [2:0] awprot;
wire [3:0] awqos;
wire awready;
wire [3:0] awregion;
wire [2:0] awsize;
wire awvalid;
wire [(I-1):0] bid;
wire bready;
wire [1:0] bresp;
wire bvalid;
wire [(8*N)-1:0] rdata;
wire [(I-1):0] rid;
wire rlast;
wire rready;
wire [1:0] rresp;
wire rvalid;
wire [(8*N)-1:0] wdata;
wire [(I-1):0] wid;
wire wlast;
wire wready;
wire [N-1:0] wstrb;
wire wvalid;
 
 
// --------------------------------------------------------------------
// synthesis translate_off
clocking cb_s @(posedge aclk);
input arid;
input araddr;
input arburst;
input arcache;
input awid;
input arlen;
input arlock;
input arprot;
input arqos;
output arready;
input arregion;
input arsize;
input arvalid;
input awaddr;
input awburst;
input awcache;
input awlen;
input awlock;
input awprot;
input awqos;
output awready;
input awregion;
input awsize;
input awvalid;
input bready;
output bid;
output bresp;
output bvalid;
output rdata;
output rid;
output rlast;
input rready;
output rresp;
output rvalid;
input wdata;
input wid;
input wlast;
output wready;
input wstrb;
input wvalid;
input aresetn;
input aclk;
endclocking
 
 
// --------------------------------------------------------------------
//
default clocking cb_m @(posedge aclk);
output arid;
output araddr;
output arburst;
output arcache;
output awid;
output arlen;
output arlock;
output arprot;
output arqos;
input arready;
output arregion;
output arsize;
output arvalid;
output awaddr;
output awburst;
output awcache;
output awlen;
output awlock;
output awprot;
output awqos;
input awready;
output awregion;
output awsize;
output awvalid;
output bready;
input bid;
input bresp;
input bvalid;
input rdata;
input rid;
input rlast;
output rready;
input rresp;
input rvalid;
output wdata;
output wid;
output wlast;
input wready;
output wstrb;
output wvalid;
input aresetn;
input aclk;
endclocking
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
`ifdef USE_MOD_PORTS
// --------------------------------------------------------------------
//
modport
slave
(
// --------------------------------------------------------------------
// synthesis translate_off
clocking cb_s,
// synthesis translate_on
// --------------------------------------------------------------------
input arid,
input araddr,
input arburst,
input arcache,
input awid,
input arlen,
input arlock,
input arprot,
input arqos,
output arready,
input arregion,
input arsize,
input arvalid,
input awaddr,
input awburst,
input awcache,
input awlen,
input awlock,
input awprot,
input awqos,
output awready,
input awregion,
input awsize,
input awvalid,
input bready,
output bid,
output bresp,
output bvalid,
output rdata,
output rid,
output rlast,
input rready,
output rresp,
output rvalid,
input wdata,
input wid,
input wlast,
output wready,
input wstrb,
input wvalid,
input aresetn,
input aclk
);
 
 
// --------------------------------------------------------------------
//
modport
master
(
// --------------------------------------------------------------------
// synthesis translate_off
clocking cb_m,
// synthesis translate_on
// --------------------------------------------------------------------
output arid,
output araddr,
output arburst,
output arcache,
output awid,
output arlen,
output arlock,
output arprot,
output arqos,
input arready,
output arregion,
output arsize,
output arvalid,
output awaddr,
output awburst,
output awcache,
output awlen,
output awlock,
output awprot,
output awqos,
input awready,
output awregion,
output awsize,
output awvalid,
output bready,
input bid,
input bresp,
input bvalid,
input rdata,
input rid,
input rlast,
output rready,
input rresp,
input rvalid,
output wdata,
output wlast,
input wready,
output wstrb,
output wvalid,
input aresetn,
input aclk
);
`endif
 
 
// --------------------------------------------------------------------
// synthesis translate_off
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/axi4_m_to_read_fifos.sv
0,0 → 1,253
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_m_to_read_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
R_D = 32,
AR_D = 2,
WATERMARK = 0,
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_m,
axi4_if axi4_read_fifo,
 
output ar_wr_full,
input ar_wr_en,
output r_rd_empty,
input r_rd_en,
output r_topped_off,
output r_watermark,
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam UB = $clog2(R_D);
 
 
// --------------------------------------------------------------------
//
localparam R_W =
8*N + // logic [(8*N)-1:0] rdata;
I + // logic [(I-1):0] rid;
1 + // logic rlast;
2; // logic [1:0] rresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AR_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AR_W-1:0] ar_rd_data;
wire [AR_W-1:0] ar_wr_data;
 
generate
begin: ar_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign ar_wr_data =
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize,
axi4_read_fifo.arcache,
axi4_read_fifo.arlock,
axi4_read_fifo.arprot,
axi4_read_fifo.arqos,
axi4_read_fifo.arregion
};
 
assign
{
axi4_m.araddr,
axi4_m.arburst,
axi4_m.arid,
axi4_m.arlen,
axi4_m.arsize,
axi4_m.arcache,
axi4_m.arlock,
axi4_m.arprot,
axi4_m.arqos,
axi4_m.arregion
} = ar_rd_data;
end
else
begin
assign ar_wr_data =
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize
};
 
assign axi4_read_fifo.arcache = 0;
assign axi4_read_fifo.arlock = 0;
assign axi4_read_fifo.arprot = 0;
assign axi4_read_fifo.arqos = 0;
assign axi4_read_fifo.arregion = 0;
 
assign
{
axi4_m.araddr,
axi4_m.arburst,
axi4_m.arid,
axi4_m.arlen,
axi4_m.arsize
} = ar_rd_data;
 
assign axi4_m.arcache = 0;
assign axi4_m.arlock = 0;
assign axi4_m.arprot = 0;
assign axi4_m.arqos = 0;
assign axi4_m.arregion = 0;
 
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire ar_rd_empty;
wire ar_rd_en = axi4_m.arready & axi4_m.arvalid;
assign axi4_m.arvalid = ~ar_rd_empty;
 
sync_fifo #(.W(AR_W), .D(AR_D))
ar_fifo
(
.wr_full(ar_wr_full),
.wr_data(ar_wr_data),
.wr_en(ar_wr_en),
.rd_empty(ar_rd_empty),
.rd_data(ar_rd_data),
.rd_en(ar_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [R_W-1:0] r_rd_data;
wire [R_W-1:0] r_wr_data;
 
assign r_wr_data =
{
axi4_m.rdata,
axi4_m.rid,
axi4_m.rlast,
axi4_m.rresp
};
 
assign
{
axi4_read_fifo.rdata,
axi4_read_fifo.rid,
axi4_read_fifo.rlast,
axi4_read_fifo.rresp
} = r_rd_data;
 
 
// --------------------------------------------------------------------
//
wire [UB:0] r_count;
 
generate
begin: r_watermark_gen
if(WATERMARK == 0)
begin
assign r_topped_off = 1;
assign r_watermark = 0;
end
else
begin
reg r_topped_off_r;
assign r_topped_off = r_topped_off_r;
assign r_watermark = r_count > WATERMARK - 1;
 
always_ff @(posedge aclk)
if(~aresetn | r_rd_empty)
r_topped_off_r <= 0;
else if(r_watermark)
r_topped_off_r <= 1;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire r_wr_full;
wire r_wr_en = axi4_m.rready & axi4_m.rvalid;
assign axi4_m.rready = ~r_wr_full;
 
sync_fifo #(.W(R_W), .D(R_D))
r_fifo
(
.wr_full(r_wr_full),
.wr_data(r_wr_data),
.wr_en(r_wr_en),
.rd_empty(r_rd_empty),
.rd_data(r_rd_data),
.rd_en(r_rd_en),
.count(r_count),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/axi4_m_to_write_fifos.sv
0,0 → 1,282
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_m_to_write_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
W_D = 32,
B_D = 2,
AW_D = 2,
WATERMARK = 0,
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_m,
axi4_if axi4_write_fifo,
output aw_wr_full,
input aw_wr_en,
output w_wr_full,
input w_wr_en,
output w_topped_off,
output w_watermark,
output b_rd_empty,
input b_rd_en,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam UB = $clog2(W_D);
 
 
// --------------------------------------------------------------------
//
localparam W_W =
8*N + // logic [(8*N)-1:0] wdata;
I + // logic [(I-1):0] wid;
1 + // logic wlast;
N; // logic [N-1:0] wstrb;
 
localparam B_W =
I + // logic [(I-1):0] bid;
2; // logic [1:0] bresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AW_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AW_W-1:0] aw_rd_data;
wire [AW_W-1:0] aw_wr_data;
 
generate
begin: aw_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign aw_wr_data =
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize,
axi4_write_fifo.awcache,
axi4_write_fifo.awlock,
axi4_write_fifo.awprot,
axi4_write_fifo.awqos,
axi4_write_fifo.awregion
};
 
assign
{
axi4_m.awaddr,
axi4_m.awburst,
axi4_m.awid,
axi4_m.awlen,
axi4_m.awsize,
axi4_m.awcache,
axi4_m.awlock,
axi4_m.awprot,
axi4_m.awqos,
axi4_m.awregion
} = aw_rd_data;
end
else
begin
assign aw_wr_data =
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize
};
 
assign
{
axi4_m.awaddr,
axi4_m.awburst,
axi4_m.awid,
axi4_m.awlen,
axi4_m.awsize
} = aw_rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire aw_rd_empty;
wire aw_rd_en = axi4_m.awready & axi4_m.awvalid;
assign axi4_m.awvalid = ~aw_rd_empty;
 
sync_fifo #(.W(AW_W), .D(AW_D))
aw_fifo
(
.wr_full(aw_wr_full),
.wr_data(aw_wr_data),
.wr_en(aw_wr_en),
.rd_empty(aw_rd_empty),
.rd_data(aw_rd_data),
.rd_en(aw_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [W_W-1:0] w_rd_data;
wire [W_W-1:0] w_wr_data;
 
assign w_wr_data =
{
axi4_write_fifo.wdata,
axi4_write_fifo.wid,
axi4_write_fifo.wlast,
axi4_write_fifo.wstrb
};
 
assign
{
axi4_m.wdata,
axi4_m.wid,
axi4_m.wlast,
axi4_m.wstrb
} = w_rd_data;
 
 
// --------------------------------------------------------------------
//
wire [UB:0] w_count;
wire w_rd_empty;
wire w_rd_en = axi4_m.wready & axi4_m.wvalid;
assign axi4_m.wvalid = ~w_rd_empty;
 
sync_fifo #(.W(W_W), .D(W_D))
w_fifo
(
.wr_full(w_wr_full),
.wr_data(w_wr_data),
.wr_en(w_wr_en),
.rd_empty(w_rd_empty),
.rd_data(w_rd_data),
.rd_en(w_rd_en),
.count(w_count),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
generate
begin: w_watermark_gen
if(WATERMARK == 0)
begin
assign w_topped_off = 1;
assign w_watermark = 0;
end
else
begin
reg w_topped_off_r;
assign w_topped_off = w_topped_off_r;
assign w_watermark = w_count > WATERMARK - 1;
 
always_ff @(posedge aclk)
if(~aresetn | w_rd_empty)
w_topped_off_r <= 0;
else if(w_watermark)
w_topped_off_r <= 1;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire [B_W-1:0] b_rd_data;
wire [B_W-1:0] b_wr_data;
 
assign b_wr_data =
{
axi4_m.bid,
axi4_m.bresp
};
 
assign
{
axi4_write_fifo.bid,
axi4_write_fifo.bresp
} = b_rd_data;
 
 
// --------------------------------------------------------------------
//
wire b_wr_full;
wire b_wr_en = axi4_m.bready & axi4_m.bvalid;
assign axi4_m.bready = ~b_wr_full;
 
sync_fifo #(.W(B_W), .D(B_D))
b_fifo
(
.wr_full(b_wr_full),
.wr_data(b_wr_data),
.wr_en(b_wr_en),
.rd_empty(b_rd_empty),
.rd_data(b_rd_data),
.rd_en(b_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
endmodule
 
/axi4_register_slice.sv
53,14 → 53,16
 
// --------------------------------------------------------------------
//
axi4_to_read_fifos
axi4_s_to_read_fifos
#(
.A(A),
.N(N),
.I(I),
.R_D(2),
.AR_D(2),
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
)
axi4_to_read_fifos_i(.*);
axi4_s_to_read_fifos_i(.*);
 
 
// --------------------------------------------------------------------
118,14 → 120,17
 
// --------------------------------------------------------------------
//
axi4_to_write_fifos
axi4_s_to_write_fifos
#(
.A(A),
.N(N),
.I(I),
.W_D(2),
.B_D(2),
.AW_D(2),
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
)
axi4_to_write_fifos_i(.*);
axi4_s_to_write_fifos_i(.*);
 
 
// --------------------------------------------------------------------
/axi4_s_to_read_fifos.sv
0,0 → 1,205
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_s_to_read_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
R_D = 32,
AR_D = 2,
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_s,
axi4_if axi4_read_fifo,
 
output ar_rd_empty,
input ar_rd_en,
output r_wr_full,
input r_wr_en,
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam R_W =
8*N + // logic [(8*N)-1:0] rdata;
I + // logic [(I-1):0] rid;
1 + // logic rlast;
2; // logic [1:0] rresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AR_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AR_W-1:0] ar_rd_data;
wire [AR_W-1:0] ar_wr_data;
 
generate
begin: ar_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign ar_wr_data =
{
axi4_s.araddr,
axi4_s.arburst,
axi4_s.arid,
axi4_s.arlen,
axi4_s.arsize,
axi4_s.arcache,
axi4_s.arlock,
axi4_s.arprot,
axi4_s.arqos,
axi4_s.arregion
};
 
assign
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize,
axi4_read_fifo.arcache,
axi4_read_fifo.arlock,
axi4_read_fifo.arprot,
axi4_read_fifo.arqos,
axi4_read_fifo.arregion
} = ar_rd_data;
end
else
begin
assign ar_wr_data =
{
axi4_s.araddr,
axi4_s.arburst,
axi4_s.arid,
axi4_s.arlen,
axi4_s.arsize
};
 
assign
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize
} = ar_rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire ar_wr_full;
wire ar_wr_en = axi4_s.arready & axi4_s.arvalid;
assign axi4_s.arready = ~ar_wr_full;
 
sync_fifo #(.W(AR_W), .D(AR_D))
ar_fifo
(
.wr_full(ar_wr_full),
.wr_data(ar_wr_data),
.wr_en(ar_wr_en),
.rd_empty(ar_rd_empty),
.rd_data(ar_rd_data),
.rd_en(ar_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [R_W-1:0] r_rd_data;
wire [R_W-1:0] r_wr_data;
 
assign r_wr_data =
{
axi4_read_fifo.rdata,
axi4_read_fifo.rid,
axi4_read_fifo.rlast,
axi4_read_fifo.rresp
};
 
assign
{
axi4_s.rdata,
axi4_s.rid,
axi4_s.rlast,
axi4_s.rresp
} = r_rd_data;
 
 
// --------------------------------------------------------------------
//
wire r_rd_empty;
wire r_rd_en = axi4_s.rready & axi4_s.rvalid;
assign axi4_s.rvalid = ~r_rd_empty;
 
sync_fifo #(.W(R_W), .D(R_D))
r_fifo
(
.wr_full(r_wr_full),
.wr_data(r_wr_data),
.wr_en(r_wr_en),
.rd_empty(r_rd_empty),
.rd_data(r_rd_data),
.rd_en(r_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/axi4_s_to_write_fifos.sv
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_s_to_write_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
W_D = 32,
B_D = 2,
AW_D = 2,
 
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_s,
axi4_if axi4_write_fifo,
 
output aw_rd_empty,
input aw_rd_en,
output w_rd_empty,
input w_rd_en,
output b_wr_full,
input b_wr_en,
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam W_W =
8*N + // logic [(8*N)-1:0] wdata;
I + // logic [(I-1):0] wid;
1 + // logic wlast;
N; // logic [N-1:0] wstrb;
 
localparam B_W =
I + // logic [(I-1):0] bid;
2; // logic [1:0] bresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AW_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AW_W-1:0] aw_rd_data;
wire [AW_W-1:0] aw_wr_data;
 
generate
begin: aw_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign aw_wr_data =
{
axi4_s.awaddr,
axi4_s.awburst,
axi4_s.awid,
axi4_s.awlen,
axi4_s.awsize,
axi4_s.awcache,
axi4_s.awlock,
axi4_s.awprot,
axi4_s.awqos,
axi4_s.awregion
};
 
assign
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize,
axi4_write_fifo.awcache,
axi4_write_fifo.awlock,
axi4_write_fifo.awprot,
axi4_write_fifo.awqos,
axi4_write_fifo.awregion
} = aw_rd_data;
end
else
begin
assign aw_wr_data =
{
axi4_s.awaddr,
axi4_s.awburst,
axi4_s.awid,
axi4_s.awlen,
axi4_s.awsize
};
 
assign
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize
} = aw_rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire aw_wr_full;
wire aw_wr_en = axi4_s.awready & axi4_s.awvalid;
assign axi4_s.awready = ~aw_wr_full;
 
sync_fifo #(.W(AW_W), .D(AW_D))
aw_fifo
(
.wr_full(aw_wr_full),
.wr_data(aw_wr_data),
.wr_en(aw_wr_en),
.rd_empty(aw_rd_empty),
.rd_data(aw_rd_data),
.rd_en(aw_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [W_W-1:0] w_rd_data;
wire [W_W-1:0] w_wr_data;
 
assign w_wr_data =
{
axi4_s.wdata,
axi4_s.wid,
axi4_s.wlast,
axi4_s.wstrb
};
 
assign
{
axi4_write_fifo.wdata,
axi4_write_fifo.wid,
axi4_write_fifo.wlast,
axi4_write_fifo.wstrb
} = w_rd_data;
 
 
// --------------------------------------------------------------------
//
wire w_wr_full;
wire w_wr_en = axi4_s.wready & axi4_s.wvalid;
assign axi4_s.wready = ~w_wr_full;
 
sync_fifo #(.W(W_W), .D(W_D))
w_fifo
(
.wr_full(w_wr_full),
.wr_data(w_wr_data),
.wr_en(w_wr_en),
.rd_empty(w_rd_empty),
.rd_data(w_rd_data),
.rd_en(w_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [B_W-1:0] b_rd_data;
wire [B_W-1:0] b_wr_data;
 
assign b_wr_data =
{
axi4_write_fifo.bid,
axi4_write_fifo.bresp
};
 
assign
{
axi4_s.bid,
axi4_s.bresp
} = b_rd_data;
 
 
// --------------------------------------------------------------------
//
wire b_rd_empty;
wire b_rd_en = axi4_s.bready & axi4_s.bvalid;
assign axi4_s.bvalid = ~b_rd_empty;
 
sync_fifo #(.W(B_W), .D(B_D))
b_fifo
(
.wr_full(b_wr_full),
.wr_data(b_wr_data),
.wr_en(b_wr_en),
.rd_empty(b_rd_empty),
.rd_data(b_rd_data),
.rd_en(b_rd_en),
.count(),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/axi4_to_axis_basic_dma.sv
0,0 → 1,170
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axi4_to_axis_basic_dma
#(
A, // address bus width
N, // data bus width in bytes
I, // ID width
BASE_ADDRESS, // must be on 4K boundry
BUFFER_SIZE,
BURST_LENGTH,
MAX_BURSTS, // max number of burst the FIFO can hold
BYTES_PER_TUSER = 0 // bytes per tuser bit . Set to 0 for transfer based.
)
(
axi4_if axi4_m,
axis_if axis_out,
input dma_enable,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam R_D = BURST_LENGTH * MAX_BURSTS;
localparam AR_D = 2;
localparam WATERMARK = BURST_LENGTH * (MAX_BURSTS - AR_D);
localparam STRIDE = N * BURST_LENGTH;
localparam ADDRESS_END = BASE_ADDRESS + BUFFER_SIZE;
localparam AR_STOP = (BUFFER_SIZE % STRIDE) ? ADDRESS_END - STRIDE : ADDRESS_END;
localparam R_STOP = (BUFFER_SIZE % N) ? ADDRESS_END - N : ADDRESS_END;
localparam U = N / BYTES_PER_TUSER;
 
 
// --------------------------------------------------------------------
// synthesis translate_off
localparam N_4K = 'h1000 / 'h8; // number of bytes in 4K
initial
begin
a_4k_mod_base_address: assert(BASE_ADDRESS % 'h1000 == 0) else $fatal;
a_4k_gt_eq_stride: assert(N_4K >= STRIDE) else $fatal;
a_4k_mod_stride: assert('h1000 % STRIDE == 0) else $fatal;
a_n: assert((N % BYTES_PER_TUSER == 0)) else $fatal;
a_buffer_size: assert(BUFFER_SIZE % N == 0) else $fatal;
a_bytes_per_tuser: assert(BYTES_PER_TUSER != 0) else $fatal; // need to fix
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N), .I(I)) axi4_read_fifo(.*);
axis_if #(.N(N), .U(U)) axis_in(.*);
 
 
// --------------------------------------------------------------------
//
reg [(A-1):0] araddr_r;
wire araddr_en = (araddr_r < AR_STOP);
wire r_watermark;
wire ar_wr_full;
wire ar_wr_en = ~ar_wr_full & ~r_watermark & araddr_en & dma_enable;
 
always_ff @(posedge aclk)
if(~aresetn | ~araddr_en)
araddr_r <= BASE_ADDRESS;
else if(ar_wr_en)
araddr_r <= araddr_r + STRIDE;
 
 
// --------------------------------------------------------------------
//
reg [(A-1):0] r_rd_addr;
wire r_rd_addr_en = (r_rd_addr < R_STOP);
wire r_rd_addr_start = (r_rd_addr == BASE_ADDRESS);
wire r_rd_addr_end = (r_rd_addr == R_STOP);
wire r_rd_empty;
wire r_topped_off;
wire r_rd_en = ~r_rd_empty & r_rd_addr_en & axis_in.tready;
 
always_ff @(posedge aclk)
if(~aresetn | ~r_rd_addr_en)
r_rd_addr <= BASE_ADDRESS;
else if(r_rd_en)
r_rd_addr <= r_rd_addr + N;
 
 
// --------------------------------------------------------------------
//
axi4_m_to_read_fifos #(.A(A), .N(N), .I(I), .R_D(R_D), .AR_D(AR_D), .WATERMARK(WATERMARK))
axi4_m_to_read_fifos_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axi4_read_fifo.araddr = araddr_r;
assign axi4_read_fifo.arid = 0;
assign axi4_read_fifo.arburst = 2'b01;
assign axi4_read_fifo.arsize = $clog2(N);
assign axi4_read_fifo.arlen = BURST_LENGTH - 1;
assign axi4_read_fifo.rready = 1;
 
 
// --------------------------------------------------------------------
//
assign axi4_m.awaddr = 0;
assign axi4_m.awburst = 0;
assign axi4_m.awcache = 0;
assign axi4_m.awid = 0;
assign axi4_m.awlen = 0;
assign axi4_m.awlock = 0;
assign axi4_m.awprot = 0;
assign axi4_m.awqos = 0;
assign axi4_m.awregion = 0;
assign axi4_m.awsize = 0;
assign axi4_m.awvalid = 0;
assign axi4_m.bready = 0;
assign axi4_m.wdata = 0;
assign axi4_m.wid = 0;
assign axi4_m.wlast = 0;
assign axi4_m.wstrb = 0;
assign axi4_m.wvalid = 0;
 
 
// --------------------------------------------------------------------
//
assign axis_in.tvalid = ~r_rd_empty;
assign axis_in.tdata = axi4_read_fifo.rdata;
assign axis_in.tlast = axi4_read_fifo.rlast;
assign axis_in.tuser[0] = r_rd_addr_start;
assign axis_in.tuser[U-1:1] = 0; // need to fix
 
 
// --------------------------------------------------------------------
//
axis_register_slice #(.N(N), .U(U))
axis_register_slice_i(.*);
 
 
// --------------------------------------------------------------------
//
endmodule
 

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