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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_lib
    from Rev 24 to Rev 29
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  •

Rev 24 → Rev 29

/sim/libs/axi4_lib_verilog/axi4_base.f
0,0 → 1,12
#
 
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_if.sv
# ${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_read_fsm.sv
# ${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_write_fsm.sv
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_read_fifos.sv
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_write_fifos.sv
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_register_slice.sv
 
 
 
 
/sim/libs/axi4_lib_verilog/axi4_stream_lib.f
0,0 → 1,13
#
 
 
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_if.sv
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_video_debug.sv
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/data_to_axis_fsm.sv
 
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_to_vid_fsm.sv
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/camera_link_to_axis.sv
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/camera_link_to_axis_fsm.sv
 
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_register_slice.sv
 
/sim/libs/axi4_lib_verilog/tiny_fifo.f
0,0 → 1,9
#
 
 
# ${ROOT_DIR}/qaz_libs/FIFOs/src/tiny_sync_fifo.sv
# ${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_read_if.sv
# ${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_write_if.sv
 
${ROOT_DIR}/qaz_libs/FIFOs/src/fifo_witout_if/tiny_sync_fifo.sv
 
/sim/libs/packages_verilog/tb_lib.f
0,0 → 1,7
#
 
${ROOT_DIR}/qaz_libs/tb_class/src/tb_bfm_pkg.sv
 
 
 
 
/sim/libs/sim_verilog/axi4_bfm.f
0,0 → 1,19
#
 
+incdir+${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva
 
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva/Axi4PC_ace.sv
 
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv
 
 
# ${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/qaz_axi4_bfm_pkg.sv
# ${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/tb_axi4lite_bfm_if.sv
 
 
 
 
/sim/libs/sim_verilog/tb_lib.f
0,0 → 1,16
#
 
-mfcu
 
${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk_class.sv
 
${ROOT_DIR}/qaz_libs/tb_class/src/tb_clk.sv
${ROOT_DIR}/qaz_libs/tb_class/src/tb_base.sv
 
 
 
 
 
 
 
 
/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv
0,0 → 1,187
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
axi4_checker
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
MAXRBURSTS = 16,
MAXWBURSTS = 16,
MAXWAITS = 16,
RecommendOn = 1'b1,
RecMaxWaitOn = 1'b1,
EXMON_WIDTH = 4,
PROTOCOL = 2'b00
)
(
axi4_if axi4_in
);
 
//---------------------------------------------------
//
localparam AWUSER_MAX = 0;
localparam WUSER_MAX = 0;
localparam BUSER_MAX = 0;
localparam ARUSER_MAX = 0;
localparam RUSER_MAX = 0;
//---------------------------------------------------
//
// INDEX: - Global Signals
// =====
wire ACLK = axi4_in.aclk; // AXI Clock
wire ARESETn = axi4_in.aresetn; // AXI Reset
 
// INDEX: - Write Address Channel
// =====
wire [(I-1):0] AWID = axi4_in.awid;
wire [(A-1):0] AWADDR = axi4_in.awaddr;
wire [7:0] AWLEN = axi4_in.awlen;
wire [2:0] AWSIZE = axi4_in.awsize;
wire [1:0] AWBURST = axi4_in.awburst;
wire [3:0] AWCACHE = axi4_in.awcache;
wire [2:0] AWPROT = axi4_in.awprot;
wire [3:0] AWQOS = axi4_in.awqos;
wire [3:0] AWREGION = axi4_in.awregion;
wire AWLOCK = axi4_in.awlock;
wire [AWUSER_MAX:0] AWUSER = 0;
wire AWVALID = axi4_in.awvalid;
wire AWREADY = axi4_in.awready;
 
// INDEX: - Write Data Channel
// =====
wire [(8*N)-1:0] WDATA = axi4_in.wdata;
wire [N-1:0] WSTRB = axi4_in.wstrb;
wire [WUSER_MAX:0] WUSER = 0;
wire WLAST = axi4_in.wlast;
wire WVALID = axi4_in.wvalid;
wire WREADY = axi4_in.wready;
 
// INDEX: - Write Response Channel
// =====
wire [(I-1):0] BID = axi4_in.bid;
wire [1:0] BRESP = axi4_in.bresp;
wire [BUSER_MAX:0] BUSER = 0;
wire BVALID = axi4_in.bvalid;
wire BREADY = axi4_in.bready;
 
// INDEX: - Read Address Channel
// =====
wire [(I-1):0] ARID = axi4_in.arid;
wire [(A-1):0] ARADDR = axi4_in.araddr;
wire [7:0] ARLEN = axi4_in.arlen;
wire [2:0] ARSIZE = axi4_in.arsize;
wire [1:0] ARBURST = axi4_in.arburst;
wire [3:0] ARCACHE = axi4_in.arcache;
wire [3:0] ARQOS = axi4_in.arqos;
wire [3:0] ARREGION = axi4_in.arregion;
wire [2:0] ARPROT = axi4_in.arprot;
wire ARLOCK = axi4_in.arlock;
wire [ARUSER_MAX:0] ARUSER = 0;
wire ARVALID = axi4_in.arvalid;
wire ARREADY = axi4_in.arready;
 
// INDEX: - Read Data Channel
// =====
wire [(I-1):0] RID = axi4_in.rid;
wire [(8*N)-1:0] RDATA = axi4_in.rdata;
wire [1:0] RRESP = axi4_in.rresp;
wire [RUSER_MAX:0] RUSER = 0;
wire RLAST = axi4_in.rlast;
wire RVALID = axi4_in.rvalid;
wire RREADY = axi4_in.rready;
 
// INDEX: - Low Power Interface
// =====
wire CACTIVE = 1;
wire CSYSREQ = 0;
wire CSYSACK = 0;
 
 
//---------------------------------------------------
//
Axi4PC_ace
#(
// Set DATA_WIDTH to the data-bus width required
.DATA_WIDTH(8*N), // = 64; // data bus width, default = 64-bit
 
// Select the number of channel ID bits required
.WID_WIDTH(I), // = 4; // (A|W|R|B)ID width
.RID_WIDTH(I), // = 4; // (A|W|R|B)ID width
 
// Select the size of the USER buses, default = 32-bit
.AWUSER_WIDTH(0), // = 32; // width of the user AW sideband field
.WUSER_WIDTH(0), // = 32; // width of the user W sideband field
.BUSER_WIDTH(0), // = 32; // width of the user B sideband field
.ARUSER_WIDTH(0), // = 32; // width of the user AR sideband field
.RUSER_WIDTH(0), // = 32; // width of the user R sideband field
 
// Size of CAMs for storing outstanding read bursts, this should match or
// exceed the number of outstanding read addresses accepted into the slave
// interface
.MAXRBURSTS(MAXRBURSTS), // = 16;
 
// Size of CAMs for storing outstanding write bursts, this should match or
// exceed the number of outstanding write bursts into the slave interface
.MAXWBURSTS(MAXWBURSTS), // = 16;
 
// Maximum number of cycles between VALID -> READY high before a warning is
// generated
.MAXWAITS(MAXWAITS), // = 16;
 
// Recommended Rules Enable
// enable/disable reporting of all AXI4_REC*_* rules
.RecommendOn(RecommendOn), // = 1'b1;
// enable/disable reporting of just AXI4_REC*_MAX_WAIT rules
.RecMaxWaitOn(RecMaxWaitOn), // = 1'b1;
 
// Set the protocol - used to disable some AXI4 checks for ACE
//PROTOCOL define the protocol
// `define AXI4PC_AMBA_AXI4 2'b00
// `define AXI4PC_AMBA_ACE 2'b01
// `define AXI4PC_AMBA_ACE_LITE 2'b10
.PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4;
 
// Set ADDR_WIDTH to the address-bus width required
.ADDR_WIDTH(A), // = 32; // address bus width, default = 32-bit
 
// Set EXMON_WIDTH to the exclusive access monitor width required
.EXMON_WIDTH(EXMON_WIDTH) // = 4; // exclusive access width, default = 4-bit
)
Axi4PC_ace_i(.*);
 
//---------------------------------------------------
//
 
endmodule
 
/sim/src/axi4_bfm/axi4_master_bfm_if.sv
0,0 → 1,526
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
axi4_master_bfm_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
)
(
axi4_if axi4_s,
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
 
 
// --------------------------------------------------------------------
//
default clocking cb @(posedge aclk);
output arid;
output araddr;
output arburst;
output arcache;
output awid;
output arlen;
output arlock;
output arprot;
output arqos;
input arready;
output arregion;
output arsize;
output arvalid;
output awaddr;
output awburst;
output awcache;
output awlen;
output awlock;
output awprot;
output awqos;
input awready;
output awregion;
output awsize;
output awvalid;
output bready;
input bid;
input bresp;
input bvalid;
input rdata;
input rid;
input rlast;
output rready;
input rresp;
input rvalid;
output wdata;
output wlast;
input wready;
output wstrb;
output wvalid;
input aresetn;
input aclk;
endclocking
 
 
// --------------------------------------------------------------------
//
assign axi4_s.arid = arid;
assign axi4_s.araddr = araddr;
assign axi4_s.arburst = arburst;
assign axi4_s.arcache = arcache;
assign axi4_s.awid = awid;
assign axi4_s.arlen = arlen;
assign axi4_s.arlock = arlock;
assign axi4_s.arprot = arprot;
assign axi4_s.arqos = arqos;
assign arready = axi4_s.arready;
assign axi4_s.arregion = arregion;
assign axi4_s.arsize = arsize;
assign axi4_s.arvalid = arvalid;
assign axi4_s.awaddr = awaddr;
assign axi4_s.awburst = awburst;
assign axi4_s.awcache = awcache;
assign axi4_s.awlen = awlen;
assign axi4_s.awlock = awlock;
assign axi4_s.awprot = awprot;
assign axi4_s.awqos = awqos;
assign awready = axi4_s.awready;
assign axi4_s.awregion = awregion;
assign axi4_s.awsize = awsize;
assign axi4_s.awvalid = awvalid;
assign axi4_s.bready = bready;
assign bid = axi4_s.bid;
assign bresp = axi4_s.bresp;
assign bvalid = axi4_s.bvalid;
assign rdata = axi4_s.rdata;
assign rid = axi4_s.rid;
assign rlast = axi4_s.rlast;
assign axi4_s.rready = rready;
assign rresp = axi4_s.rresp;
assign rvalid = axi4_s.rvalid;
assign axi4_s.wdata = wdata;
assign axi4_s.wlast = wlast;
assign wready = axi4_s.wready;
assign axi4_s.wstrb = wstrb;
assign axi4_s.wvalid = wvalid;
 
 
// --------------------------------------------------------------------
//
function void
ar_default;
 
cb.araddr <= 'bx;
cb.arburst <= 'bx;
cb.arcache <= 'bx;
cb.arid <= 'bx;
cb.arlen <= 'bx;
cb.arlock <= 'bx;
cb.arprot <= 'bx;
cb.arqos <= 'bx;
cb.arregion <= 'bx;
cb.arsize <= 'bx;
cb.arvalid <= 0;
 
endfunction: ar_default
 
 
// --------------------------------------------------------------------
//
function void
aw_default;
 
cb.awaddr <= 'bx;
cb.awburst <= 'bx;
cb.awcache <= 'bx;
cb.awid <= 'bx;
cb.awlen <= 'bx;
cb.awlock <= 'bx;
cb.awprot <= 'bx;
cb.awqos <= 'bx;
cb.awregion <= 'bx;
cb.awsize <= 'bx;
cb.awvalid <= 0;
 
endfunction: aw_default
 
 
// --------------------------------------------------------------------
//
function void
r_default;
 
cb.rready <= 0;
 
endfunction: r_default
 
 
// --------------------------------------------------------------------
//
function void
w_default;
 
cb.wdata <= 'bx;
cb.wlast <= 'bx;
cb.wstrb <= {N{1'b1}};
cb.wvalid <= 0;
 
endfunction: w_default
 
 
// --------------------------------------------------------------------
//
function void
b_default;
 
cb.bready <= 0;
 
endfunction: b_default
 
 
// --------------------------------------------------------------------
//
function void
init;
 
ar_default();
r_default();
aw_default();
w_default();
b_default();
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
import tb_bfm_pkg::*;
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class ar_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.araddr <= tr_h.addr;
cb.arid <= tr_h.id;
cb.arlen <= tr_h.len;
cb.arsize <= tr_h.size;
 
cb.arburst <= tr_h.burst;
cb.arcache <= tr_h.cache;
cb.arlock <= tr_h.lock;
cb.arprot <= tr_h.prot;
cb.arqos <= tr_h.qos;
cb.arregion <= tr_h.region;
cb.arvalid <= 1;
 
$display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);
 
##1;
wait(cb.arready);
 
##0;
ar_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: ar_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class r_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
tr_h.data_h = new(tr_h.len);
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
cb.rready <= 1;
##1;
 
wait(cb.rvalid);
##0;
 
tr_h.data_h.w[i] = cb.rdata;
 
$display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
r_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: r_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class aw_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.awaddr <= tr_h.addr;
cb.awid <= tr_h.id;
cb.awlen <= tr_h.len;
cb.awsize <= tr_h.size;
 
cb.awburst <= tr_h.burst;
cb.awcache <= tr_h.cache;
cb.awlock <= tr_h.lock;
cb.awprot <= tr_h.prot;
cb.awqos <= tr_h.qos;
cb.awregion <= tr_h.region;
cb.awvalid <= 1;
 
$display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);
 
##1;
wait(cb.awready);
 
##0;
aw_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: aw_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class w_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.wdata <= tr_h.payload_h.w[i];
// cb.wstrb <= tr_h.strb; // need to fix
 
if(i < tr_h.payload_h.w.size - 1)
cb.wlast <= 0;
else
cb.wlast <= 1;
 
cb.wvalid <= 1;
 
##1;
wait(cb.wready);
 
##0;
$display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
w_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: w_master_transaction_class
 
 
// --------------------------------------------------------------------
//
class b_master_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
cb.bready <= 1;
##1;
 
wait(cb.bvalid);
##0;
 
$display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp);
b_default();
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: b_master_transaction_class
 
 
// --------------------------------------------------------------------
//
ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h;
aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h;
b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h;
 
initial
begin
init();
ar_h = new;
ar_h.init();
r_h = new;
r_h.init();
aw_h = new;
aw_h.init();
w_h = new;
w_h.init();
b_h = new;
b_h.init();
end
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv
0,0 → 1,153
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_simple_agent_pkg;
 
// --------------------------------------------------------------------
//
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class axi4_simple_agent_class #(A = 32, N = 8, I = 1);
 
axi4_transaction_class tr_h;
virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m;
virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s;
 
 
//--------------------------------------------------------------------
function new
(
virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m,
virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s
);
 
this.axi4_m = axi4_m;
this.axi4_s = axi4_s;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
task
basic_read
(
input logic [(A-1):0] araddr,
input logic [7:0] arlen,
output logic [(8*N)-1:0] data[],
output logic [1:0] rresp
);
 
this.tr_h = new;
this.tr_h.basic_read(araddr, arlen);
 
axi4_m.ar_h.put(tr_h);
axi4_s.ar_h.put(tr_h);
axi4_m.r_h.put(tr_h);
 
@(axi4_m.r_h.done);
data = tr_h.data_h.w;
rresp = tr_h.resp;
 
endtask: basic_read
 
 
// --------------------------------------------------------------------
//
task
basic_write
(
input logic [(A-1):0] awaddr,
input logic [7:0] awlen,
input logic [(8*N)-1:0] data[],
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_write(awaddr, awlen);
 
foreach(this.tr_h.payload_h.w[i])
this.tr_h.payload_h.w[i] = data[i];
 
axi4_m.aw_h.put(tr_h);
axi4_s.aw_h.put(tr_h);
axi4_m.w_h.put(tr_h);
axi4_s.w_h.put(tr_h);
axi4_m.b_h.put(tr_h);
 
@(axi4_s.b_h.done);
bresp = tr_h.resp;
 
endtask: basic_write
 
 
// --------------------------------------------------------------------
//
task
basic_random_write
(
input logic [(A-1):0] awaddr,
input logic [7:0] awlen,
output logic [1:0] bresp
);
 
this.tr_h = new;
this.tr_h.basic_write(awaddr, awlen);
 
axi4_m.aw_h.put(tr_h);
axi4_s.aw_h.put(tr_h);
axi4_m.w_h.put(tr_h);
axi4_s.w_h.put(tr_h);
axi4_m.b_h.put(tr_h);
 
@(axi4_s.b_h.done);
bresp = tr_h.resp;
 
endtask: basic_random_write
 
 
// --------------------------------------------------------------------
//
function void
init;
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
endclass: axi4_simple_agent_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_simple_agent_pkg
 
/sim/src/axi4_bfm/axi4_slave_bfm_if.sv
0,0 → 1,514
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
interface
axi4_slave_bfm_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
)
(
axi4_if axi4_m,
input aresetn,
input aclk
);
 
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
 
 
// --------------------------------------------------------------------
//
default clocking cb @(posedge aclk);
input arid;
input araddr;
input arburst;
input arcache;
input awid;
input arlen;
input arlock;
input arprot;
input arqos;
output arready;
input arregion;
input arsize;
input arvalid;
input awaddr;
input awburst;
input awcache;
input awlen;
input awlock;
input awprot;
input awqos;
output awready;
input awregion;
input awsize;
input awvalid;
input bready;
output bid;
output bresp;
output bvalid;
output rdata;
output rid;
output rlast;
input rready;
output rresp;
output rvalid;
input wdata;
input wid;
input wlast;
output wready;
input wstrb;
input wvalid;
input aresetn;
input aclk;
endclocking
 
 
// --------------------------------------------------------------------
//
assign arid = axi4_m.arid;
assign araddr = axi4_m.araddr;
assign arburst = axi4_m.arburst;
assign arcache = axi4_m.arcache;
assign awid = axi4_m.awid;
assign arlen = axi4_m.arlen;
assign arlock = axi4_m.arlock;
assign arprot = axi4_m.arprot;
assign arqos = axi4_m.arqos;
assign axi4_m.arready = arready;
assign arregion = axi4_m.arregion;
assign arsize = axi4_m.arsize;
assign arvalid = axi4_m.arvalid;
assign awaddr = axi4_m.awaddr;
assign awburst = axi4_m.awburst;
assign awcache = axi4_m.awcache;
assign awlen = axi4_m.awlen;
assign awlock = axi4_m.awlock;
assign awprot = axi4_m.awprot;
assign awqos = axi4_m.awqos;
assign axi4_m.awready = awready;
assign awregion = axi4_m.awregion;
assign awsize = axi4_m.awsize;
assign awvalid = axi4_m.awvalid;
assign bready = axi4_m.bready;
assign axi4_m.bid = bid;
assign axi4_m.bresp = bresp;
assign axi4_m.bvalid = bvalid;
assign axi4_m.rdata = rdata;
assign axi4_m.rid = rid;
assign axi4_m.rlast = rlast;
assign rready = axi4_m.rready;
assign axi4_m.rresp = rresp;
assign axi4_m.rvalid = rvalid;
assign wdata = axi4_m.wdata;
assign wlast = axi4_m.wlast;
assign axi4_m.wready = wready;
assign wstrb = axi4_m.wstrb;
assign wvalid = axi4_m.wvalid;
 
 
// --------------------------------------------------------------------
//
function void
ar_default;
 
cb.arready <= 0;
 
endfunction: ar_default
 
 
// --------------------------------------------------------------------
//
function void
aw_default;
 
cb.awready <= 0;
 
endfunction: aw_default
 
 
// --------------------------------------------------------------------
//
function void
r_default;
 
cb.rdata <= 'bx;
cb.rid <= 'bx;
cb.rlast <= 'bx;
cb.rresp <= 0;
cb.rvalid <= 0;
 
endfunction: r_default
 
 
// --------------------------------------------------------------------
//
function void
w_default;
 
cb.wready <= 0;
 
endfunction: w_default
 
 
// --------------------------------------------------------------------
//
function void
b_default;
 
cb.bid <= 0;
cb.bresp <= 0;
cb.bvalid <= 0;
 
endfunction: b_default
 
 
// --------------------------------------------------------------------
//
function void
init;
 
ar_default();
r_default();
aw_default();
w_default();
b_default();
 
endfunction: init
 
 
// --------------------------------------------------------------------
//
task
zero_cycle_delay;
 
##0;
 
endtask: zero_cycle_delay
 
 
// --------------------------------------------------------------------
//
import tb_bfm_pkg::*;
import axi4_transaction_pkg::*;
 
 
// --------------------------------------------------------------------
//
class r_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.rdata <= tr_h.payload_h.w[i];
cb.rresp <= tr_h.resp;
cb.rid <= tr_h.id;
 
if(i < tr_h.payload_h.w.size - 1)
cb.rlast <= 0;
else
cb.rlast <= 1;
 
cb.rvalid <= 1;
##1;
 
wait(cb.rready);
##0;
 
$display("^^^ %16.t | %m | slave R transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
r_default();
end
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: r_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
r_slave_transaction_class #(.A(A), .N(N), .I(I)) r_h;
 
class ar_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.arready <= 1;
##1;
 
wait(cb.arvalid);
 
##0;
r_h.put(tr_h);
ar_default();
 
$display("^^^ %16.t | %m | slave AR transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: ar_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
class aw_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
semaphore aw_semaphore;
 
 
//--------------------------------------------------------------------
function new;
 
super.new();
this.aw_semaphore = new(0);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
##(tr_h.delay_h.next());
 
cb.awready <= 1;
##1;
 
wait(cb.awvalid);
 
##0;
this.aw_semaphore.put();
aw_default();
 
$display("^^^ %16.t | %m | slave AW transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
 
->this.done;
 
endtask: transaction
 
// --------------------------------------------------------------------
//
endclass: aw_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
aw_slave_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
 
class b_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
// Error: AXI4_ERRS_BRESP_AW: A slave must not give a write response before the write address.
// Spec: section A3.3.1 and figure A3-7.
aw_h.aw_semaphore.get(); // better way to do this???
 
##(tr_h.delay_h.next());
 
cb.bresp <= tr_h.resp;
cb.bid <= tr_h.id;
 
cb.bvalid <= 1;
##1;
 
wait(cb.bready);
##0;
 
$display("^^^ %16.t | %m | slave B transaction |", $time);
b_default();
 
->this.done;
 
endtask: transaction
 
// --------------------------------------------------------------------
//
endclass: b_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
b_slave_transaction_class #(.A(A), .N(N), .I(I)) b_h;
 
class w_slave_transaction_class #(A = 32, N = 8, I = 1)
extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
// --------------------------------------------------------------------
//
task automatic
transaction
(
ref T tr_h
);
 
->this.start;
 
tr_h.data_h = new(tr_h.len);
 
foreach(tr_h.payload_h.w[i])
begin
##(tr_h.delay_h.next());
 
cb.wready <= 1;
##1;
 
wait(cb.wvalid);
##0;
 
tr_h.data_h.w[i] <= cb.wdata;
$display("^^^ %16.t | %m | slave W transaction | %d | 0x%016x |", $time, i, cb.wdata);
w_default();
end
 
b_h.put(tr_h);
 
->this.done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
endclass: w_slave_transaction_class
 
 
// --------------------------------------------------------------------
//
ar_slave_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
w_slave_transaction_class #(.A(A), .N(N), .I(I)) w_h;
 
initial
begin
init();
ar_h = new;
ar_h.init();
r_h = new;
r_h.init();
aw_h = new;
aw_h.init();
w_h = new;
w_h.init();
b_h = new;
b_h.init();
end
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/sim/src/axi4_bfm/axi4_transaction_pkg.sv
0,0 → 1,253
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package axi4_transaction_pkg;
 
// --------------------------------------------------------------------
//
class axi4_delay_class;
 
rand int unsigned delay;
 
 
// --------------------------------------------------------------------
//
function int unsigned
next;
 
assert(this.randomize() with{delay dist {0 := 40, [1:3] := 40, [4:7] := 20};});
return(delay);
 
endfunction: next
 
 
// --------------------------------------------------------------------
//
endclass: axi4_delay_class
 
 
// --------------------------------------------------------------------
//
class axi4_payload_class #(N = 8);
 
rand logic [(8*N)-1:0] w[];
 
 
// --------------------------------------------------------------------
//
function
new
(
logic [7:0] len = 0
);
 
this.w = new[len + 1];
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
random
(
logic [7:0] len = 0
);
 
this.w = new[len + 1];
assert(this.randomize());
 
endfunction: random
 
 
// --------------------------------------------------------------------
//
endclass: axi4_payload_class
 
 
// --------------------------------------------------------------------
//
class axi4_transaction_class #(A = 32, N = 8, I = 1);
 
axi4_delay_class delay_h;
axi4_payload_class #(.N(N)) payload_h;
axi4_payload_class #(.N(N)) data_h;
rand logic [(A-1):0] addr = 'bz;
rand logic [1:0] burst = 2'b01;
rand logic [7:0] len = 0;
rand logic [2:0] size = $clog2(N);
rand logic [(I-1):0] id = 0;
rand logic [1:0] resp = 0;
 
logic [3:0] cache = 0;
logic lock = 0;
logic [2:0] prot = 0;
logic [3:0] qos = 0;
logic [3:0] region = 0;
 
constraint default_len
{
len dist {0 := 40, [1:15] := 40, [16:255] := 20};
}
 
 
// --------------------------------------------------------------------
//
function
new
(
logic [7:0] len = 0
);
 
this.payload_h = new(len + 1);
this.delay_h = new;
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
function void
basic_random;
 
assert(this.randomize() with
{
this.id == 0;
this.resp == 0;
this.burst == 2'b01;
this.len == 0;
this.size == $clog2(N);
});
 
this.payload_h.random(this.len);
 
endfunction: basic_random
 
 
// --------------------------------------------------------------------
//
function void
basic_random_burst;
 
assert(this.randomize() with
{
this.addr[$clog2(N*8)-1:0] == 0;
this.id == 0;
this.resp == 0;
this.burst == 2'b01;
this.size == $clog2(N);
this.len dist {0 := 40, [1:3] := 40, [4:15] := 20};
});
 
this.payload_h.random(this.len);
 
endfunction: basic_random_burst
 
 
// --------------------------------------------------------------------
//
function void
basic_read
(
logic [(A-1):0] addr,
logic [7:0] len = 0
);
 
this.id = 0;
this.resp = 0;
this.burst = 2'b01;
this.size = $clog2(N);
this.addr = addr;
this.len = len;
this.payload_h.random(len);
 
endfunction: basic_read
 
 
// --------------------------------------------------------------------
//
function void
basic_write
(
logic [(A-1):0] addr,
logic [7:0] len = 0
);
 
this.id = 0;
this.resp = 0;
this.burst = 2'b01;
this.size = $clog2(N);
this.addr = addr;
this.len = len;
this.payload_h.random(len);
 
endfunction: basic_write
 
 
// --------------------------------------------------------------------
//
function void copy
(
axi4_transaction_class #(.A(A), .N(N), .I(I)) from
);
 
this.addr = from.addr;
this.burst = from.burst;
this.len = from.len;
this.size = from.size;
this.id = from.id;
this.resp = from.resp;
this.cache = from.cache;
this.lock = from.lock;
this.prot = from.prot;
this.qos = from.qos;
this.region = from.region;
 
endfunction: copy
 
 
// --------------------------------------------------------------------
//
virtual function axi4_transaction_class #(.A(A), .N(N), .I(I)) clone;
 
clone = new();
clone.copy(this);
return(clone);
 
endfunction: clone
 
 
// --------------------------------------------------------------------
//
endclass: axi4_transaction_class
 
 
// --------------------------------------------------------------------
//
endpackage: axi4_transaction_pkg
 
/sim/src/tb_bfm.sv
0,0 → 1,119
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 8;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N))
axi4_bus(.*);
 
axi4_checker #(.A(A), .N(N))
axi4_in_check(.axi4_in(axi4_bus));
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
import axi4_simple_agent_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_master_bfm_if #(.A(A), .N(N))
axi4_m(.axi4_s(axi4_bus), .*);
 
axi4_slave_bfm_if #(.A(A), .N(N))
axi4_s(.axi4_m(axi4_bus), .*);
 
 
// --------------------------------------------------------------------
//
axi4_simple_agent_class bfm;
 
initial
bfm = new(axi4_m, axi4_s);
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/sim/src/tb_register_slice.sv
0,0 → 1,133
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
localparam A = 32;
localparam N = 8;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N))
axi4_s(.*);
axi4_if #(.A(A), .N(N))
axi4_m(.*);
 
// --------------------------------------------------------------------
//
axi4_register_slice #(.A(A), .N(N))
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N))
axi4_s_check(.axi4_in(axi4_s));
 
axi4_checker #(.A(A), .N(N))
axi4_m_check(.axi4_in(axi4_m));
 
 
// --------------------------------------------------------------------
//
import axi4_simple_agent_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_master_bfm_if #(.A(A), .N(N))
tb_axi4_m(.axi4_s(axi4_s), .*);
 
axi4_slave_bfm_if #(.A(A), .N(N))
tb_axi4_s(.axi4_m(axi4_m), .*);
 
 
// --------------------------------------------------------------------
//
axi4_simple_agent_class bfm;
 
initial
bfm = new(tb_axi4_m, tb_axi4_s);
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
 
 
 
/sim/tests/debug_bfm/init_test.do
0,0 → 1,34
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all packages
sim_compile_all sim
sim_compile_all axi4_lib
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_bfm.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/sim/tests/debug_bfm/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/sim/tests/debug_bfm/the_test.sv
0,0 → 1,117
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
localparam A = tb_top.A;
localparam N = tb_top.N;
 
 
// --------------------------------------------------------------------
//
import axi4_transaction_pkg::*;
axi4_payload_class payload_h;
 
 
// --------------------------------------------------------------------
//
logic [(8*N)-1:0] data[];
logic [1:0] resp;
 
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(100us);
 
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
#100ns;
 
// // --------------------------------------------------------------------
// #100ns;
 
repeat(5)
begin
tb_top.bfm.basic_read(32'h1234_0000, 3, data, resp);
 
foreach(data[i])
$display("^^^ %16.t | %d | 0x%016x |", $time, i, data[i]);
end
 
tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp);
$display("^^^ %16.t | 0x%016x |", $time, data[0]);
 
 
// --------------------------------------------------------------------
#100ns;
 
data = new[1];
data[0] = 64'habba_beef_cafe_1a7e;
tb_top.bfm.basic_write(32'h1234_0000, 0, data, resp);
// $display("^^^ %16.t | 0x%016x |", $time, data[0]);
 
// --------------------------------------------------------------------
#100ns;
 
repeat(5)
begin
tb_top.bfm.basic_random_write(32'habcd_0000, 0, resp);
end
 
// --------------------------------------------------------------------
#100ns;
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/sim/tests/debug_bfm/wip.do
0,0 → 1,14
#
 
# vlog -f ../../libs/packages_verilog/tb_lib.f
vlog -f ../../libs/sim_verilog/axi4_bfm.f
 
vlog -f ../../libs/axi4_lib_verilog/axi4_base.f
 
# simulation $root
vlog ../../src/tb_bfm.sv
 
# compile test last
vlog ./the_test.sv
 
/sim/tests/debug_register_slice/init_test.do
0,0 → 1,34
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all packages
sim_compile_all sim
sim_compile_all axi4_lib
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_register_slice.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/sim/tests/debug_register_slice/sim.do
0,0 → 1,21
#
#
 
 
quit -sim
 
# vsim opt_tb_top
 
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
 
# # log all signals
# log -r *
 
# run -all
 
 
/sim/tests/debug_register_slice/the_test.sv
0,0 → 1,126
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
localparam A = tb_top.A;
localparam N = tb_top.N;
// --------------------------------------------------------------------
//
import axi4_transaction_pkg::*;
axi4_payload_class payload_h;
// --------------------------------------------------------------------
//
logic [(8*N)-1:0] data[];
logic [1:0] resp;
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
 
tb_top.tb.timeout_stop(20us);
// tb_top.tb.timeout_stop(300ns);
 
// --------------------------------------------------------------------
wait(~tb_rst);
 
 
// --------------------------------------------------------------------
#100ns;
repeat(5)
begin
tb_top.bfm.basic_read(32'h1234_0000, 3, data, resp);
foreach(data[i])
$display("^^^ %16.t | %d | 0x%016x |", $time, i, data[i]);
end
tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp);
$display("^^^ %16.t | 0x%016x |", $time, data[0]);
// // --------------------------------------------------------------------
// tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp);
// $display("^^^ %16.t | 0x%016x |", $time, data[0]);
// --------------------------------------------------------------------
#100ns;
 
data = new[1];
data[0] = 64'habba_beef_cafe_1a7e;
tb_top.bfm.basic_write(32'h1234_0000, 0, data, resp);
 
// --------------------------------------------------------------------
#100ns;
 
repeat(5)
begin
tb_top.bfm.basic_random_write(32'habcd_0000, 0, resp);
end
 
// --------------------------------------------------------------------
#100ns;
 
repeat(5)
begin
tb_top.bfm.basic_random_write(32'habcd_0000, 3, resp);
end
// --------------------------------------------------------------------
#100ns;
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 
/sim/tests/debug_register_slice/wip.do
0,0 → 1,14
#
 
# vlog -f ../../libs/packages_verilog/tb_lib.f
vlog -f ../../libs/sim_verilog/axi4_bfm.f
 
vlog -f ../../libs/axi4_lib_verilog/axi4_base.f
 
# simulation $root
vlog ../../src/tb_register_slice.sv
 
# compile test last
vlog ./the_test.sv
 
/src/axi4_if.sv
29,146 → 29,60
interface
axi4_if
#(
DATA_WIDTH = 64
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1 // ID width
)
(
input aresetn,
input aclk
input aresetn,
input aclk
);
 
wire arready;
wire arregion;
wire awready;
wire awregion;
wire bvalid;
wire rlast;
wire rvalid;
wire wready;
wire [1:0] bresp;
wire [1:0] rresp;
wire [5:0] bid;
wire [5:0] rid;
wire [DATA_WIDTH-1:0] rdata;
wire [7:0] rcount;
wire [7:0] wcount;
wire [2:0] racount;
wire [5:0] wacount;
wire arvalid;
wire awvalid;
wire bready;
wire rready;
wire wlast;
wire wvalid;
wire [1:0] arburst;
wire [1:0] arlock;
wire [2:0] arsize;
wire [1:0] awburst;
wire [1:0] awlock;
wire [2:0] awsize;
wire [2:0] arprot;
wire [2:0] awprot;
wire [31:0] araddr;
wire [31:0] awaddr;
wire [3:0] arcache;
wire [7:0] arlen;
wire [3:0] arqos;
wire [3:0] awcache;
wire [3:0] awlen;
wire [3:0] awqos;
wire [5:0] arid;
wire [5:0] awid;
wire [5:0] wid;
wire [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH/8-1:0] wstrb;
// --------------------------------------------------------------------
//
modport
master
(
output arid,
output araddr,
output arburst,
output arcache,
output arlen,
output arlock,
output arprot,
output arqos,
input arready,
output arregion,
output arsize,
output arvalid,
output awaddr,
output awburst,
output awcache,
output awlen,
output awlock,
output awprot,
output awqos,
input awready,
output awregion,
output awsize,
output awvalid,
output bready,
input bresp,
input bvalid,
input rdata,
input rlast,
output rready,
input rresp,
input rvalid,
output wdata,
output wlast,
input wready,
output wstrb,
output wvalid,
input aresetn,
input aclk
);
modport
slave
(
input arid,
input araddr,
input arburst,
input arcache,
input arlen,
input arlock,
input arprot,
input arqos,
output arready,
input arregion,
input arsize,
input arvalid,
input awaddr,
input awburst,
input awcache,
input awlen,
input awlock,
input awprot,
input awqos,
output awready,
input awregion,
input awsize,
input awvalid,
input bready,
output bresp,
output bvalid,
output rdata,
output rlast,
input rready,
output rresp,
output rvalid,
input wdata,
input wlast,
output wready,
input wstrb,
input wvalid,
input aresetn,
input aclk
);
endinterface: axi4_if
logic [(A-1):0] araddr;
logic [1:0] arburst;
logic [3:0] arcache;
logic [(I-1):0] arid;
logic [7:0] arlen;
logic arlock;
logic [2:0] arprot;
logic [3:0] arqos;
logic arready;
logic [3:0] arregion;
logic [2:0] arsize;
logic arvalid;
logic [(A-1):0] awaddr;
logic [1:0] awburst;
logic [3:0] awcache;
logic [(I-1):0] awid;
logic [7:0] awlen;
logic awlock;
logic [2:0] awprot;
logic [3:0] awqos;
logic awready;
logic [3:0] awregion;
logic [2:0] awsize;
logic awvalid;
logic [(I-1):0] bid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(8*N)-1:0] rdata;
logic [(I-1):0] rid;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(8*N)-1:0] wdata;
logic [(I-1):0] wid;
logic wlast;
logic wready;
logic [N-1:0] wstrb;
logic wvalid;
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 
/src/axi4_register_slice.sv
0,0 → 1,182
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_register_slice
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_s,
axi4_if axi4_m,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
wire ar_rd_empty;
wire ar_rd_en = axi4_m.arvalid & axi4_m.arready;
wire r_wr_full;
wire r_wr_en = axi4_m.rvalid & axi4_m.rready;
 
axi4_if #(.A(A), .N(N), .I(I))
axi4_read_fifo(.*);
 
 
// --------------------------------------------------------------------
//
axi4_to_read_fifos
#(
.A(A),
.N(N),
.I(I),
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
)
axi4_to_read_fifos_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axi4_m.arid = axi4_read_fifo.arid;
assign axi4_m.araddr = axi4_read_fifo.araddr;
assign axi4_m.arburst = axi4_read_fifo.arburst;
assign axi4_m.arlen = axi4_read_fifo.arlen;
assign axi4_m.arsize = axi4_read_fifo.arsize;
assign axi4_m.arvalid = ~ar_rd_empty;
 
generate
begin: ar_assign_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign axi4_m.arcache = axi4_read_fifo.arcache;
assign axi4_m.arlock = axi4_read_fifo.arlock;
assign axi4_m.arprot = axi4_read_fifo.arprot;
assign axi4_m.arqos = axi4_read_fifo.arqos;
assign axi4_m.arregion = axi4_read_fifo.arregion;
end
else
begin
assign axi4_m.arcache = 0;
assign axi4_m.arlock = 0;
assign axi4_m.arprot = 0;
assign axi4_m.arqos = 0;
assign axi4_m.arregion = 0;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axi4_m.rready = ~r_wr_full;
assign axi4_read_fifo.rdata = axi4_m.rdata;
assign axi4_read_fifo.rid = axi4_m.rid;
assign axi4_read_fifo.rlast = axi4_m.rlast;
assign axi4_read_fifo.rresp = axi4_m.rresp;
 
 
// --------------------------------------------------------------------
//
wire aw_rd_empty;
wire aw_rd_en = axi4_m.awvalid & axi4_m.awready;
wire w_rd_empty;
wire w_rd_en = axi4_m.wvalid & axi4_m.wready;
wire b_wr_full;
wire b_wr_en = axi4_m.bvalid & axi4_m.bready;
 
axi4_if #(.A(A), .N(N), .I(I))
axi4_write_fifo(.*);
 
 
// --------------------------------------------------------------------
//
axi4_to_write_fifos
#(
.A(A),
.N(N),
.I(I),
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
)
axi4_to_write_fifos_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axi4_m.awid = axi4_write_fifo.awid;
assign axi4_m.awaddr = axi4_write_fifo.awaddr;
assign axi4_m.awburst = axi4_write_fifo.awburst;
assign axi4_m.awlen = axi4_write_fifo.awlen;
assign axi4_m.awsize = axi4_write_fifo.awsize;
assign axi4_m.awvalid = ~aw_rd_empty;
 
generate
begin: aw_assign_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign axi4_m.awcache = axi4_write_fifo.awcache;
assign axi4_m.awlock = axi4_write_fifo.awlock;
assign axi4_m.awprot = axi4_write_fifo.awprot;
assign axi4_m.awqos = axi4_write_fifo.awqos;
assign axi4_m.awregion = axi4_write_fifo.awregion;
end
else
begin
assign axi4_m.awcache = 0;
assign axi4_m.awlock = 0;
assign axi4_m.awprot = 0;
assign axi4_m.awqos = 0;
assign axi4_m.awregion = 0;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axi4_m.wvalid = ~w_rd_empty;
assign axi4_m.wdata = axi4_write_fifo.wdata;
assign axi4_m.wid = axi4_write_fifo.wid;
assign axi4_m.wlast = axi4_write_fifo.wlast;
assign axi4_m.wstrb = axi4_write_fifo.wstrb;
 
 
// --------------------------------------------------------------------
//
assign axi4_m.bready = ~b_wr_full;
assign axi4_write_fifo.bid = axi4_m.bid;
assign axi4_write_fifo.bresp = axi4_m.bresp;
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/src/axi4_to_read_fifos.sv
0,0 → 1,202
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_to_read_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_s,
axi4_if axi4_read_fifo,
 
output ar_rd_empty,
input ar_rd_en,
output r_wr_full,
input r_wr_en,
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam R_W =
8*N + // logic [(8*N)-1:0] rdata;
I + // logic [(I-1):0] rid;
1 + // logic rlast;
2; // logic [1:0] rresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AR_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AR_W-1:0] ar_rd_data;
wire [AR_W-1:0] ar_wr_data;
 
generate
begin: ar_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign ar_wr_data =
{
axi4_s.araddr,
axi4_s.arburst,
axi4_s.arid,
axi4_s.arlen,
axi4_s.arsize,
axi4_s.arcache,
axi4_s.arlock,
axi4_s.arprot,
axi4_s.arqos,
axi4_s.arregion
};
 
assign
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize,
axi4_read_fifo.arcache,
axi4_read_fifo.arlock,
axi4_read_fifo.arprot,
axi4_read_fifo.arqos,
axi4_read_fifo.arregion
} = ar_rd_data;
end
else
begin
assign ar_wr_data =
{
axi4_s.araddr,
axi4_s.arburst,
axi4_s.arid,
axi4_s.arlen,
axi4_s.arsize
};
 
assign
{
axi4_read_fifo.araddr,
axi4_read_fifo.arburst,
axi4_read_fifo.arid,
axi4_read_fifo.arlen,
axi4_read_fifo.arsize
} = ar_rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire ar_wr_full;
wire ar_wr_en = axi4_s.arready & axi4_s.arvalid;
assign axi4_s.arready = ~ar_wr_full;
 
tiny_sync_fifo #(.W(AR_W))
ar_fifo
(
.wr_full(ar_wr_full),
.wr_data(ar_wr_data),
.wr_en(ar_wr_en),
.rd_empty(ar_rd_empty),
.rd_data(ar_rd_data),
.rd_en(ar_rd_en),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [R_W-1:0] r_rd_data;
wire [R_W-1:0] r_wr_data;
 
assign r_wr_data =
{
axi4_read_fifo.rdata,
axi4_read_fifo.rid,
axi4_read_fifo.rlast,
axi4_read_fifo.rresp
};
 
assign
{
axi4_s.rdata,
axi4_s.rid,
axi4_s.rlast,
axi4_s.rresp
} = r_rd_data;
 
 
// --------------------------------------------------------------------
//
wire r_rd_empty;
wire r_rd_en = axi4_s.rready & axi4_s.rvalid;
assign axi4_s.rvalid = ~r_rd_empty;
 
 
tiny_sync_fifo #(.W(R_W))
r_fifo
(
.wr_full(r_wr_full),
.wr_data(r_wr_data),
.wr_en(r_wr_en),
.rd_empty(r_rd_empty),
.rd_data(r_rd_data),
.rd_en(r_rd_en),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 
/src/axi4_to_write_fifos.sv
0,0 → 1,245
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
axi4_to_write_fifos
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
I = 1, // ID width
USE_ADVANCED_PROTOCOL = 0
)
(
axi4_if axi4_s,
axi4_if axi4_write_fifo,
 
output aw_rd_empty,
input aw_rd_en,
output w_rd_empty,
input w_rd_en,
output b_wr_full,
input b_wr_en,
 
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
//
localparam W_W =
8*N + // logic [(8*N)-1:0] wdata;
I + // logic [(I-1):0] wid;
1 + // logic wlast;
N; // logic [N-1:0] wstrb;
 
localparam B_W =
I + // logic [(I-1):0] bid;
2; // logic [1:0] bresp;
 
localparam AX_BASIC_W =
A + // logic [(A-1):0] axaddr;
2 + // logic [1:0] axburst;
I + // logic [(I-1):0] axid;
8 + // logic [7:0] axlen;
3; // logic [2:0] axsize;
 
localparam AX_ADVANCED_W =
4 + // logic [3:0] axcache;
1 + // logic axlock;
3 + // logic [2:0] axprot;
4 + // logic [3:0] axqos;
4; // logic [3:0] axregion;
 
localparam AW_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
 
 
// --------------------------------------------------------------------
//
wire [AW_W-1:0] aw_rd_data;
wire [AW_W-1:0] aw_wr_data;
 
generate
begin: aw_data_gen
if(USE_ADVANCED_PROTOCOL)
begin
assign aw_wr_data =
{
axi4_s.awaddr,
axi4_s.awburst,
axi4_s.awid,
axi4_s.awlen,
axi4_s.awsize,
axi4_s.awcache,
axi4_s.awlock,
axi4_s.awprot,
axi4_s.awqos,
axi4_s.awregion
};
 
assign
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize,
axi4_write_fifo.awcache,
axi4_write_fifo.awlock,
axi4_write_fifo.awprot,
axi4_write_fifo.awqos,
axi4_write_fifo.awregion
} = aw_rd_data;
end
else
begin
assign aw_wr_data =
{
axi4_s.awaddr,
axi4_s.awburst,
axi4_s.awid,
axi4_s.awlen,
axi4_s.awsize
};
 
assign
{
axi4_write_fifo.awaddr,
axi4_write_fifo.awburst,
axi4_write_fifo.awid,
axi4_write_fifo.awlen,
axi4_write_fifo.awsize
} = aw_rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
wire aw_wr_full;
wire aw_wr_en = axi4_s.awready & axi4_s.awvalid;
assign axi4_s.awready = ~aw_wr_full;
 
tiny_sync_fifo #(.W(AW_W))
aw_fifo
(
.wr_full(aw_wr_full),
.wr_data(aw_wr_data),
.wr_en(aw_wr_en),
.rd_empty(aw_rd_empty),
.rd_data(aw_rd_data),
.rd_en(aw_rd_en),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [W_W-1:0] w_rd_data;
wire [W_W-1:0] w_wr_data;
 
assign w_wr_data =
{
axi4_s.wdata,
axi4_s.wid,
axi4_s.wlast,
axi4_s.wstrb
};
 
assign
{
axi4_write_fifo.wdata,
axi4_write_fifo.wid,
axi4_write_fifo.wlast,
axi4_write_fifo.wstrb
} = w_rd_data;
 
 
// --------------------------------------------------------------------
//
wire w_wr_full;
wire w_wr_en = axi4_s.wready & axi4_s.wvalid;
assign axi4_s.wready = ~w_wr_full;
 
tiny_sync_fifo #(.W(W_W))
w_fifo
(
.wr_full(w_wr_full),
.wr_data(w_wr_data),
.wr_en(w_wr_en),
.rd_empty(w_rd_empty),
.rd_data(w_rd_data),
.rd_en(w_rd_en),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
wire [B_W-1:0] b_rd_data;
wire [B_W-1:0] b_wr_data;
 
assign b_wr_data =
{
axi4_write_fifo.bid,
axi4_write_fifo.bresp
};
 
assign
{
axi4_s.bid,
axi4_s.bresp
} = b_rd_data;
 
 
// --------------------------------------------------------------------
//
wire b_rd_empty;
wire b_rd_en = axi4_s.bready & axi4_s.bvalid;
assign axi4_s.bvalid = ~b_rd_empty;
 
tiny_sync_fifo #(.W(B_W))
b_fifo
(
.wr_full(b_wr_full),
.wr_data(b_wr_data),
.wr_en(b_wr_en),
.rd_empty(b_rd_empty),
.rd_data(b_rd_data),
.rd_en(b_rd_en),
.clk(aclk),
.reset(~aresetn)
);
 
 
// --------------------------------------------------------------------
//
 
endmodule
 

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