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Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_stream_lib/sim/tests
    from Rev 28 to Rev 31
    ↔ Reverse comparison
  •

Rev 28 → Rev 31

/tb_axis_to_axi4_basic_dma/init_test.do
0,0 → 1,34
# ------------------------------------
#
# ------------------------------------
 
global env
 
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_axis_to_axi4_basic_dma
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all tb_packages
sim_compile_all bfm_packages
sim_compile_all axi4_lib
sim_compile_all qaz_lib
sim_compile_all sim
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
/tb_axis_to_axi4_basic_dma/sim.do
0,0 → 1,13
#
#
 
quit -sim
 
vsim -novopt work.tb_top
 
# log all signals
log -r *
 
# run -all
 
 
/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f
0,0 → 1,12
#
 
${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv
 
${PROJECT_DIR}/sim/src/tb_axis_to_axi4_agent_class_pkg.sv
 
${PROJECT_DIR}/src/axis_to_axi4_basic_dma.sv
 
./${SIM_TB}_pkg.sv
./${SIM_TB}.sv
 
/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv
0,0 → 1,115
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module tb_top();
 
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
 
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
 
 
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
 
sync_reset
sync_reset_i(aclk, tb_rst, tb_rst_s);
 
 
// --------------------------------------------------------------------
//
import tb_axis_to_axi4_basic_dma_pkg::*;
 
 
// --------------------------------------------------------------------
//
axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*);
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*);
 
 
// --------------------------------------------------------------------
//
logic dma_enable = 0;
 
axis_to_axi4_basic_dma
#(
.A(A),
.N(N),
.I(I),
.BASE_ADDRESS(BASE_ADDRESS),
.BUFFER_SIZE(BUFFER_SIZE),
.BURST_LENGTH(BURST_LENGTH),
.MAX_BURSTS(MAX_BURSTS),
.BYTES_PER_TUSER(BYTES_PER_TUSER)
)
dut(.*);
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
 
// --------------------------------------------------------------------
//
axi4_checker #(.A(A), .N(N), .MAXWAITS(64))
axi4_checker_i(.axi4_in(axi4_m));
 
 
// --------------------------------------------------------------------
//
axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64))
axis_checker_i(.axis_in(axis_in));
 
 
// --------------------------------------------------------------------
//
tb_axis_to_axi4_basic_dma_class a_h;
 
initial
a_h = new(axi4_m, axis_in);
 
 
// --------------------------------------------------------------------
//
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// debug wires
 
 
// --------------------------------------------------------------------
// test
the_test test(tb_clk, tb_rst);
 
initial
begin
 
test.run_the_test();
 
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
 
$display("^^^---------------------------------");
 
$stop();
 
end
 
endmodule
/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv
0,0 → 1,58
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
package tb_axis_to_axi4_basic_dma_pkg;
 
// --------------------------------------------------------------------
//
import tb_axis_to_axi4_agent_class_pkg::*;
 
 
// --------------------------------------------------------------------
//
localparam BASE_ADDRESS = 32'h0000_0000; // must be on 4K boundry
localparam BUFFER_SIZE = 'h800;
localparam BURST_LENGTH = 8'h08;
localparam MAX_BURSTS = 4;
localparam BYTES_PER_TUSER = 2; // bytes per tuser bit. Set to 0 for transfer based.
 
localparam N = 8; // data bus width in bytes
localparam A = 32; // address bus width
localparam I = 1; // ID width
localparam D = 1; // TDEST width
localparam U = N / BYTES_PER_TUSER; // TUSER width
 
 
// --------------------------------------------------------------------
//
class tb_axis_to_axi4_basic_dma_class
extends tb_axis_to_axi4_agent_class #(N, A, I, D, U);
 
 
//--------------------------------------------------------------------
//
function new
(
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m,
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in
);
 
super.new(.axi4_m(axi4_m), .axis_in(axis_in));
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: tb_axis_to_axi4_basic_dma_class
 
// --------------------------------------------------------------------
//
endpackage: tb_axis_to_axi4_basic_dma_pkg
 
 
 
 
 
/tb_axis_to_axi4_basic_dma/the_test.sv
0,0 → 1,60
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
import tb_axis_to_axi4_basic_dma_pkg::*;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.", $time);
$display("^^^---------------------------------");
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(50us);
 
// --------------------------------------------------------------------
wait(tb_top.aresetn);
#200ns;
 
// --------------------------------------------------------------------
force tb_top.dma_enable = 1;
#100ns;
 
// --------------------------------------------------------------------
repeat(8)
begin
tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE, N * BURST_LENGTH);
tb_top.a_h.compare(BASE_ADDRESS);
end
 
// --------------------------------------------------------------------
#200ns;
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
// --------------------------------------------------------------------
//
endmodule
 
/tb_axis_to_axi4_basic_dma/wip.do
0,0 → 1,11
#
 
vlog -f ./tb_axis_to_axi4_basic_dma.f
 
# simulation $root
vlog ./tb_axis_to_axi4_basic_dma.sv
 
# compile test last
vlog ./the_test.sv
 
/tb_axis_upsizer/init_test.do
0,0 → 1,37
# ------------------------------------
#
# ------------------------------------
 
global env
 
set env(ROOT_DIR) ../../../../..
set env(PROJECT_DIR) ../../..
set env(SIM_TARGET) fpga
 
# load sim procedures
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do
 
radix -hexadecimal
 
make_lib work 1
 
sim_compile_all tb_packages
sim_compile_all bfm_packages
sim_compile_all axi4_lib
sim_compile_all qaz_libs
sim_compile_all sim
vlog -f ./tb_axis_upsizer.f
 
# simulation $root
vlog $env(PROJECT_DIR)/sim/src/tb_axis_upsizer.sv
 
# compile test last
vlog ./the_test.sv
 
# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top
 
# run the sim
sim_run_test
 
 
 
/tb_axis_upsizer/sim.do
0,0 → 1,16
#
#
 
 
quit -sim
 
# vsim opt_tb_top
vsim -novopt work.tb_top
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top
 
# log all signals
log -r *
 
# run -all
 
 
/tb_axis_upsizer/tb_axis_upsizer.f
0,0 → 1,6
#
 
${PROJECT_DIR}/sim/src/tb_axis_upsizer_agent_class_pkg.sv
${PROJECT_DIR}/sim/src/tb_axis_upsizer_class_pkg.sv
${PROJECT_DIR}/src/axis_upsizer.sv
/tb_axis_upsizer/the_test.sv
0,0 → 1,98
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
module
the_test(
input tb_clk,
input tb_rst
);
 
// --------------------------------------------------------------------
//
int mismatch_count = 0;
 
 
// --------------------------------------------------------------------
//
task run_the_test;
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
 
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(50us);
 
 
// --------------------------------------------------------------------
wait(tb_top.aresetn);
#1us;
 
// --------------------------------------------------------------------
repeat(3) tb_top.a_h.queue_frame("counting");
repeat(3) tb_top.a_h.compare_frame();
 
// --------------------------------------------------------------------
tb_top.a_h.tx_h.make_frame("constant", 16'habba);
tb_top.a_h.queue_frame();
tb_top.a_h.compare_frame();
 
tb_top.a_h.queue_frame("random");
tb_top.a_h.compare_frame();
 
tb_top.a_h.queue_frame("constant", 16'hbeef);
tb_top.a_h.compare_frame();
 
tb_top.a_h.queue_frame("random");
tb_top.a_h.rx_h.wait_for_rx_frames(1);
tb_top.a_h.compare_frame();
 
tb_top.a_h.queue_frame("counting");
tb_top.a_h.compare_frame();
 
repeat(3) tb_top.a_h.queue_frame("random");
repeat(3) tb_top.a_h.compare_frame();
 
// --------------------------------------------------------------------
#1us;
// #6us;
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
endtask
 
 
endmodule
 

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